* @file
* @brief This is the main ia32 firm backend driver.
* @author Christian Wuerdig
- * @version $Id$
*/
-#ifdef HAVE_CONFIG_H
#include "config.h"
-#endif
#include "lc_opts.h"
#include "lc_opts_enum.h"
#include <math.h>
-#include "pseudo_irg.h"
#include "irarch.h"
#include "irgwalk.h"
#include "irprog.h"
#include "irflag.h"
#include "irgmod.h"
#include "irgopt.h"
-#include "irbitset.h"
#include "irgopt.h"
+#include "irdump.h"
#include "pdeq.h"
#include "pset.h"
#include "debug.h"
#include "irtools.h"
#include "iroptimize.h"
#include "instrument.h"
-
-#include "../beabi.h"
-#include "../beirg_t.h"
-#include "../benode_t.h"
-#include "../belower.h"
-#include "../besched_t.h"
+#include "iropt_t.h"
+#include "lower_dw.h"
+#include "lower_calls.h"
+#include "lower_mode_b.h"
+#include "lower_softfloat.h"
+
+#include "beabi.h"
+#include "beirg.h"
+#include "benode.h"
+#include "belower.h"
+#include "besched.h"
#include "be.h"
-#include "../be_t.h"
-#include "../beirgmod.h"
-#include "../be_dbgout.h"
-#include "../beblocksched.h"
-#include "../bemachine.h"
-#include "../beilpsched.h"
-#include "../bespillslots.h"
-#include "../bemodule.h"
-#include "../begnuas.h"
-#include "../bestate.h"
-#include "../beflags.h"
+#include "be_t.h"
+#include "beirgmod.h"
+#include "be_dbgout.h"
+#include "beblocksched.h"
+#include "bespillutil.h"
+#include "bespillslots.h"
+#include "bemodule.h"
+#include "begnuas.h"
+#include "bestate.h"
+#include "beflags.h"
+#include "betranshlp.h"
+#include "belistsched.h"
+#include "beabihelper.h"
+#include "bestack.h"
#include "bearch_ia32_t.h"
#include "ia32_new_nodes.h"
#include "gen_ia32_regalloc_if.h"
-#include "gen_ia32_machine.h"
#include "ia32_common_transform.h"
#include "ia32_transform.h"
#include "ia32_emitter.h"
-#include "ia32_map_regs.h"
#include "ia32_optimize.h"
#include "ia32_x87.h"
#include "ia32_dbg_stat.h"
#include "ia32_finish.h"
-#include "ia32_util.h"
#include "ia32_fpu.h"
#include "ia32_architecture.h"
#ifdef FIRM_GRGEN_BE
#include "ia32_pbqp_transform.h"
-#endif
-DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
+transformer_t be_transformer = TRANSFORMER_DEFAULT;
+#endif
-/* TODO: ugly */
-static set *cur_reg_set = NULL;
+ir_mode *ia32_mode_fpcw;
+ir_mode *ia32_mode_E;
+ir_type *ia32_type_E;
-ir_mode *mode_fpcw = NULL;
-ia32_code_gen_t *ia32_current_cg = NULL;
+/** The current omit-fp state */
+static ir_type *omit_fp_between_type = NULL;
+static ir_type *between_type = NULL;
+static ir_entity *old_bp_ent = NULL;
+static ir_entity *ret_addr_ent = NULL;
+static ir_entity *omit_fp_ret_addr_ent = NULL;
/**
* The environment for the intrinsic mapping.
static ia32_intrinsic_env_t intrinsic_env = {
NULL, /* the isa */
NULL, /* the irg, these entities belong to */
- NULL, /* entity for first div operand (move into FPU) */
- NULL, /* entity for second div operand (move into FPU) */
- NULL, /* entity for converts ll -> d */
- NULL, /* entity for converts d -> ll */
NULL, /* entity for __divdi3 library call */
NULL, /* entity for __moddi3 library call */
NULL, /* entity for __udivdi3 library call */
NULL, /* entity for __umoddi3 library call */
- NULL, /* bias value for conversion from float to unsigned 64 */
};
-typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
+typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
-static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
+/**
+ * Used to create per-graph unique pseudo nodes.
+ */
+static inline ir_node *create_const(ir_graph *irg, ir_node **place,
create_const_node_func func,
const arch_register_t* reg)
{
ir_node *block, *res;
- if(*place != NULL)
+ if (*place != NULL)
return *place;
- block = get_irg_start_block(cg->irg);
- res = func(NULL, cg->irg, block);
- arch_set_irn_register(cg->arch_env, res, reg);
+ block = get_irg_start_block(irg);
+ res = func(NULL, block);
+ arch_set_irn_register(res, reg);
*place = res;
- add_irn_dep(get_irg_end(cg->irg), res);
- /* add_irn_dep(get_irg_start(cg->irg), res); */
-
return res;
}
/* Creates the unique per irg GP NoReg node. */
-ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
- return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
- &ia32_gp_regs[REG_GP_NOREG]);
-}
-
-ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
- return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
- &ia32_vfp_regs[REG_VFP_NOREG]);
-}
-
-ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
- return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
- &ia32_xmm_regs[REG_XMM_NOREG]);
-}
-
-ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
- return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
- &ia32_gp_regs[REG_GP_UKNWN]);
+ir_node *ia32_new_NoReg_gp(ir_graph *irg)
+{
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+ return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
+ &ia32_registers[REG_GP_NOREG]);
}
-ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
- return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
- &ia32_vfp_regs[REG_VFP_UKNWN]);
+ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
+{
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+ return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
+ &ia32_registers[REG_VFP_NOREG]);
}
-ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
- return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
- &ia32_xmm_regs[REG_XMM_UKNWN]);
+ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
+{
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+ return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
+ &ia32_registers[REG_XMM_NOREG]);
}
-ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
- return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
- &ia32_fp_cw_regs[REG_FPCW]);
+ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
+{
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+ return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
+ &ia32_registers[REG_FPCW]);
}
/**
* Returns the admissible noreg register node for input register pos of node irn.
*/
-ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
- const arch_register_req_t *req;
+static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
+{
+ ir_graph *irg = get_irn_irg(irn);
+ const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
- req = arch_get_register_req(cg->arch_env, irn, pos);
assert(req != NULL && "Missing register requirements");
if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
- return ia32_new_NoReg_gp(cg);
+ return ia32_new_NoReg_gp(irg);
if (ia32_cg_config.use_sse2) {
- return ia32_new_NoReg_xmm(cg);
- } else {
- return ia32_new_NoReg_vfp(cg);
- }
-}
-
-/**************************************************
- * _ _ _ __
- * | | | (_)/ _|
- * _ __ ___ __ _ __ _| | | ___ ___ _| |_
- * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
- * | | | __/ (_| | | (_| | | | (_) | (__ | | |
- * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
- * __/ |
- * |___/
- **************************************************/
-
-/**
- * Return register requirements for an ia32 node.
- * If the node returns a tuple (mode_T) then the proj's
- * will be asked for this information.
- */
-static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
- int pos)
-{
- ir_mode *mode = get_irn_mode(node);
- long node_pos;
-
- if (mode == mode_X || is_Block(node)) {
- return arch_no_register_req;
- }
-
- if (mode == mode_T && pos < 0) {
- return arch_no_register_req;
- }
-
- node_pos = pos == -1 ? 0 : pos;
- if (is_Proj(node)) {
- if (mode == mode_M || pos >= 0) {
- return arch_no_register_req;
- }
-
- node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
- node = skip_Proj_const(node);
- }
-
- if (is_ia32_irn(node)) {
- const arch_register_req_t *req;
- if (pos >= 0)
- req = get_ia32_in_req(node, pos);
- else
- req = get_ia32_out_req(node, node_pos);
-
- assert(req != NULL);
-
- return req;
- }
-
- /* unknowns should be transformed already */
- assert(!is_Unknown(node));
- return arch_no_register_req;
-}
-
-static void ia32_set_irn_reg(ir_node *irn, const arch_register_t *reg)
-{
- int pos = 0;
-
- if (get_irn_mode(irn) == mode_X) {
- return;
- }
-
- if (is_Proj(irn)) {
- pos = get_Proj_proj(irn);
- irn = skip_Proj(irn);
- }
-
- if (is_ia32_irn(irn)) {
- const arch_register_t **slots;
-
- slots = get_ia32_slots(irn);
- slots[pos] = reg;
- } else {
- ia32_set_firm_reg(irn, reg, cur_reg_set);
- }
-}
-
-static const arch_register_t *ia32_get_irn_reg(const ir_node *irn)
-{
- int pos = 0;
- const arch_register_t *reg = NULL;
-
- if (is_Proj(irn)) {
-
- if (get_irn_mode(irn) == mode_X) {
- return NULL;
- }
-
- pos = get_Proj_proj(irn);
- irn = skip_Proj_const(irn);
- }
-
- if (is_ia32_irn(irn)) {
- const arch_register_t **slots;
- slots = get_ia32_slots(irn);
- assert(pos < get_ia32_n_res(irn));
- reg = slots[pos];
+ return ia32_new_NoReg_xmm(irg);
} else {
- reg = ia32_get_firm_reg(irn, cur_reg_set);
- }
-
- return reg;
-}
-
-static arch_irn_class_t ia32_classify(const ir_node *irn) {
- arch_irn_class_t classification = arch_irn_class_normal;
-
- irn = skip_Proj_const(irn);
-
- if (is_cfop(irn))
- classification |= arch_irn_class_branch;
-
- if (! is_ia32_irn(irn))
- return classification & ~arch_irn_class_normal;
-
- if (is_ia32_Ld(irn))
- classification |= arch_irn_class_load;
-
- if (is_ia32_St(irn))
- classification |= arch_irn_class_store;
-
- if (is_ia32_need_stackent(irn))
- classification |= arch_irn_class_reload;
-
- return classification;
-}
-
-static arch_irn_flags_t ia32_get_flags(const ir_node *irn) {
- arch_irn_flags_t flags = arch_irn_flags_none;
-
- if (is_Unknown(irn))
- return arch_irn_flags_ignore;
-
- if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
- ir_node *pred = get_Proj_pred(irn);
-
- if(is_ia32_irn(pred)) {
- flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
- }
-
- irn = pred;
+ return ia32_new_NoReg_vfp(irg);
}
-
- if (is_ia32_irn(irn)) {
- flags |= get_ia32_flags(irn);
- }
-
- return flags;
}
/**
*/
typedef struct {
be_abi_call_flags_bits_t flags; /**< The call flags. */
- const arch_env_t *aenv; /**< The architecture environment. */
ir_graph *irg; /**< The associated graph. */
} ia32_abi_env_t;
-static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
+static ir_entity *ia32_get_frame_entity(const ir_node *irn)
+{
return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
}
-static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
- set_ia32_frame_ent(irn, ent);
+static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
+{
+ if (is_be_node(node))
+ be_node_set_frame_entity(node, entity);
+ else
+ set_ia32_frame_ent(node, entity);
}
static void ia32_set_frame_offset(ir_node *irn, int bias)
return;
if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
- ia32_code_gen_t *cg = ia32_current_cg;
- int omit_fp = be_abi_omit_fp(cg->birg->abi);
- if (omit_fp) {
+ ir_graph *irg = get_irn_irg(irn);
+ be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
+ if (layout->sp_relative) {
/* Pop nodes modify the stack pointer before calculating the
* destination address, so fix this here
*/
static int ia32_get_sp_bias(const ir_node *node)
{
+ if (is_ia32_Call(node))
+ return -(int)get_ia32_call_attr_const(node)->pop;
+
if (is_ia32_Push(node))
return 4;
if (is_ia32_Pop(node) || is_ia32_PopMem(node))
return -4;
- return 0;
-}
-
-/**
- * Put all registers which are saved by the prologue/epilogue in a set.
- *
- * @param self The callback object.
- * @param s The result set.
- */
-static void ia32_abi_dont_save_regs(void *self, pset *s)
-{
- ia32_abi_env_t *env = self;
- if(env->flags.try_omit_fp)
- pset_insert_ptr(s, env->aenv->bp);
-}
-
-/**
- * Generate the routine prologue.
- *
- * @param self The callback object.
- * @param mem A pointer to the mem node. Update this if you define new memory.
- * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
- * @param stack_bias Points to the current stack bias, can be modified if needed.
- *
- * @return The register which shall be used as a stack frame base.
- *
- * All nodes which define registers in @p reg_map must keep @p reg_map current.
- */
-static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
-{
- ia32_abi_env_t *env = self;
- ia32_code_gen_t *cg = ia32_current_cg;
- const arch_env_t *arch_env = env->aenv;
-
- if (! env->flags.try_omit_fp) {
- ir_graph *irg =env->irg;
- ir_node *bl = get_irg_start_block(irg);
- ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
- ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
- ir_node *noreg = ia32_new_NoReg_gp(cg);
- ir_node *push;
-
- /* ALL nodes representing bp must be set to ignore. */
- be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
-
- /* push ebp */
- push = new_rd_ia32_Push(NULL, irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
- curr_sp = new_r_Proj(irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
- *mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
-
- /* the push must have SP out register */
- arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
- set_ia32_flags(push, arch_irn_flags_ignore);
-
- /* this modifies the stack bias, because we pushed 32bit */
- *stack_bias -= 4;
-
- /* move esp to ebp */
- curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp);
- be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp);
- arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
- be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
-
- /* beware: the copy must be done before any other sp use */
- curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
- be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), arch_env->sp);
- arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
- be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
-
- be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
- be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
-
- return arch_env->bp;
- }
-
- return arch_env->sp;
-}
-
-/**
- * Generate the routine epilogue.
- * @param self The callback object.
- * @param bl The block for the epilog
- * @param mem A pointer to the mem node. Update this if you define new memory.
- * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
- * @return The register which shall be used as a stack frame base.
- *
- * All nodes which define registers in @p reg_map must keep @p reg_map current.
- */
-static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
-{
- ia32_abi_env_t *env = self;
- const arch_env_t *arch_env = env->aenv;
- ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
- ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
- ir_graph *irg = env->irg;
-
- if (env->flags.try_omit_fp) {
- /* simply remove the stack frame here */
- curr_sp = be_new_IncSP(arch_env->sp, irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
- } else {
- ir_mode *mode_bp = arch_env->bp->reg_class->mode;
-
- if (ia32_cg_config.use_leave) {
- ir_node *leave;
-
- /* leave */
- leave = new_rd_ia32_Leave(NULL, irg, bl, curr_bp);
- set_ia32_flags(leave, arch_irn_flags_ignore);
- curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
- curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
- } else {
- ir_node *pop;
-
- /* the old SP is not needed anymore (kill the proj) */
- assert(is_Proj(curr_sp));
- kill_node(curr_sp);
-
- /* copy ebp to esp */
- curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
- arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
- be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
-
- /* pop ebp */
- pop = new_rd_ia32_Pop(NULL, env->irg, bl, *mem, curr_sp);
- set_ia32_flags(pop, arch_irn_flags_ignore);
- curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
- curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
-
- *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
- }
- arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
- arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
+ if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
+ return SP_BIAS_RESET;
}
- be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
- be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
-}
-
-/**
- * Initialize the callback object.
- * @param call The call object.
- * @param aenv The architecture environment.
- * @param irg The graph with the method.
- * @return Some pointer. This pointer is passed to all other callback functions as self object.
- */
-static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
-{
- ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
- be_abi_call_flags_t fl = be_abi_call_get_flags(call);
- env->flags = fl.bits;
- env->irg = irg;
- env->aenv = aenv;
- return env;
-}
-
-/**
- * Destroy the callback object.
- * @param self The callback object.
- */
-static void ia32_abi_done(void *self) {
- free(self);
+ return 0;
}
/**
- * Produces the type which sits between the stack args and the locals on the stack.
- * it will contain the return address and space to store the old base pointer.
- * @return The Firm type modeling the ABI between type.
+ * Build the between type and entities if not already build.
*/
-static ir_type *ia32_abi_get_between_type(void *self)
+static void ia32_build_between_type(void)
{
#define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
- static ir_type *omit_fp_between_type = NULL;
- static ir_type *between_type = NULL;
-
- ia32_abi_env_t *env = self;
-
if (! between_type) {
- ir_entity *old_bp_ent;
- ir_entity *ret_addr_ent;
- ir_entity *omit_fp_ret_addr_ent;
-
- ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
- ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
+ ir_type *old_bp_type = new_type_primitive(mode_Iu);
+ ir_type *ret_addr_type = new_type_primitive(mode_Iu);
between_type = new_type_struct(IDENT("ia32_between_type"));
old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
set_type_state(omit_fp_between_type, layout_fixed);
}
-
- return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
#undef IDENT
}
+/**
+ * Produces the type which sits between the stack args and the locals on the stack.
+ * it will contain the return address and space to store the old base pointer.
+ * @return The Firm type modeling the ABI between type.
+ */
+static ir_type *ia32_abi_get_between_type(ir_graph *irg)
+{
+ const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
+ ia32_build_between_type();
+ return layout->sp_relative ? omit_fp_between_type : between_type;
+}
+
+/**
+ * Return the stack entity that contains the return address.
+ */
+ir_entity *ia32_get_return_address_entity(ir_graph *irg)
+{
+ const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
+ ia32_build_between_type();
+ return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
+}
+
+/**
+ * Return the stack entity that contains the frame address.
+ */
+ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
+{
+ const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
+ ia32_build_between_type();
+ return layout->sp_relative ? NULL : old_bp_ent;
+}
+
/**
* Get the estimated cycle count for @p irn.
*
cycles.
*/
if (is_ia32_use_frame(irn) || (
- is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
- is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
+ is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
+ is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
)) {
cost += 5;
} else {
* @param obstack The obstack to use for allocation of the returned nodes array
* @return The inverse operation or NULL if operation invertible
*/
-static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
- ir_graph *irg;
+static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
+{
+ (void) irn;
+ (void) i;
+ (void) inverse;
+ (void) obst;
+ return NULL;
+
+#if 0
ir_mode *mode;
ir_mode *irn_mode;
ir_node *block, *noreg, *nomem;
- dbg_info *dbg;
+ dbg_info *dbgi;
/* we cannot invert non-ia32 irns */
if (! is_ia32_irn(irn))
irn);
return NULL;
- irg = get_irn_irg(irn);
block = get_nodes_block(irn);
mode = get_irn_mode(irn);
irn_mode = get_irn_mode(irn);
noreg = get_irn_n(irn, 0);
- nomem = new_r_NoMem(irg);
- dbg = get_irn_dbg_info(irn);
+ nomem = get_irg_no_mem(irg);
+ dbgi = get_irn_dbg_info(irn);
/* initialize structure */
inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
switch (get_ia32_irn_opcode(irn)) {
case iro_ia32_Add:
-#if 0
if (get_ia32_immop_type(irn) == ia32_ImmConst) {
/* we have an add with a const here */
/* invers == add with negated const */
- inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+ inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
/* we have an add with a symconst here */
/* invers == sub with const */
- inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+ inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 2;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal add: inverse == sub */
- inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
+ inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
inverse->costs += 2;
}
-#endif
break;
case iro_ia32_Sub:
-#if 0
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* we have a sub with a const/symconst here */
/* invers == add with this const */
- inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+ inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal sub */
if (i == n_ia32_binary_left) {
- inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
+ inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
}
else {
- inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
+ inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
}
inverse->costs += 1;
}
-#endif
break;
case iro_ia32_Xor:
-#if 0
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* xor with const: inverse = xor */
- inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+ inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal xor */
- inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
+ inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
inverse->costs += 1;
}
-#endif
break;
case iro_ia32_Not: {
- inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
+ inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
case iro_ia32_Neg: {
- inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
+ inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
}
return inverse;
+#endif
}
static ir_mode *get_spill_mode_mode(const ir_mode *mode)
{
- if(mode_is_float(mode))
+ if (mode_is_float(mode))
return mode_D;
return mode_Iu;
*/
static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
{
- if(mode_is_float(mode)) {
- return mode == spillmode;
- } else {
- return 1;
- }
+ return !mode_is_float(mode) || mode == spillmode;
}
/**
* Check if irn can load its operand at position i from memory (source addressmode).
- * @param self Pointer to irn ops itself
* @param irn The irn to be checked
* @param i The operands position
* @return Non-Zero if operand can be loaded
*/
-static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) {
- ir_node *op = get_irn_n(irn, i);
- const ir_mode *mode = get_irn_mode(op);
+static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
+{
+ ir_node *op = get_irn_n(irn, i);
+ const ir_mode *mode = get_irn_mode(op);
const ir_mode *spillmode = get_spill_mode(op);
- if (
- (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
- ! is_ia32_irn(irn) || /* must be an ia32 irn */
- get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
- get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
- ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
- ! ia32_is_spillmode_compatible(mode, spillmode) ||
- is_ia32_use_frame(irn)) /* must not already use frame */
+ if (!is_ia32_irn(irn) || /* must be an ia32 irn */
+ get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
+ !ia32_is_spillmode_compatible(mode, spillmode) ||
+ is_ia32_use_frame(irn)) /* must not already use frame */
return 0;
- if (i == n_ia32_binary_left) {
- const arch_register_req_t *req;
- if(!is_ia32_commutative(irn))
+ switch (get_ia32_am_support(irn)) {
+ case ia32_am_none:
return 0;
- /* we can't swap left/right for limited registers
- * (As this (currently) breaks constraint handling copies)
- */
- req = get_ia32_in_req(irn, n_ia32_binary_left);
- if (req->type & arch_register_req_type_limited) {
- return 0;
- }
+
+ case ia32_am_unary:
+ if (i != n_ia32_unary_op)
+ return 0;
+ break;
+
+ case ia32_am_binary:
+ switch (i) {
+ case n_ia32_binary_left: {
+ const arch_register_req_t *req;
+ if (!is_ia32_commutative(irn))
+ return 0;
+
+ /* we can't swap left/right for limited registers
+ * (As this (currently) breaks constraint handling copies)
+ */
+ req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
+ if (req->type & arch_register_req_type_limited)
+ return 0;
+ break;
+ }
+
+ case n_ia32_binary_right:
+ break;
+
+ default:
+ return 0;
+ }
+ break;
+
+ default:
+ panic("Unknown AM type");
}
+ /* HACK: must not already use "real" memory.
+ * This can happen for Call and Div */
+ if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
+ return 0;
+
return 1;
}
ir_mode *load_mode;
ir_mode *dest_op_mode;
- ia32_code_gen_t *cg = ia32_current_cg;
-
assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
- if (i == n_ia32_binary_left) {
- ia32_swap_left_right(irn);
- }
-
set_ia32_op_type(irn, ia32_AddrModeS);
load_mode = get_irn_mode(get_irn_n(irn, i));
set_ia32_use_frame(irn);
set_ia32_need_stackent(irn);
- set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
- set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
- set_irn_n(irn, n_ia32_mem, spill);
- set_ia32_is_reload(irn);
-
- /* immediates are only allowed on the right side */
- if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
+ if (i == n_ia32_binary_left &&
+ get_ia32_am_support(irn) == ia32_am_binary &&
+ /* immediates are only allowed on the right side */
+ !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
ia32_swap_left_right(irn);
+ i = n_ia32_binary_right;
}
+
+ assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
+
+ set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
+ set_irn_n(irn, n_ia32_mem, spill);
+ set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
+ set_ia32_is_reload(irn);
}
static const be_abi_callbacks_t ia32_abi_callbacks = {
- ia32_abi_init,
- ia32_abi_done,
ia32_abi_get_between_type,
- ia32_abi_dont_save_regs,
- ia32_abi_prologue,
- ia32_abi_epilogue
};
-/* fill register allocator interface */
-
+/* register allocator interface */
static const arch_irn_ops_t ia32_irn_ops = {
- ia32_get_irn_reg_req,
- ia32_set_irn_reg,
- ia32_get_irn_reg,
- ia32_classify,
- ia32_get_flags,
ia32_get_frame_entity,
- ia32_set_frame_entity,
ia32_set_frame_offset,
ia32_get_sp_bias,
ia32_get_inverse,
ia32_perform_memory_operand,
};
-/**************************************************
- * _ _ __
- * | | (_)/ _|
- * ___ ___ __| | ___ __ _ ___ _ __ _| |_
- * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
- * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
- * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
- * __/ |
- * |___/
- **************************************************/
-
static ir_entity *mcount = NULL;
+static int gprof = 0;
-#define ID(s) new_id_from_chars(s, sizeof(s) - 1)
-
-static void ia32_before_abi(void *self) {
- lower_mode_b_config_t lower_mode_b_config = {
- mode_Iu, /* lowered mode */
- mode_Bu, /* prefered mode for set */
- 0, /* don't lower direct compares */
- };
- ia32_code_gen_t *cg = self;
-
- ir_lower_mode_b(cg->irg, &lower_mode_b_config);
- if (cg->dump)
- be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
- if (cg->gprof) {
+static void ia32_before_abi(ir_graph *irg)
+{
+ if (gprof) {
if (mcount == NULL) {
- ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
- mcount = new_entity(get_glob_type(), ID("mcount"), tp);
+ ir_type *tp = new_type_method(0, 0);
+ ident *id = new_id_from_str("mcount");
+ mcount = new_entity(get_glob_type(), id, tp);
/* FIXME: enter the right ld_ident here */
set_entity_ld_ident(mcount, get_entity_ident(mcount));
- set_entity_visibility(mcount, visibility_external_allocated);
+ set_entity_visibility(mcount, ir_visibility_external);
}
- instrument_initcall(cg->irg, mcount);
+ instrument_initcall(irg, mcount);
}
}
-transformer_t be_transformer = TRANSFORMER_DEFAULT;
-
/**
* Transforms the standard firm graph into
* an ia32 firm graph
*/
-static void ia32_prepare_graph(void *self) {
- ia32_code_gen_t *cg = self;
-
- /* do local optimizations */
- optimize_graph_df(cg->irg);
-
- /* TODO: we often have dead code reachable through out-edges here. So for
- * now we rebuild edges (as we need correct user count for code selection)
- */
-#if 1
- edges_deactivate(cg->irg);
- edges_activate(cg->irg);
-#endif
-
- if (cg->dump)
- be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
-
- switch (be_transformer) {
- case TRANSFORMER_DEFAULT:
- /* transform remaining nodes into assembler instructions */
- ia32_transform_graph(cg);
- break;
+static void ia32_prepare_graph(ir_graph *irg)
+{
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
#ifdef FIRM_GRGEN_BE
- case TRANSFORMER_PBQP:
- case TRANSFORMER_RAND:
- /* transform nodes into assembler instructions by PBQP magic */
- ia32_transform_graph_by_pbqp(cg);
- break;
+ switch (be_transformer) {
+ case TRANSFORMER_DEFAULT:
+ /* transform remaining nodes into assembler instructions */
+ ia32_transform_graph(irg);
+ break;
+
+ case TRANSFORMER_PBQP:
+ case TRANSFORMER_RAND:
+ /* transform nodes into assembler instructions by PBQP magic */
+ ia32_transform_graph_by_pbqp(irg);
+ break;
+
+ default:
+ panic("invalid transformer");
+ }
+#else
+ ia32_transform_graph(irg);
#endif
- default: panic("invalid transformer");
- }
-
/* do local optimizations (mainly CSE) */
- optimize_graph_df(cg->irg);
+ optimize_graph_df(irg);
+ /* backend code expects that outedges are always enabled */
+ edges_assure(irg);
- if (cg->dump)
- be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
+ if (irg_data->dump)
+ dump_ir_graph(irg, "transformed");
/* optimize address mode */
- ia32_optimize_graph(cg);
-
- if (cg->dump)
- be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
+ ia32_optimize_graph(irg);
/* do code placement, to optimize the position of constants */
- place_code(cg->irg);
-
- if (cg->dump)
- be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
-}
+ place_code(irg);
+ /* backend code expects that outedges are always enabled */
+ edges_assure(irg);
-/**
- * Dummy functions for hooks we don't need but which must be filled.
- */
-static void ia32_before_sched(void *self) {
- (void) self;
+ if (irg_data->dump)
+ dump_ir_graph(irg, "place");
}
-static void turn_back_am(ir_node *node)
+ir_node *ia32_turn_back_am(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_graph *irg = get_irn_irg(node);
ir_node *block = get_nodes_block(node);
ir_node *base = get_irn_n(node, n_ia32_base);
- ir_node *index = get_irn_n(node, n_ia32_index);
+ ir_node *idx = get_irn_n(node, n_ia32_index);
ir_node *mem = get_irn_n(node, n_ia32_mem);
- ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
- ir_node *load;
- ir_node *load_res;
- ir_node *mem_proj;
- const ir_edge_t *edge;
+ ir_node *noreg;
- load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
- load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
+ ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
+ ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
ia32_copy_am_attrs(load, node);
if (is_ia32_is_reload(node))
set_ia32_is_reload(load);
- set_irn_n(node, n_ia32_mem, new_NoMem());
+ set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
- switch (get_ia32_am_arity(node)) {
+ switch (get_ia32_am_support(node)) {
case ia32_am_unary:
set_irn_n(node, n_ia32_unary_op, load_res);
break;
case ia32_am_binary:
- if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
- assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
- is_ia32_Test(node) || is_ia32_Test8Bit(node));
+ if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
set_irn_n(node, n_ia32_binary_left, load_res);
} else {
set_irn_n(node, n_ia32_binary_right, load_res);
}
break;
- case ia32_am_ternary:
- set_irn_n(node, n_ia32_binary_right, load_res);
- break;
-
- default: break;
+ default:
+ panic("Unknown AM type");
}
- set_irn_n(node, n_ia32_base, noreg);
+ noreg = ia32_new_NoReg_gp(current_ir_graph);
+ set_irn_n(node, n_ia32_base, noreg);
set_irn_n(node, n_ia32_index, noreg);
set_ia32_am_offs_int(node, 0);
set_ia32_am_sc(node, NULL);
/* rewire mem-proj */
if (get_irn_mode(node) == mode_T) {
- mem_proj = NULL;
+ const ir_edge_t *edge;
foreach_out_edge(node, edge) {
ir_node *out = get_edge_src_irn(edge);
- if(get_irn_mode(out) == mode_M) {
- assert(mem_proj == NULL);
- mem_proj = out;
+ if (get_irn_mode(out) == mode_M) {
+ set_Proj_pred(out, load);
+ set_Proj_proj(out, pn_ia32_Load_M);
+ break;
}
}
-
- if(mem_proj != NULL) {
- set_Proj_pred(mem_proj, load);
- set_Proj_proj(mem_proj, pn_ia32_Load_M);
- }
}
set_ia32_op_type(node, ia32_Normal);
if (sched_is_scheduled(node))
sched_add_before(node, load);
+
+ return load_res;
}
static ir_node *flags_remat(ir_node *node, ir_node *after)
type = get_ia32_op_type(node);
switch (type) {
case ia32_AddrModeS:
- turn_back_am(node);
+ ia32_turn_back_am(node);
break;
case ia32_AddrModeD:
/* TODO implement this later... */
panic("found DestAM with flag user %+F this should not happen", node);
- break;
default: assert(type == ia32_Normal); break;
}
/**
* Called before the register allocator.
*/
-static void ia32_before_ra(void *self) {
- ia32_code_gen_t *cg = self;
-
+static void ia32_before_ra(ir_graph *irg)
+{
/* setup fpu rounding modes */
- ia32_setup_fpu_mode(cg);
+ ia32_setup_fpu_mode(irg);
/* fixup flags */
- be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
- &flags_remat);
+ be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
+ &flags_remat, NULL);
- ia32_add_missing_keeps(cg);
+ be_add_missing_keeps(irg);
}
/**
* Transforms a be_Reload into a ia32 Load.
*/
-static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
+static void transform_to_Load(ir_node *node)
+{
ir_graph *irg = get_irn_irg(node);
- dbg_info *dbg = get_irn_dbg_info(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_entity *ent = be_get_frame_entity(node);
ir_mode *mode = get_irn_mode(node);
ir_mode *spillmode = get_spill_mode(node);
- ir_node *noreg = ia32_new_NoReg_gp(cg);
+ ir_node *noreg = ia32_new_NoReg_gp(irg);
ir_node *sched_point = NULL;
ir_node *ptr = get_irg_frame(irg);
- ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
+ ir_node *mem = get_irn_n(node, n_be_Reload_mem);
ir_node *new_op, *proj;
const arch_register_t *reg;
if (mode_is_float(spillmode)) {
if (ia32_cg_config.use_sse2)
- new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
+ new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
else
- new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
+ new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
}
else if (get_mode_size_bits(spillmode) == 128) {
/* Reload 128 bit SSE registers */
- new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
+ new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
}
else
- new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
+ new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
set_ia32_op_type(new_op, ia32_AddrModeS);
set_ia32_ls_mode(new_op, spillmode);
DBG_OPT_RELOAD2LD(node, new_op);
- proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
+ proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
if (sched_point) {
sched_add_after(sched_point, new_op);
}
/* copy the register from the old node to the new Load */
- reg = arch_get_irn_register(cg->arch_env, node);
- arch_set_irn_register(cg->arch_env, new_op, reg);
+ reg = arch_get_irn_register(node);
+ arch_set_irn_register(proj, reg);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
+ SET_IA32_ORIG_NODE(new_op, node);
exchange(node, proj);
}
/**
* Transforms a be_Spill node into a ia32 Store.
*/
-static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
+static void transform_to_Store(ir_node *node)
+{
ir_graph *irg = get_irn_irg(node);
- dbg_info *dbg = get_irn_dbg_info(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_entity *ent = be_get_frame_entity(node);
- const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
+ const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
ir_mode *mode = get_spill_mode(spillval);
- ir_node *noreg = ia32_new_NoReg_gp(cg);
- ir_node *nomem = new_rd_NoMem(irg);
+ ir_node *noreg = ia32_new_NoReg_gp(irg);
+ ir_node *nomem = get_irg_no_mem(irg);
ir_node *ptr = get_irg_frame(irg);
- ir_node *val = get_irn_n(node, be_pos_Spill_val);
+ ir_node *val = get_irn_n(node, n_be_Spill_val);
+ ir_node *res;
ir_node *store;
ir_node *sched_point = NULL;
sched_point = sched_prev(node);
}
- /* No need to spill unknown values... */
- if(is_ia32_Unknown_GP(val) ||
- is_ia32_Unknown_VFP(val) ||
- is_ia32_Unknown_XMM(val)) {
- store = nomem;
- if(sched_point)
- sched_remove(node);
-
- exchange(node, store);
- return;
- }
-
if (mode_is_float(mode)) {
- if (ia32_cg_config.use_sse2)
- store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
- else
- store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
+ if (ia32_cg_config.use_sse2) {
+ store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
+ res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
+ } else {
+ store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
+ res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
+ }
} else if (get_mode_size_bits(mode) == 128) {
/* Spill 128 bit SSE registers */
- store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
+ store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
+ res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
} else if (get_mode_size_bits(mode) == 8) {
- store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
+ store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
+ res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
} else {
- store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
+ store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
+ res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
}
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_frame_ent(store, ent);
set_ia32_use_frame(store);
set_ia32_is_spill(store);
- SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
+ SET_IA32_ORIG_NODE(store, node);
DBG_OPT_SPILL2ST(node, store);
if (sched_point) {
sched_remove(node);
}
- exchange(node, store);
+ exchange(node, res);
}
-static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
- ir_graph *irg = get_irn_irg(node);
- dbg_info *dbg = get_irn_dbg_info(node);
- ir_node *block = get_nodes_block(node);
- ir_node *noreg = ia32_new_NoReg_gp(cg);
- ir_node *frame = get_irg_frame(irg);
+static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
+{
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *noreg = ia32_new_NoReg_gp(irg);
+ ir_node *frame = get_irg_frame(irg);
- ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
+ ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
set_ia32_frame_ent(push, ent);
set_ia32_use_frame(push);
set_ia32_op_type(push, ia32_AddrModeS);
set_ia32_ls_mode(push, mode_Is);
+ set_ia32_is_spill(push);
sched_add_before(schedpoint, push);
return push;
}
-static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
- ir_graph *irg = get_irn_irg(node);
- dbg_info *dbg = get_irn_dbg_info(node);
- ir_node *block = get_nodes_block(node);
- ir_node *noreg = ia32_new_NoReg_gp(cg);
- ir_node *frame = get_irg_frame(irg);
+static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
+{
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *noreg = ia32_new_NoReg_gp(irg);
+ ir_node *frame = get_irg_frame(irg);
- ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp);
+ ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
+ get_irg_no_mem(irg), sp);
set_ia32_frame_ent(pop, ent);
set_ia32_use_frame(pop);
set_ia32_op_type(pop, ia32_AddrModeD);
set_ia32_ls_mode(pop, mode_Is);
+ set_ia32_is_reload(pop);
sched_add_before(schedpoint, pop);
return pop;
}
-static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
- ir_graph *irg = get_irn_irg(node);
- dbg_info *dbg = get_irn_dbg_info(node);
- ir_node *block = get_nodes_block(node);
- ir_mode *spmode = mode_Iu;
- const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
+static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
+{
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *spmode = mode_Iu;
+ const arch_register_t *spreg = &ia32_registers[REG_ESP];
ir_node *sp;
- sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
- arch_set_irn_register(cg->arch_env, sp, spreg);
+ sp = new_rd_Proj(dbgi, pred, spmode, pos);
+ arch_set_irn_register(sp, spreg);
return sp;
}
* push/pop into/from memory cascades. This is possible without using
* any registers.
*/
-static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
- ir_graph *irg = get_irn_irg(node);
- ir_node *block = get_nodes_block(node);
- ir_node *in[1];
- ir_node *keep;
- int i, arity;
- ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
+static void transform_MemPerm(ir_node *node)
+{
+ ir_node *block = get_nodes_block(node);
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
+ int arity = be_get_MemPerm_entity_arity(node);
+ ir_node **pops = ALLOCAN(ir_node*, arity);
+ ir_node *in[1];
+ ir_node *keep;
+ int i;
const ir_edge_t *edge;
const ir_edge_t *next;
- ir_node **pops;
-
- arity = be_get_MemPerm_entity_arity(node);
- pops = alloca(arity * sizeof(pops[0]));
/* create Pushs */
- for(i = 0; i < arity; ++i) {
+ for (i = 0; i < arity; ++i) {
ir_entity *inent = be_get_MemPerm_in_entity(node, i);
ir_entity *outent = be_get_MemPerm_out_entity(node, i);
ir_type *enttype = get_entity_type(inent);
ir_node *push;
/* work around cases where entities have different sizes */
- if(entsize2 < entsize)
+ if (entsize2 < entsize)
entsize = entsize2;
assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
- push = create_push(cg, node, node, sp, mem, inent);
- sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
- if(entsize == 8) {
+ push = create_push(node, node, sp, mem, inent);
+ sp = create_spproj(node, push, pn_ia32_Push_stack);
+ if (entsize == 8) {
/* add another push after the first one */
- push = create_push(cg, node, node, sp, mem, inent);
+ push = create_push(node, node, sp, mem, inent);
add_ia32_am_offs_int(push, 4);
- sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
+ sp = create_spproj(node, push, pn_ia32_Push_stack);
}
- set_irn_n(node, i, new_Bad());
+ set_irn_n(node, i, new_r_Bad(irg, mode_X));
}
/* create pops */
- for(i = arity - 1; i >= 0; --i) {
+ for (i = arity - 1; i >= 0; --i) {
ir_entity *inent = be_get_MemPerm_in_entity(node, i);
ir_entity *outent = be_get_MemPerm_out_entity(node, i);
ir_type *enttype = get_entity_type(outent);
ir_node *pop;
/* work around cases where entities have different sizes */
- if(entsize2 < entsize)
+ if (entsize2 < entsize)
entsize = entsize2;
assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
- pop = create_pop(cg, node, node, sp, outent);
- sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
- if(entsize == 8) {
+ pop = create_pop(node, node, sp, outent);
+ sp = create_spproj(node, pop, pn_ia32_Pop_stack);
+ if (entsize == 8) {
add_ia32_am_offs_int(pop, 4);
/* add another pop after the first one */
- pop = create_pop(cg, node, node, sp, outent);
- sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
+ pop = create_pop(node, node, sp, outent);
+ sp = create_spproj(node, pop, pn_ia32_Pop_stack);
}
pops[i] = pop;
}
in[0] = sp;
- keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
+ keep = be_new_Keep(block, 1, in);
sched_add_before(node, keep);
/* exchange memprojs */
}
/* remove memperm */
- arity = get_irn_arity(node);
- for(i = 0; i < arity; ++i) {
- set_irn_n(node, i, new_Bad());
- }
sched_remove(node);
+ kill_node(node);
}
/**
* Block-Walker: Calls the transform functions Spill and Reload.
*/
-static void ia32_after_ra_walker(ir_node *block, void *env) {
+static void ia32_after_ra_walker(ir_node *block, void *env)
+{
ir_node *node, *prev;
- ia32_code_gen_t *cg = env;
+ (void) env;
/* beware: the schedule is changed here */
for (node = sched_last(block); !sched_is_begin(node); node = prev) {
prev = sched_prev(node);
if (be_is_Reload(node)) {
- transform_to_Load(cg, node);
+ transform_to_Load(node);
} else if (be_is_Spill(node)) {
- transform_to_Store(cg, node);
+ transform_to_Store(node);
} else if (be_is_MemPerm(node)) {
- transform_MemPerm(cg, node);
+ transform_MemPerm(node);
}
}
}
*/
static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
{
- be_fec_env_t *env = data;
+ be_fec_env_t *env = (be_fec_env_t*)data;
+ const ir_mode *mode;
+ int align;
if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
- const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
- int align = get_mode_size_bytes(mode);
- be_node_needs_frame_entity(env, node, mode, align);
- } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
- && is_ia32_use_frame(node)) {
- if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
- const ir_mode *mode = get_ia32_ls_mode(node);
- const ia32_attr_t *attr = get_ia32_attr_const(node);
- int align;
-
- if (is_ia32_is_reload(node)) {
- mode = get_spill_mode_mode(mode);
+ mode = get_spill_mode_mode(get_irn_mode(node));
+ align = get_mode_size_bytes(mode);
+ } else if (is_ia32_irn(node) &&
+ get_ia32_frame_ent(node) == NULL &&
+ is_ia32_use_frame(node)) {
+ if (is_ia32_need_stackent(node))
+ goto need_stackent;
+
+ switch (get_ia32_irn_opcode(node)) {
+need_stackent:
+ case iro_ia32_Load: {
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+
+ if (attr->data.need_32bit_stackent) {
+ mode = mode_Is;
+ } else if (attr->data.need_64bit_stackent) {
+ mode = mode_Ls;
+ } else {
+ mode = get_ia32_ls_mode(node);
+ if (is_ia32_is_reload(node))
+ mode = get_spill_mode_mode(mode);
+ }
+ align = get_mode_size_bytes(mode);
+ break;
}
- if(attr->data.need_64bit_stackent) {
- mode = mode_Ls;
+ case iro_ia32_vfild:
+ case iro_ia32_vfld:
+ case iro_ia32_xLoad: {
+ mode = get_ia32_ls_mode(node);
+ align = 4;
+ break;
}
- if(attr->data.need_32bit_stackent) {
- mode = mode_Is;
+
+ case iro_ia32_FldCW: {
+ /* although 2 byte would be enough 4 byte performs best */
+ mode = mode_Iu;
+ align = 4;
+ break;
}
- align = get_mode_size_bytes(mode);
- be_node_needs_frame_entity(env, node, mode, align);
- } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
- || is_ia32_vfld(node)) {
- const ir_mode *mode = get_ia32_ls_mode(node);
- int align = 4;
- be_node_needs_frame_entity(env, node, mode, align);
- } else if(is_ia32_FldCW(node)) {
- /* although 2 byte would be enough 4 byte performs best */
- const ir_mode *mode = mode_Iu;
- int align = 4;
- be_node_needs_frame_entity(env, node, mode, align);
- } else {
+
+ default:
#ifndef NDEBUG
- assert(is_ia32_St(node) ||
- is_ia32_xStoreSimple(node) ||
- is_ia32_vfst(node) ||
- is_ia32_vfist(node) ||
- is_ia32_vfisttp(node) ||
- is_ia32_FnstCW(node));
+ panic("unexpected frame user while collection frame entity nodes");
+
+ case iro_ia32_FnstCW:
+ case iro_ia32_Store8Bit:
+ case iro_ia32_Store:
+ case iro_ia32_fst:
+ case iro_ia32_fstp:
+ case iro_ia32_vfist:
+ case iro_ia32_vfisttp:
+ case iro_ia32_vfst:
+ case iro_ia32_xStore:
+ case iro_ia32_xStoreSimple:
#endif
+ return;
}
+ } else {
+ return;
+ }
+ be_node_needs_frame_entity(env, node, mode, align);
+}
+
+static int determine_ebp_input(ir_node *ret)
+{
+ const arch_register_t *bp = &ia32_registers[REG_EBP];
+ int arity = get_irn_arity(ret);
+ int i;
+
+ for (i = 0; i < arity; ++i) {
+ ir_node *input = get_irn_n(ret, i);
+ if (arch_get_irn_register(input) == bp)
+ return i;
+ }
+ panic("no ebp input found at %+F", ret);
+}
+
+static void introduce_epilog(ir_node *ret)
+{
+ const arch_register_t *sp = &ia32_registers[REG_ESP];
+ const arch_register_t *bp = &ia32_registers[REG_EBP];
+ ir_graph *irg = get_irn_irg(ret);
+ ir_type *frame_type = get_irg_frame_type(irg);
+ unsigned frame_size = get_type_size_bytes(frame_type);
+ be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
+ ir_node *block = get_nodes_block(ret);
+ ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
+ ir_node *curr_sp = first_sp;
+ ir_mode *mode_gp = mode_Iu;
+
+ if (!layout->sp_relative) {
+ int n_ebp = determine_ebp_input(ret);
+ ir_node *curr_bp = get_irn_n(ret, n_ebp);
+ if (ia32_cg_config.use_leave) {
+ ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
+ curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
+ curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
+ arch_set_irn_register(curr_bp, bp);
+ arch_set_irn_register(curr_sp, sp);
+ sched_add_before(ret, leave);
+ } else {
+ ir_node *pop;
+ ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
+ /* copy ebp to esp */
+ curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
+ arch_set_irn_register(curr_sp, sp);
+ sched_add_before(ret, curr_sp);
+
+ /* pop ebp */
+ pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
+ curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
+ curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
+ curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
+ arch_set_irn_register(curr_bp, bp);
+ arch_set_irn_register(curr_sp, sp);
+ sched_add_before(ret, pop);
+
+ set_irn_n(ret, n_be_Return_mem, curr_mem);
+ }
+ set_irn_n(ret, n_ebp, curr_bp);
+ } else {
+ ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
+ sched_add_before(ret, incsp);
+ curr_sp = incsp;
+ }
+ set_irn_n(ret, n_be_Return_sp, curr_sp);
+
+ /* keep verifier happy... */
+ if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
+ kill_node(first_sp);
}
}
/**
- * We transform Spill and Reload here. This needs to be done before
- * stack biasing otherwise we would miss the corrected offset for these nodes.
+ * put the Prolog code at the beginning, epilog code before each return
*/
-static void ia32_after_ra(void *self) {
- ia32_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
- be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
+static void introduce_prolog_epilog(ir_graph *irg)
+{
+ const arch_register_t *sp = &ia32_registers[REG_ESP];
+ const arch_register_t *bp = &ia32_registers[REG_EBP];
+ ir_node *start = get_irg_start(irg);
+ ir_node *block = get_nodes_block(start);
+ ir_type *frame_type = get_irg_frame_type(irg);
+ unsigned frame_size = get_type_size_bytes(frame_type);
+ be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
+ ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
+ ir_node *curr_sp = initial_sp;
+ ir_mode *mode_gp = mode_Iu;
+
+ if (!layout->sp_relative) {
+ /* push ebp */
+ ir_node *mem = get_irg_initial_mem(irg);
+ ir_node *noreg = ia32_new_NoReg_gp(irg);
+ ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
+ ir_node *curr_bp = initial_bp;
+ ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
+ ir_node *incsp;
+
+ curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
+ mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
+ arch_set_irn_register(curr_sp, sp);
+ sched_add_after(start, push);
- /* create and coalesce frame entities */
- irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
- be_assign_entities(fec_env);
- be_free_frame_entity_coalescer(fec_env);
+ /* move esp to ebp */
+ curr_bp = be_new_Copy(block, curr_sp);
+ sched_add_after(push, curr_bp);
+ be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
+ curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
+ sched_add_after(curr_bp, curr_sp);
+ be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
+ edges_reroute(initial_bp, curr_bp);
+ set_irn_n(push, n_ia32_Push_val, initial_bp);
+
+ incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
+ edges_reroute(initial_sp, incsp);
+ set_irn_n(push, n_ia32_Push_stack, initial_sp);
+ sched_add_after(curr_sp, incsp);
+
+ /* make sure the initial IncSP is really used by someone */
+ if (get_irn_n_edges(incsp) <= 1) {
+ ir_node *in[] = { incsp };
+ ir_node *keep = be_new_Keep(block, 1, in);
+ sched_add_after(incsp, keep);
+ }
- irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
+ layout->initial_bias = -4;
+ } else {
+ ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
+ edges_reroute(initial_sp, incsp);
+ be_set_IncSP_pred(incsp, curr_sp);
+ sched_add_after(start, incsp);
+ }
+
+ /* introduce epilog for every return node */
+ {
+ ir_node *end_block = get_irg_end_block(irg);
+ int arity = get_irn_arity(end_block);
+ int i;
+
+ for (i = 0; i < arity; ++i) {
+ ir_node *ret = get_irn_n(end_block, i);
+ assert(be_is_Return(ret));
+ introduce_epilog(ret);
+ }
+ }
}
/**
* virtual with real x87 instructions, creating a block schedule and peephole
* optimisations.
*/
-static void ia32_finish(void *self) {
- ia32_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
+static void ia32_finish(ir_graph *irg)
+{
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+ be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
+ bool at_begin = stack_layout->sp_relative ? true : false;
+ be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
+
+ /* create and coalesce frame entities */
+ irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
+ be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
+ be_free_frame_entity_coalescer(fec_env);
+
+ irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
- ia32_finish_irg(irg, cg);
+ introduce_prolog_epilog(irg);
+
+ /* fix stack entity offsets */
+ be_abi_fix_stack_nodes(irg);
+ be_abi_fix_stack_bias(irg);
+
+ /* fix 2-address code constraints */
+ ia32_finish_irg(irg);
/* we might have to rewrite x87 virtual registers */
- if (cg->do_x87_sim) {
- x87_simulate_graph(cg->arch_env, cg->birg);
+ if (irg_data->do_x87_sim) {
+ ia32_x87_simulate_graph(irg);
}
/* do peephole optimisations */
- ia32_peephole_optimization(cg);
+ ia32_peephole_optimization(irg);
+
+ be_remove_dead_nodes_from_schedule(irg);
/* create block schedule, this also removes empty blocks which might
* produce critical edges */
- cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
+ irg_data->blk_sched = be_create_block_schedule(irg);
}
/**
* Emits the code, closes the output file and frees
* the code generator interface.
*/
-static void ia32_codegen(void *self) {
- ia32_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
-
- ia32_gen_routine(cg, irg);
-
- cur_reg_set = NULL;
-
- /* remove it from the isa */
- cg->isa->cg = NULL;
-
- assert(ia32_current_cg == cg);
- ia32_current_cg = NULL;
-
- /* de-allocate code generator */
- del_set(cg->reg_set);
- free(cg);
+static void ia32_emit(ir_graph *irg)
+{
+ if (ia32_cg_config.emit_machcode) {
+ ia32_gen_binary_routine(irg);
+ } else {
+ ia32_gen_routine(irg);
+ }
}
/**
* Returns the node representing the PIC base.
*/
-static ir_node *ia32_get_pic_base(void *self) {
+static ir_node *ia32_get_pic_base(ir_graph *irg)
+{
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
ir_node *block;
- ia32_code_gen_t *cg = self;
- ir_node *get_eip = cg->get_eip;
+ ir_node *get_eip = irg_data->get_eip;
if (get_eip != NULL)
return get_eip;
- block = get_irg_start_block(cg->irg);
- get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block);
- cg->get_eip = get_eip;
-
- add_irn_dep(get_eip, get_irg_frame(cg->irg));
+ block = get_irg_start_block(irg);
+ get_eip = new_bd_ia32_GetEIP(NULL, block);
+ irg_data->get_eip = get_eip;
return get_eip;
}
-static void *ia32_cg_init(be_irg_t *birg);
-
-static const arch_code_generator_if_t ia32_code_gen_if = {
- ia32_cg_init,
- ia32_get_pic_base, /* return node used as base in pic code addresses */
- ia32_before_abi, /* before abi introduce hook */
- ia32_prepare_graph,
- NULL, /* spill */
- ia32_before_sched, /* before scheduling hook */
- ia32_before_ra, /* before register allocation hook */
- ia32_after_ra, /* after register allocation hook */
- ia32_finish, /* called before codegen */
- ia32_codegen /* emit && done */
-};
-
/**
* Initializes a IA32 code generator.
*/
-static void *ia32_cg_init(be_irg_t *birg) {
- ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
- ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
-
- cg->impl = &ia32_code_gen_if;
- cg->irg = birg->irg;
- cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
- cg->isa = isa;
- cg->arch_env = birg->main_env->arch_env;
- cg->birg = birg;
- cg->blk_sched = NULL;
- cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
- cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
-
- if (cg->gprof) {
- /* Linux gprof implementation needs base pointer */
- birg->main_env->options->omit_fp = 0;
- }
+static void ia32_init_graph(ir_graph *irg)
+{
+ struct obstack *obst = be_get_be_obst(irg);
+ ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
- /* enter it */
- isa->cg = cg;
+ irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
-#ifndef NDEBUG
- if (isa->name_obst) {
- obstack_free(isa->name_obst, NULL);
- obstack_init(isa->name_obst);
+ if (gprof) {
+ /* Linux gprof implementation needs base pointer */
+ be_get_irg_options(irg)->omit_fp = 0;
}
-#endif /* NDEBUG */
- cur_reg_set = cg->reg_set;
-
- assert(ia32_current_cg == NULL);
- ia32_current_cg = cg;
-
- return (arch_code_generator_t *)cg;
+ be_birg_from_irg(irg)->isa_link = irg_data;
}
-
-
-/*****************************************************************
- * ____ _ _ _____ _____
- * | _ \ | | | | |_ _|/ ____| /\
- * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
- * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
- * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
- * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
- *
- *****************************************************************/
-
-/**
- * Set output modes for GCC
- */
static const tarval_mode_info mo_integer = {
TVO_HEX,
"0x",
*/
static void set_tarval_output_modes(void)
{
- int i;
+ size_t i;
- for (i = get_irp_n_modes() - 1; i >= 0; --i) {
- ir_mode *mode = get_irp_mode(i);
+ for (i = get_irp_n_modes(); i > 0;) {
+ ir_mode *mode = get_irp_mode(--i);
if (mode_is_int(mode))
set_tarval_mode_output_option(mode, &mo_integer);
}
}
-const arch_isa_if_t ia32_isa_if;
-
-/**
- * The template that generates a new ISA object.
- * Note that this template can be changed by command line
- * arguments.
- */
-static ia32_isa_t ia32_isa_template = {
- {
- &ia32_isa_if, /* isa interface implementation */
- &ia32_gp_regs[REG_ESP], /* stack pointer register */
- &ia32_gp_regs[REG_EBP], /* base pointer register */
- -1, /* stack direction */
- 2, /* power of two stack alignment, 2^2 == 4 */
- NULL, /* main environment */
- 7, /* costs for a spill instruction */
- 5, /* costs for a reload instruction */
- },
- NULL, /* 16bit register names */
- NULL, /* 8bit register names */
- NULL, /* 8bit register names high */
- NULL, /* types */
- NULL, /* tv_ents */
- NULL, /* current code generator */
- NULL, /* abstract machine */
-#ifndef NDEBUG
- NULL, /* name obstack */
-#endif
-};
+extern const arch_isa_if_t ia32_isa_if;
static void init_asm_constraints(void)
{
}
/**
- * Initializes the backend ISA.
+ * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
*/
-static arch_env_t *ia32_init(FILE *file_handle) {
- static int inited = 0;
- ia32_isa_t *isa;
- int i, n;
+static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
+ ir_node *mux_false)
+{
+ ir_node *cmp_l;
+ ir_node *cmp_r;
+ ir_relation relation;
+
+ if (!is_Cmp(sel))
+ return false;
+
+ cmp_l = get_Cmp_left(sel);
+ cmp_r = get_Cmp_right(sel);
+ if (!mode_is_float(get_irn_mode(cmp_l)))
+ return false;
+
+ /* check for min/max. They're defined as (C-Semantik):
+ * min(a, b) = a < b ? a : b
+ * or min(a, b) = a <= b ? a : b
+ * max(a, b) = a > b ? a : b
+ * or max(a, b) = a >= b ? a : b
+ * (Note we only handle float min/max here)
+ */
+ relation = get_Cmp_relation(sel);
+ switch (relation) {
+ case ir_relation_greater_equal:
+ case ir_relation_greater:
+ /* this is a max */
+ if (cmp_l == mux_true && cmp_r == mux_false)
+ return true;
+ break;
+ case ir_relation_less_equal:
+ case ir_relation_less:
+ /* this is a min */
+ if (cmp_l == mux_true && cmp_r == mux_false)
+ return true;
+ break;
+ case ir_relation_unordered_greater_equal:
+ case ir_relation_unordered_greater:
+ /* this is a min */
+ if (cmp_l == mux_false && cmp_r == mux_true)
+ return true;
+ break;
+ case ir_relation_unordered_less_equal:
+ case ir_relation_unordered_less:
+ /* this is a max */
+ if (cmp_l == mux_false && cmp_r == mux_true)
+ return true;
+ break;
+
+ default:
+ break;
+ }
+
+ return false;
+}
+
+static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
+{
+ ir_mode *mode = get_irn_mode(mux_true);
+ (void) sel;
- if (inited)
- return NULL;
- inited = 1;
+ if (!mode_is_int(mode) && !mode_is_reference(mode)
+ && mode != mode_b)
+ return false;
- set_tarval_output_modes();
+ if (is_Const(mux_true) && is_Const(mux_false)) {
+ /* we can create a set plus up two 3 instructions for any combination
+ * of constants */
+ return true;
+ }
+
+ return false;
+}
- isa = xmalloc(sizeof(*isa));
- memcpy(isa, &ia32_isa_template, sizeof(*isa));
+static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
+ ir_node *mux_false)
+{
+ (void) sel;
+
+ if (!mode_is_float(get_irn_mode(mux_true)))
+ return false;
- if(mode_fpcw == NULL) {
- mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
+ return is_Const(mux_true) && is_Const(mux_false);
+}
+
+static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
+{
+ ir_node *cmp_left;
+ ir_node *cmp_right;
+ ir_node *sub_left;
+ ir_node *sub_right;
+ ir_mode *mode;
+ ir_relation relation;
+
+ if (!is_Cmp(sel))
+ return false;
+
+ mode = get_irn_mode(mux_true);
+ if (mode_is_signed(mode) || mode_is_float(mode))
+ return false;
+
+ relation = get_Cmp_relation(sel);
+ cmp_left = get_Cmp_left(sel);
+ cmp_right = get_Cmp_right(sel);
+
+ /* "move" zero constant to false input */
+ if (is_Const(mux_true) && is_Const_null(mux_true)) {
+ ir_node *tmp = mux_false;
+ mux_false = mux_true;
+ mux_true = tmp;
+ relation = get_negated_relation(relation);
+ }
+ if (!is_Const(mux_false) || !is_Const_null(mux_false))
+ return false;
+ if (!is_Sub(mux_true))
+ return false;
+ sub_left = get_Sub_left(mux_true);
+ sub_right = get_Sub_right(mux_true);
+
+ /* Mux(a >=u b, 0, a-b) */
+ if ((relation & ir_relation_greater)
+ && sub_left == cmp_left && sub_right == cmp_right)
+ return true;
+ /* Mux(a <=u b, 0, b-a) */
+ if ((relation & ir_relation_less)
+ && sub_left == cmp_right && sub_right == cmp_left)
+ return true;
+
+ return false;
+}
+
+static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
+ ir_node *mux_true)
+{
+ ir_mode *mode;
+
+ /* middleend can handle some things */
+ if (ir_is_optimizable_mux(sel, mux_false, mux_true))
+ return true;
+ /* we can handle Set for all modes and compares */
+ if (mux_is_set(sel, mux_true, mux_false))
+ return true;
+ /* SSE has own min/max operations */
+ if (ia32_cg_config.use_sse2
+ && mux_is_float_min_max(sel, mux_true, mux_false))
+ return true;
+ /* we can handle Mux(?, Const[f], Const[f]) */
+ if (mux_is_float_const_const(sel, mux_true, mux_false)) {
+#ifdef FIRM_GRGEN_BE
+ /* well, some code selectors can't handle it */
+ if (be_transformer != TRANSFORMER_PBQP
+ || be_transformer != TRANSFORMER_RAND)
+ return true;
+#else
+ return true;
+#endif
}
- ia32_register_init();
- ia32_create_opcodes(&ia32_irn_ops);
+ /* no support for 64bit inputs to cmov */
+ mode = get_irn_mode(mux_true);
+ if (get_mode_size_bits(mode) > 32)
+ return false;
+ /* we can handle Abs for all modes and compares (except 64bit) */
+ if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
+ return true;
+ /* we can't handle MuxF yet */
+ if (mode_is_float(mode))
+ return false;
- be_emit_init(file_handle);
- isa->regs_16bit = pmap_create();
- isa->regs_8bit = pmap_create();
- isa->regs_8bit_high = pmap_create();
- isa->types = pmap_create();
- isa->tv_ent = pmap_create();
- isa->cpu = ia32_init_machine_description();
+ if (mux_is_doz(sel, mux_true, mux_false))
+ return true;
- ia32_build_16bit_reg_map(isa->regs_16bit);
- ia32_build_8bit_reg_map(isa->regs_8bit);
- ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
+ /* Check Cmp before the node */
+ if (is_Cmp(sel)) {
+ ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
-#ifndef NDEBUG
- isa->name_obst = xmalloc(sizeof(*isa->name_obst));
- obstack_init(isa->name_obst);
-#endif /* NDEBUG */
+ /* we can't handle 64bit compares */
+ if (get_mode_size_bits(cmp_mode) > 32)
+ return false;
- /* enter the ISA object into the intrinsic environment */
- intrinsic_env.isa = isa;
- ia32_handle_intrinsics();
-
- /* emit asm includes */
- n = get_irp_n_asms();
- for (i = 0; i < n; ++i) {
- be_emit_cstring("#APP\n");
- be_emit_ident(get_irp_asm(i));
- be_emit_cstring("\n#NO_APP\n");
+ /* we can't handle float compares */
+ if (mode_is_float(cmp_mode))
+ return false;
}
- /* needed for the debug support */
- be_gas_emit_switch_section(GAS_SECTION_TEXT);
- be_emit_cstring(".Ltext0:\n");
- be_emit_write_line();
-
- /* we mark referenced global entities, so we can only emit those which
- * are actually referenced. (Note: you mustn't use the type visited flag
- * elsewhere in the backend)
- */
- inc_master_type_visited();
+ /* did we disable cmov generation? */
+ if (!ia32_cg_config.use_cmov)
+ return false;
- return &isa->arch_env;
+ /* we can use a cmov */
+ return true;
}
-
+/**
+ * Create the trampoline code.
+ */
+static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
+{
+ ir_graph *const irg = get_irn_irg(block);
+ ir_node * p = trampoline;
+ ir_mode *const mode = get_irn_mode(p);
+ ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
+ ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
+ ir_node * st;
+
+ /* mov ecx,<env> */
+ st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
+ mem = new_r_Proj(st, mode_M, pn_Store_M);
+ p = new_r_Add(block, p, one, mode);
+ st = new_r_Store(block, mem, p, env, cons_none);
+ mem = new_r_Proj(st, mode_M, pn_Store_M);
+ p = new_r_Add(block, p, four, mode);
+ /* jmp <callee> */
+ st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
+ mem = new_r_Proj(st, mode_M, pn_Store_M);
+ p = new_r_Add(block, p, one, mode);
+ st = new_r_Store(block, mem, p, callee, cons_none);
+ mem = new_r_Proj(st, mode_M, pn_Store_M);
+ p = new_r_Add(block, p, four, mode);
+
+ return mem;
+}
+
+static const ir_settings_arch_dep_t ia32_arch_dep = {
+ 1, /* also use subs */
+ 4, /* maximum shifts */
+ 63, /* maximum shift amount */
+ ia32_evaluate_insn, /* evaluate the instruction sequence */
+
+ 1, /* allow Mulhs */
+ 1, /* allow Mulus */
+ 32, /* Mulh allowed up to 32 bit */
+};
+static backend_params ia32_backend_params = {
+ 1, /* support inline assembly */
+ 1, /* support Rotl nodes */
+ 0, /* little endian */
+ 1, /* modulo shift efficient */
+ 0, /* non-modulo shift not efficient */
+ &ia32_arch_dep, /* will be set later */
+ ia32_is_mux_allowed,
+ 32, /* machine_size */
+ NULL, /* float arithmetic mode, will be set below */
+ NULL, /* long long type */
+ NULL, /* unsigned long long type */
+ NULL, /* long double type */
+ 12, /* size of trampoline code */
+ 4, /* alignment of trampoline code */
+ ia32_create_trampoline_fkt,
+ 4 /* alignment of stack parameter */
+};
/**
- * Closes the output file and frees the ISA structure.
+ * Initializes the backend ISA.
*/
-static void ia32_done(void *self) {
- ia32_isa_t *isa = self;
+static void ia32_init(void)
+{
+ ir_mode *mode_long_long;
+ ir_mode *mode_unsigned_long_long;
+ ir_type *type_long_long;
+ ir_type *type_unsigned_long_long;
- /* emit now all global declarations */
- be_gas_emit_decls(isa->arch_env.main_env, 1);
+ ia32_setup_cg_config();
- pmap_destroy(isa->regs_16bit);
- pmap_destroy(isa->regs_8bit);
- pmap_destroy(isa->regs_8bit_high);
- pmap_destroy(isa->tv_ent);
- pmap_destroy(isa->types);
+ init_asm_constraints();
-#ifndef NDEBUG
- obstack_free(isa->name_obst, NULL);
-#endif /* NDEBUG */
+ ia32_register_init();
+ ia32_create_opcodes(&ia32_irn_ops);
- be_emit_exit();
+ ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
- free(self);
-}
+ /* note mantissa is 64bit but with explicitely encoded 1 so the really
+ * usable part as counted by firm is only 63 bits */
+ ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63);
+ ia32_type_E = new_type_primitive(ia32_mode_E);
+ set_type_size_bytes(ia32_type_E, 12);
+ set_type_alignment_bytes(ia32_type_E, 16);
+ mode_long_long = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
+ type_long_long = new_type_primitive(mode_long_long);
+ mode_unsigned_long_long
+ = new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64);
+ type_unsigned_long_long = new_type_primitive(mode_unsigned_long_long);
+
+ ia32_backend_params.type_long_long = type_long_long;
+ ia32_backend_params.type_unsigned_long_long = type_unsigned_long_long;
+
+ if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
+ ia32_backend_params.mode_float_arithmetic = NULL;
+ ia32_backend_params.type_long_double = NULL;
+ } else {
+ ia32_backend_params.mode_float_arithmetic = ia32_mode_E;
+ ia32_backend_params.type_long_double = ia32_type_E;
+ }
+}
/**
- * Return the number of register classes for this architecture.
- * We report always these:
- * - the general purpose registers
- * - the SSE floating point register set
- * - the virtual floating point registers
- * - the SSE vector register set
+ * The template that generates a new ISA object.
+ * Note that this template can be changed by command line
+ * arguments.
*/
-static unsigned ia32_get_n_reg_class(const void *self) {
- (void) self;
- return N_CLASSES;
+static ia32_isa_t ia32_isa_template = {
+ {
+ &ia32_isa_if, /* isa interface implementation */
+ N_IA32_REGISTERS,
+ ia32_registers,
+ N_IA32_CLASSES,
+ ia32_reg_classes,
+ &ia32_registers[REG_ESP], /* stack pointer register */
+ &ia32_registers[REG_EBP], /* base pointer register */
+ &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
+ 2, /* power of two stack alignment, 2^2 == 4 */
+ NULL, /* main environment */
+ 7, /* costs for a spill instruction */
+ 5, /* costs for a reload instruction */
+ false, /* no custom abi handling */
+ },
+ NULL, /* tv_ents */
+ IA32_FPU_ARCH_X87, /* FPU architecture */
+};
+
+static arch_env_t *ia32_begin_codegeneration(const be_main_env_t *env)
+{
+ ia32_isa_t *isa = XMALLOC(ia32_isa_t);
+
+ set_tarval_output_modes();
+
+ *isa = ia32_isa_template;
+ isa->tv_ent = pmap_create();
+
+ /* enter the ISA object into the intrinsic environment */
+ intrinsic_env.isa = isa;
+
+ be_emit_init(env->file_handle);
+ be_gas_begin_compilation_unit(env);
+
+ return &isa->base;
}
/**
- * Return the register class for index i.
+ * Closes the output file and frees the ISA structure.
*/
-static const arch_register_class_t *ia32_get_reg_class(const void *self,
- unsigned i)
+static void ia32_end_codegeneration(void *self)
{
- (void) self;
- assert(i < N_CLASSES);
- return &ia32_reg_classes[i];
+ ia32_isa_t *isa = (ia32_isa_t*)self;
+
+ /* emit now all global declarations */
+ be_gas_end_compilation_unit(isa->base.main_env);
+
+ be_emit_exit();
+
+ pmap_destroy(isa->tv_ent);
+ free(self);
}
/**
- * Get the register class which shall be used to store a value of a given mode.
- * @param self The this pointer.
- * @param mode The mode in question.
- * @return A register class which can hold values of the given mode.
+ * Returns the register for parameter nr.
*/
-const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
- const ir_mode *mode)
+static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
+ const ir_mode *mode)
{
- (void) self;
+ static const arch_register_t *gpreg_param_reg_fastcall[] = {
+ &ia32_registers[REG_ECX],
+ &ia32_registers[REG_EDX],
+ NULL
+ };
+ static const unsigned MAXNUM_GPREG_ARGS = 3;
+
+ static const arch_register_t *gpreg_param_reg_regparam[] = {
+ &ia32_registers[REG_EAX],
+ &ia32_registers[REG_EDX],
+ &ia32_registers[REG_ECX]
+ };
+
+ static const arch_register_t *gpreg_param_reg_this[] = {
+ &ia32_registers[REG_ECX],
+ NULL,
+ NULL
+ };
+
+ static const arch_register_t *fpreg_sse_param_reg_std[] = {
+ &ia32_registers[REG_XMM0],
+ &ia32_registers[REG_XMM1],
+ &ia32_registers[REG_XMM2],
+ &ia32_registers[REG_XMM3],
+ &ia32_registers[REG_XMM4],
+ &ia32_registers[REG_XMM5],
+ &ia32_registers[REG_XMM6],
+ &ia32_registers[REG_XMM7]
+ };
+
+ static const arch_register_t *fpreg_sse_param_reg_this[] = {
+ NULL, /* in case of a "this" pointer, the first parameter must not be a float */
+ };
+ static const unsigned MAXNUM_SSE_ARGS = 8;
+
+ if ((cc & cc_this_call) && nr == 0)
+ return gpreg_param_reg_this[0];
+
+ if (! (cc & cc_reg_param))
+ return NULL;
if (mode_is_float(mode)) {
- return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
+ if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
+ return NULL;
+ if (nr >= MAXNUM_SSE_ARGS)
+ return NULL;
+
+ if (cc & cc_this_call) {
+ return fpreg_sse_param_reg_this[nr];
+ }
+ return fpreg_sse_param_reg_std[nr];
+ } else if (mode_is_int(mode) || mode_is_reference(mode)) {
+ unsigned num_regparam;
+
+ if (get_mode_size_bits(mode) > 32)
+ return NULL;
+
+ if (nr >= MAXNUM_GPREG_ARGS)
+ return NULL;
+
+ if (cc & cc_this_call) {
+ return gpreg_param_reg_this[nr];
+ }
+ num_regparam = cc & ~cc_bits;
+ if (num_regparam == 0) {
+ /* default fastcall */
+ return gpreg_param_reg_fastcall[nr];
+ }
+ if (nr < num_regparam)
+ return gpreg_param_reg_regparam[nr];
+ return NULL;
}
- else
- return &ia32_reg_classes[CLASS_ia32_gp];
+
+ panic("unknown argument mode");
}
/**
* Get the ABI restrictions for procedure calls.
- * @param self The this pointer.
- * @param method_type The type of the method (procedure) in question.
- * @param abi The abi object to be modified
*/
-static void ia32_get_call_abi(const void *self, ir_type *method_type,
- be_abi_call_t *abi)
+static void ia32_get_call_abi(ir_type *method_type, be_abi_call_t *abi)
{
- ir_type *tp;
- ir_mode *mode;
unsigned cc;
int n, i, regnum;
int pop_amount = 0;
be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
- (void) self;
-
/* set abi flags for calls */
- call_flags.bits.left_to_right = 0; /* always last arg first on stack */
call_flags.bits.store_args_sequential = 0;
/* call_flags.bits.try_omit_fp not changed: can handle both settings */
call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
- call_flags.bits.call_has_imm = 1; /* No call immediates, we handle this by ourselves */
+ call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
/* set parameter passing style */
be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
+ cc = get_method_calling_convention(method_type);
if (get_method_variadicity(method_type) == variadicity_variadic) {
/* pass all parameters of a variadic function on the stack */
- cc = cc_cdecl_set;
+ cc = cc_cdecl_set | (cc & cc_this_call);
} else {
- cc = get_method_calling_convention(method_type);
if (get_method_additional_properties(method_type) & mtp_property_private &&
ia32_cg_config.optimize_cc) {
- /* set the calling conventions to register parameter */
- cc = (cc & ~cc_bits) | cc_reg_param;
+ /* set the fast calling conventions (allowing up to 3) */
+ cc = SET_FASTCALL(cc) | 3;
}
}
/* we have to pop the shadow parameter ourself for compound calls */
- if( (get_method_calling_convention(method_type) & cc_compound_ret)
+ if ( (get_method_calling_convention(method_type) & cc_compound_ret)
&& !(cc & cc_reg_param)) {
pop_amount += get_mode_size_bytes(mode_P_data);
}
n = get_method_n_params(method_type);
for (i = regnum = 0; i < n; i++) {
- ir_mode *mode;
- const arch_register_t *reg = NULL;
+ const arch_register_t *reg = NULL;
+ ir_type *tp = get_method_param_type(method_type, i);
+ ir_mode *mode = get_type_mode(tp);
- tp = get_method_param_type(method_type, i);
- mode = get_type_mode(tp);
if (mode != NULL) {
reg = ia32_get_RegParam_reg(cc, regnum, mode);
}
if (reg != NULL) {
- be_abi_call_param_reg(abi, i, reg);
+ be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
++regnum;
} else {
/* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
if (size < 4) load_mode = mode_Iu;
}
- be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
+ be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
}
}
/* In case of 64bit returns, we will have two 32bit values */
if (n == 2) {
- tp = get_method_res_type(method_type, 0);
- mode = get_type_mode(tp);
+ ir_type *tp = get_method_res_type(method_type, 0);
+ ir_mode *mode = get_type_mode(tp);
assert(!mode_is_float(mode) && "two FP results not supported");
assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
- be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
- be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
+ be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
+ be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
}
else if (n == 1) {
+ ir_type *tp = get_method_res_type(method_type, 0);
+ ir_mode *mode = get_type_mode(tp);
const arch_register_t *reg;
-
- tp = get_method_res_type(method_type, 0);
assert(is_atomic_type(tp));
- mode = get_type_mode(tp);
- reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
+ reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
- be_abi_call_res_reg(abi, 0, reg);
+ be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
}
}
-int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
+static void ia32_mark_remat(ir_node *node)
{
- (void) block_env;
-
- if(!is_ia32_irn(irn)) {
- return -1;
+ if (is_ia32_irn(node)) {
+ set_ia32_is_remat(node);
}
-
- if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
- || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
- || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
- || is_ia32_Immediate(irn))
- return 0;
-
- return 1;
}
-/**
- * Initializes the code generator interface.
- */
-static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
+static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
{
- (void) self;
- return &ia32_code_gen_if;
-}
+ (void) c;
-/**
- * Returns the estimated execution time of an ia32 irn.
- */
-static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
- (void) env;
- return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
+ /* we already added all our simple flags to the flags modifier list in
+ * init, so this flag we don't know. */
+ return ASM_CONSTRAINT_FLAG_INVALID;
}
-list_sched_selector_t ia32_sched_selector;
-
-/**
- * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
- */
-static const list_sched_selector_t *ia32_get_list_sched_selector(
- const void *self, list_sched_selector_t *selector)
+static int ia32_is_valid_clobber(const char *clobber)
{
- (void) self;
- memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
- ia32_sched_selector.exectime = ia32_sched_exectime;
- ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
- return &ia32_sched_selector;
+ return ia32_get_clobber_register(clobber) != NULL;
}
-static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
+static void ia32_lower_for_target(void)
{
- (void) self;
- return NULL;
-}
+ size_t i, n_irgs = get_irp_n_irgs();
-/**
- * Returns the necessary byte alignment for storing a register of given class.
- */
-static int ia32_get_reg_class_alignment(const void *self,
- const arch_register_class_t *cls)
-{
- ir_mode *mode = arch_register_class_mode(cls);
- int bytes = get_mode_size_bytes(mode);
- (void) self;
+ /* perform doubleword lowering */
+ lwrdw_param_t lower_dw_params = {
+ 1, /* little endian */
+ 64, /* doubleword size */
+ ia32_create_intrinsic_fkt,
+ &intrinsic_env,
+ };
- if (mode_is_float(mode) && bytes > 8)
- return 16;
- return bytes;
-}
+ ia32_create_opcodes(&ia32_irn_ops);
-static const be_execution_unit_t ***ia32_get_allowed_execution_units(
- const void *self, const ir_node *irn)
-{
- static const be_execution_unit_t *_allowed_units_BRANCH[] = {
- &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
- &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
- NULL,
- };
- static const be_execution_unit_t *_allowed_units_GP[] = {
- &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
- &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
- &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
- &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
- &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
- &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
- &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
- NULL,
- };
- static const be_execution_unit_t *_allowed_units_DUMMY[] = {
- &be_machine_execution_units_DUMMY[0],
- NULL,
- };
- static const be_execution_unit_t **_units_callret[] = {
- _allowed_units_BRANCH,
- NULL
- };
- static const be_execution_unit_t **_units_other[] = {
- _allowed_units_GP,
- NULL
- };
- static const be_execution_unit_t **_units_dummy[] = {
- _allowed_units_DUMMY,
- NULL
- };
- const be_execution_unit_t ***ret;
- (void) self;
+ /* lower compound param handling
+ * Note: we lower compound arguments ourself, since on ia32 we don't
+ * have hidden parameters but know where to find the structs on the stack.
+ * (This also forces us to always allocate space for the compound arguments
+ * on the callframe and we can't just use an arbitrary position on the
+ * stackframe)
+ */
+ lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
- if (is_ia32_irn(irn)) {
- ret = get_ia32_exec_units(irn);
- }
- else if (is_be_node(irn)) {
- if (be_is_Call(irn) || be_is_Return(irn)) {
- ret = _units_callret;
- }
- else if (be_is_Barrier(irn)) {
- ret = _units_dummy;
- }
- else {
- ret = _units_other;
- }
- }
- else {
- ret = _units_dummy;
+ /* replace floating point operations by function calls */
+ if (ia32_cg_config.use_softfloat) {
+ lower_floating_point();
}
- return ret;
-}
+ ir_prepare_dw_lowering(&lower_dw_params);
+ ir_lower_dw_ops();
-/**
- * Return the abstract ia32 machine.
- */
-static const be_machine_t *ia32_get_machine(const void *self) {
- const ia32_isa_t *isa = self;
- return isa->cpu;
+ for (i = 0; i < n_irgs; ++i) {
+ ir_graph *irg = get_irp_irg(i);
+ /* lower for mode_b stuff */
+ ir_lower_mode_b(irg, mode_Iu);
+ /* break up switches with wide ranges */
+ lower_switch(irg, 4, 256, false);
+ }
+
+ for (i = 0; i < n_irgs; ++i) {
+ ir_graph *irg = get_irp_irg(i);
+ /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
+ * so we can generate rep movs later, and turn all big CopyBs into
+ * memcpy calls. */
+ lower_CopyB(irg, 64, 8193, true);
+ }
}
/**
- * Return irp irgs in the desired order.
+ * Returns the libFirm configuration parameter for this backend.
*/
-static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
+static const backend_params *ia32_get_libfirm_params(void)
{
- (void) self;
- (void) irg_list;
- return NULL;
-}
-
-static void ia32_mark_remat(const void *self, ir_node *node) {
- (void) self;
- if (is_ia32_irn(node)) {
- set_ia32_is_remat(node);
- }
+ return &ia32_backend_params;
}
/**
- * Allows or disallows the creation of Psi nodes for the given Phi nodes.
- * @return 1 if allowed, 0 otherwise
+ * Check if the given register is callee or caller save.
*/
-static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
+static int ia32_register_saved_by(const arch_register_t *reg, int callee)
{
- ir_node *phi;
- ir_node *cmp = NULL;
-
- /* we can't handle psis with 64bit compares yet */
- if (is_Proj(sel)) {
- cmp = get_Proj_pred(sel);
- if (is_Cmp(cmp)) {
- ir_node *left = get_Cmp_left(cmp);
- ir_mode *cmp_mode = get_irn_mode(left);
- if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
+ if (callee) {
+ /* check for callee saved */
+ if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
+ switch (reg->index) {
+ case REG_GP_EBX:
+ case REG_GP_ESI:
+ case REG_GP_EDI:
+ case REG_GP_EBP:
+ return 1;
+ default:
return 0;
- } else {
- cmp = NULL;
- }
- }
-
- if (ia32_cg_config.use_cmov) {
- if (ia32_cg_config.use_sse2 && cmp != NULL) {
- pn_Cmp pn = get_Proj_proj(sel);
- ir_node *cl = get_Cmp_left(cmp);
- ir_node *cr = get_Cmp_right(cmp);
-
- /* check the Phi nodes: no 64bit and no floating point cmov */
- for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
- ir_mode *mode = get_irn_mode(phi);
-
- if (mode_is_float(mode)) {
- /* check for Min, Max */
- ir_node *t = get_Phi_pred(phi, i);
- ir_node *f = get_Phi_pred(phi, j);
- int res = 0;
-
- /* SSE2 supports Min & Max */
- if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
- if (cl == t && cr == f) {
- /* Psi(a <=/>= b, a, b) => MIN, MAX */
- res = 1;
- } else if (cl == f && cr == t) {
- /* Psi(a <=/>= b, b, a) => MAX, MIN */
- res = 1;
- }
- }
- if (! res)
- return 0;
-
- } else if (get_mode_size_bits(mode) > 32)
- return 0;
- }
- } else {
- /* check the Phi nodes: no 64bit and no floating point cmov */
- for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
- ir_mode *mode = get_irn_mode(phi);
-
- if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
- return 0;
}
}
-
- return 1;
} else {
- ir_node *cl, *cr;
- pn_Cmp pn;
-
- /* No cmov, only some special cases */
- if (cmp == NULL)
- return 0;
-
- /* Now some supported cases here */
- pn = get_Proj_proj(sel);
- cl = get_Cmp_left(cmp);
- cr = get_Cmp_right(cmp);
-
- for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
- ir_mode *mode = get_irn_mode(phi);
- int res = 0;
- ir_node *t, *f;
-
- t = get_Phi_pred(phi, i);
- f = get_Phi_pred(phi, j);
-
- /* no floating point and no 64bit yet */
- if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
+ /* check for caller saved */
+ if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
+ switch (reg->index) {
+ case REG_GP_EDX:
+ case REG_GP_ECX:
+ case REG_GP_EAX:
+ return 1;
+ default:
return 0;
-
- if (is_Const(t) && is_Const(f)) {
- if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
- /* always support Psi(x, C1, C2) */
- res = 1;
- }
- } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
- if (0) {
-#if 0
- } else if (cl == t && cr == f) {
- /* Psi(a <=/>= b, a, b) => Min, Max */
- res = 1;
- } else if (cl == f && cr == t) {
- /* Psi(a <=/>= b, b, a) => Max, Min */
- res = 1;
-#endif
- } else if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
- is_Const(f) && is_Const_null(f) && is_Sub(t) &&
- get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
- /* Psi(a >=u b, a - b, 0) unsigned Doz */
- res = 1;
- } else if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
- is_Const(t) && is_Const_null(t) && is_Sub(f) &&
- get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
- /* Psi(a <=u b, 0, a - b) unsigned Doz */
- res = 1;
- } else if (is_Const(cr) && is_Const_null(cr)) {
- if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
- /* Psi(a <=/>= 0 ? a : -a) Nabs/Abs */
- res = 1;
- } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
- /* Psi(a <=/>= 0 ? -a : a) Abs/Nabs */
- res = 1;
- }
- }
}
- if (! res)
- return 0;
+ } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
+ /* all XMM registers are caller save */
+ return reg->index != REG_XMM_NOREG;
+ } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
+ /* all VFP registers are caller save */
+ return reg->index != REG_VFP_NOREG;
}
- /* all checks passed */
- return 1;
}
return 0;
}
-static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c)
-{
- (void) self;
- (void) c;
-
- /* we already added all our simple flags to the flags modifier list in
- * init, so this flag we don't know. */
- return ASM_CONSTRAINT_FLAG_INVALID;
-}
-
-static int ia32_is_valid_clobber(const void *self, const char *clobber)
-{
- (void) self;
-
- return ia32_get_clobber_register(clobber) != NULL;
-}
-
-/**
- * Returns the libFirm configuration parameter for this backend.
- */
-static const backend_params *ia32_get_libfirm_params(void) {
- static const ir_settings_if_conv_t ifconv = {
- 4, /* maxdepth, doesn't matter for Psi-conversion */
- ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
- };
- static const ir_settings_arch_dep_t ad = {
- 1, /* also use subs */
- 4, /* maximum shifts */
- 31, /* maximum shift amount */
- ia32_evaluate_insn, /* evaluate the instruction sequence */
-
- 1, /* allow Mulhs */
- 1, /* allow Mulus */
- 32 /* Mulh allowed up to 32 bit */
- };
- static backend_params p = {
- 1, /* need dword lowering */
- 1, /* support inline assembly */
- 0, /* no immediate floating point mode. */
- NULL, /* no additional opcodes */
- NULL, /* will be set later */
- ia32_create_intrinsic_fkt,
- &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
- NULL, /* will be set below */
- NULL /* will be set below */
- };
-
- ia32_setup_cg_config();
-
- /* doesn't really belong here, but this is the earliest place the backend
- * is called... */
- init_asm_constraints();
-
- p.dep_param = &ad;
- p.if_conv_info = &ifconv;
- return &p;
-}
-
static const lc_opt_enum_int_items_t gas_items[] = {
- { "elf", GAS_FLAVOUR_ELF },
- { "mingw", GAS_FLAVOUR_MINGW },
- { "yasm", GAS_FLAVOUR_YASM },
- { "macho", GAS_FLAVOUR_MACH_O },
- { NULL, 0 }
+ { "elf", OBJECT_FILE_FORMAT_ELF },
+ { "mingw", OBJECT_FILE_FORMAT_COFF },
+ { "macho", OBJECT_FILE_FORMAT_MACH_O },
+ { NULL, 0 }
};
static lc_opt_enum_int_var_t gas_var = {
- (int*) &be_gas_flavour, gas_items
+ (int*) &be_gas_object_file_format, gas_items
};
+#ifdef FIRM_GRGEN_BE
static const lc_opt_enum_int_items_t transformer_items[] = {
{ "default", TRANSFORMER_DEFAULT },
-#ifdef FIRM_GRGEN_BE
{ "pbqp", TRANSFORMER_PBQP },
{ "random", TRANSFORMER_RAND },
-#endif
{ NULL, 0 }
};
static lc_opt_enum_int_var_t transformer_var = {
(int*)&be_transformer, transformer_items
};
+#endif
static const lc_opt_table_entry_t ia32_options[] = {
LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
+#ifdef FIRM_GRGEN_BE
LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
- LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
- &ia32_isa_template.arch_env.stack_alignment),
+#endif
+ LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
+ &ia32_isa_template.base.stack_alignment),
+ LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
LC_OPT_LAST
};
const arch_isa_if_t ia32_isa_if = {
ia32_init,
- ia32_done,
- ia32_get_n_reg_class,
- ia32_get_reg_class,
- ia32_get_reg_class_for_mode,
- ia32_get_call_abi,
- ia32_get_code_generator_if,
- ia32_get_list_sched_selector,
- ia32_get_ilp_sched_selector,
- ia32_get_reg_class_alignment,
ia32_get_libfirm_params,
- ia32_get_allowed_execution_units,
- ia32_get_machine,
- ia32_get_irg_list,
- ia32_mark_remat,
+ ia32_lower_for_target,
ia32_parse_asm_constraint,
- ia32_is_valid_clobber
-};
+ ia32_is_valid_clobber,
-void ia32_init_emitter(void);
-void ia32_init_finish(void);
-void ia32_init_optimize(void);
-void ia32_init_transform(void);
-void ia32_init_x87(void);
+ ia32_begin_codegeneration,
+ ia32_end_codegeneration,
+ ia32_init_graph,
+ ia32_get_call_abi,
+ ia32_mark_remat,
+ ia32_get_pic_base, /* return node used as base in pic code addresses */
+ be_new_spill,
+ be_new_reload,
+ ia32_register_saved_by,
+ ia32_handle_intrinsics,
+ ia32_before_abi, /* before abi introduce hook */
+ ia32_prepare_graph,
+ ia32_before_ra, /* before register allocation hook */
+ ia32_finish, /* called before codegen */
+ ia32_emit, /* emit && done */
+};
+
+BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
void be_init_arch_ia32(void)
{
lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
lc_opt_add_table(ia32_grp, ia32_options);
be_register_isa_if("ia32", &ia32_isa_if);
- FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
-
ia32_init_emitter();
ia32_init_finish();
ia32_init_optimize();
ia32_init_x87();
ia32_init_architecture();
}
-
-BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
projects / libfirm / blobdiff