#include "benode.h"
#include "beirg.h"
#include "beintlive_t.h"
+#include "belistsched.h"
static int my_values_interfere(const ir_node *a, const ir_node *b);
{
be_verify_schedule_env_t *env = (be_verify_schedule_env_t*) data;
ir_node *node;
- ir_node *non_phi_found = NULL;
- int cfchange_found = 0;
+ ir_node *non_phi_found = NULL;
+ ir_node *cfchange_found = NULL;
int last_timestep = INT_MIN;
/*
* (except mode_X projs)
*/
sched_foreach(block, node) {
- int i, arity;
int timestep;
/* this node is scheduled */
}
/* Check for control flow changing nodes */
- if (is_cfop(node) && get_irn_opcode(node) != iro_Start) {
+ if (is_cfop(node)) {
/* check, that only one CF operation is scheduled */
- if (cfchange_found == 1) {
- ir_fprintf(stderr, "Verify Warning: More than 1 control flow changing node (%+F) scheduled in block %+F (%s)\n",
- node, block, get_irg_dump_name(env->irg));
+ if (cfchange_found != NULL) {
+ ir_fprintf(stderr, "Verify Warning: Additional control flow changing node %+F scheduled after %+F in block %+F (%s)\n",
+ node, block, cfchange_found, get_irg_dump_name(env->irg));
env->problem_found = 1;
+ } else {
+ cfchange_found = node;
}
- cfchange_found = 1;
- } else if (cfchange_found) {
+ } else if (cfchange_found != NULL) {
/* proj and keepany aren't real instructions... */
if (!is_Proj(node) && !be_is_Keep(node)) {
ir_fprintf(stderr, "Verify Warning: Node %+F scheduled after control flow changing node in block %+F (%s)\n",
/* Check that all uses come before their definitions */
if (!is_Phi(node)) {
- int nodetime = sched_get_time_step(node);
+ int i;
+ int arity;
+ sched_timestep_t nodetime = sched_get_time_step(node);
for (i = 0, arity = get_irn_arity(node); i < arity; ++i) {
ir_node *arg = get_irn_n(node, i);
if (get_nodes_block(arg) != block
prev = sched_prev(prev);
while (true) {
+ int i;
for (i = 0; i < arity; ++i) {
ir_node *in = get_irn_n(node, i);
in = skip_Proj(in);
static void check_schedule(ir_node *node, void *data)
{
be_verify_schedule_env_t *env = (be_verify_schedule_env_t*)data;
- bool should_be = to_appear_in_schedule(node);
+ bool should_be = !is_Proj(node) && !(arch_get_irn_flags(node) & arch_irn_flags_not_scheduled);
bool scheduled = bitset_is_set(env->scheduled, get_irn_idx(node));
if (should_be != scheduled) {
static void check_output_constraints(ir_node *node)
{
/* verify output register */
- if (arch_get_irn_reg_class_out(node) == regclass) {
+ if (arch_get_irn_reg_class(node) == regclass) {
+ const arch_register_req_t *req = arch_get_irn_register_req(node);
const arch_register_t *reg = arch_get_irn_register(node);
if (reg == NULL) {
ir_fprintf(stderr, "Verify warning: Node %+F in block %+F(%s) should have a register assigned\n",
node, get_nodes_block(node), get_irg_dump_name(irg));
problem_found = 1;
- } else if (!(reg->type & arch_register_type_joker) && !arch_reg_out_is_allocatable(node, reg)) {
+ } else if (!arch_reg_is_allocatable(req, reg)) {
ir_fprintf(stderr, "Verify warning: Register %s assigned as output of %+F not allowed (register constraint) in block %+F(%s)\n",
reg->name, node, get_nodes_block(node), get_irg_dump_name(irg));
problem_found = 1;
/* verify input register */
arity = get_irn_arity(node);
for (i = 0; i < arity; ++i) {
- const arch_register_req_t *req = arch_get_in_register_req(node, i);
+ const arch_register_req_t *req = arch_get_irn_register_req_in(node, i);
ir_node *pred = get_irn_n(node, i);
- const arch_register_req_t *pred_req = arch_get_register_req_out(pred);
+ const arch_register_req_t *pred_req = arch_get_irn_register_req(pred);
if (is_Bad(pred)) {
ir_fprintf(stderr, "Verify warning: %+F in block %+F(%s) has Bad as input %d\n",
pred, get_nodes_block(pred), get_irg_dump_name(irg), node);
problem_found = 1;
continue;
- } else if (!(reg->type & arch_register_type_joker) && ! arch_reg_is_allocatable(node, i, reg)) {
+ } else if (!arch_reg_is_allocatable(req, reg)) {
ir_fprintf(stderr, "Verify warning: Register %s as input %d of %+F not allowed (register constraint) in block %+F(%s)\n",
reg->name, i, node, get_nodes_block(node), get_irg_dump_name(irg));
problem_found = 1;
/* phis should be NOPs at this point, which means all input regs
* must be the same as the output reg */
if (is_Phi(node)) {
- int i, arity;
-
reg = arch_get_irn_register(node);
arity = get_irn_arity(node);
const arch_register_t *reg;
ir_node *reg_node;
- if (arch_get_irn_reg_class_out(node) != regclass)
+ if (arch_get_irn_reg_class(node) != regclass)
return;
reg = arch_get_irn_register(node);
const arch_register_t *reg;
ir_node *reg_node;
- if (arch_get_irn_reg_class_out(node) != regclass)
+ if (arch_get_irn_reg_class(node) != regclass)
return;
reg = arch_get_irn_register(node);
reg_node = registers[reg->index];
+ /* a little cheat, since its so hard to remove all outedges to dead code
+ * in the backend. This particular case should never be a problem. */
+ if (reg_node == NULL && get_irn_n_edges(node) == 0)
+ return;
+
if (reg_node != node) {
ir_fprintf(stderr, "Verify warning: Node %+F not registered as value for Register %s (but %+F) in block %+F(%s)\n",
node, reg->name, reg_node, get_nodes_block(node), get_irg_dump_name(irg));
registers = ALLOCANZ(ir_node*, n_regs);
be_lv_foreach(lv, block, be_lv_state_end, idx) {
- ir_node *node = be_lv_get_irn(lv, block, idx);
- value_used(block, node);
+ ir_node *lv_node = be_lv_get_irn(lv, block, idx);
+ value_used(block, lv_node);
}
sched_foreach_reverse(block, node) {
}
be_lv_foreach(lv, block, be_lv_state_in, idx) {
- ir_node *node = be_lv_get_irn(lv, block, idx);
- value_def(node);
+ ir_node *lv_node = be_lv_get_irn(lv, block, idx);
+ value_def(lv_node);
}
/* set must be empty now */
projects / libfirm / blobdiff