prefalloc will respect alignment when initially assigning registers

[libfirm] / ir / be / beverify.c

diff --git a/ir/be/beverify.c b/ir/be/beverify.c
index 628c43f..3dbc79f 100644 (file)
--- a/ir/be/beverify.c
+++ b/ir/be/beverify.c
@@ -45,6 +45,7 @@
 #include "benode.h"
 #include "beirg.h"
 #include "beintlive_t.h"
+#include "belistsched.h"
 
 static int my_values_interfere(const ir_node *a, const ir_node *b);
 
@@ -168,7 +169,6 @@ static void verify_schedule_walker(ir_node *block, void *data)
         *       (except mode_X projs)
         */
        sched_foreach(block, node) {
-               int i, arity;
                int timestep;
 
                /* this node is scheduled */
@@ -225,7 +225,9 @@ static void verify_schedule_walker(ir_node *block, void *data)
 
                /* Check that all uses come before their definitions */
                if (!is_Phi(node)) {
-                       int nodetime = sched_get_time_step(node);
+                       int i;
+                       int arity;
+                       sched_timestep_t nodetime = sched_get_time_step(node);
                        for (i = 0, arity = get_irn_arity(node); i < arity; ++i) {
                                ir_node *arg = get_irn_n(node, i);
                                if (get_nodes_block(arg) != block
@@ -257,6 +259,7 @@ static void verify_schedule_walker(ir_node *block, void *data)
                                prev = sched_prev(prev);
 
                        while (true) {
+                               int i;
                                for (i = 0; i < arity; ++i) {
                                        ir_node *in = get_irn_n(node, i);
                                        in = skip_Proj(in);
@@ -281,7 +284,7 @@ static void verify_schedule_walker(ir_node *block, void *data)
 static void check_schedule(ir_node *node, void *data)
 {
        be_verify_schedule_env_t *env = (be_verify_schedule_env_t*)data;
-       bool should_be = to_appear_in_schedule(node);
+       bool should_be = !is_Proj(node) && !(arch_irn_get_flags(node) & arch_irn_flags_not_scheduled);
        bool scheduled = bitset_is_set(env->scheduled, get_irn_idx(node));
 
        if (should_be != scheduled) {
@@ -726,8 +729,6 @@ static void check_input_constraints(ir_node *node)
        /* phis should be NOPs at this point, which means all input regs
         * must be the same as the output reg */
        if (is_Phi(node)) {
-               int i, arity;
-
                reg = arch_get_irn_register(node);
 
                arity = get_irn_arity(node);
@@ -784,6 +785,11 @@ static void value_def(ir_node *node)
 
        reg_node = registers[reg->index];
 
+       /* a little cheat, since its so hard to remove all outedges to dead code
+        * in the backend. This particular case should never be a problem. */
+       if (reg_node == NULL && get_irn_n_edges(node) == 0)
+               return;
+
        if (reg_node != node) {
                ir_fprintf(stderr, "Verify warning: Node %+F not registered as value for Register %s (but %+F) in block %+F(%s)\n",
                               node, reg->name, reg_node, get_nodes_block(node), get_irg_dump_name(irg));
@@ -810,8 +816,8 @@ static void verify_block_register_allocation(ir_node *block, void *data)
                registers = ALLOCANZ(ir_node*, n_regs);
 
                be_lv_foreach(lv, block, be_lv_state_end, idx) {
-                       ir_node *node = be_lv_get_irn(lv, block, idx);
-                       value_used(block, node);
+                       ir_node *lv_node = be_lv_get_irn(lv, block, idx);
+                       value_used(block, lv_node);
                }
 
                sched_foreach_reverse(block, node) {
@@ -842,8 +848,8 @@ static void verify_block_register_allocation(ir_node *block, void *data)
                }
 
                be_lv_foreach(lv, block, be_lv_state_in, idx) {
-                       ir_node *node = be_lv_get_irn(lv, block, idx);
-                       value_def(node);
+                       ir_node *lv_node = be_lv_get_irn(lv, block, idx);
+                       value_def(lv_node);
                }
 
                /* set must be empty now */