beverify: test register width in regalloc verification

[libfirm] / ir / be / bespillbelady.c

diff --git a/ir/be/bespillbelady.c b/ir/be/bespillbelady.c
index 282f885..ee43e8b 100644 (file)
--- a/ir/be/bespillbelady.c
+++ b/ir/be/bespillbelady.c
@@ -293,7 +293,7 @@ static unsigned get_distance(ir_node *from, const ir_node *def, int skip_from_us
                return USES_INFINITY;
 
        /* We have to keep nonspillable nodes in the workingset */
-       if (arch_irn_get_flags(skip_Proj_const(def)) & arch_irn_flags_dont_spill)
+       if (arch_get_irn_flags(skip_Proj_const(def)) & arch_irn_flags_dont_spill)
                return 0;
 
        /* give some bonus to rematerialisable nodes */
@@ -479,7 +479,7 @@ static loc_t to_take_or_not_to_take(ir_node* first, ir_node *node,
        }
 
        /* We have to keep nonspillable nodes in the workingset */
-       if (arch_irn_get_flags(skip_Proj_const(node)) & arch_irn_flags_dont_spill) {
+       if (arch_get_irn_flags(skip_Proj_const(node)) & arch_irn_flags_dont_spill) {
                loc.time = 0;
                DB((dbg, DBG_START, "    %+F taken (dontspill node)\n", node, loc.time));
                return loc;