* as described in: Sid-Ahmed-Ali Touati
* Register Saturation in Superscalar and VLIW Codes
*/
-#ifdef HAVE_CONFIG_H
#include "config.h"
-#endif
#include <limits.h>
}
/* Dumps the potential killing DAG (PKG) as vcg. */
-static void debug_vcg_dump_pkg(rss_t *rss, ir_nodeset_t *max_ac, int iteration) {
+static void debug_vcg_dump_pkg(rss_t *rss, ir_nodeset_t *max_ac, int iteration)
+{
FILE *f;
char file_name[256];
- char *suffix = alloca(32);
+ char suffix[32];
static const char suffix1[] = "-RSS-PKG.vcg";
static const char suffix2[] = "-RSS-PKG-MAXAC.vcg";
plist_element_t *el;
if (! max_ac) {
- snprintf(suffix, 32, "%s", suffix1);
+ snprintf(suffix, sizeof(suffix), "%s", suffix1);
}
else {
- snprintf(suffix, 32, "-%02d%s", iteration, suffix2);
+ snprintf(suffix, sizeof(suffix), "-%02d%s", iteration, suffix2);
}
build_file_name(rss, suffix, strlen(suffix) + 1, file_name, sizeof(file_name));
ir_node *user = get_edge_src_irn(edge);
/* skip ignore nodes as they do not really contribute to register pressure */
- if (arch_irn_is(rss->arch_env, user, ignore))
+ if (arch_irn_is_ignore(user))
continue;
/*
}
if (is_Proj(user)) {
- //if (arch_get_irn_reg_class(user, -1) == rss->cls)
+ //if (arch_get_irn_reg_class_out(user) == rss->cls)
collect_descendants(rss, rirn, user, got_sink, cur_desc_walk);
}
else {
assert(! is_Proj(consumer) && "Cannot handle Projs");
if (! is_Phi(consumer) && ! is_Block(consumer) && get_nodes_block(consumer) == block) {
- if (! arch_irn_is(rss->arch_env, consumer, ignore) && ! plist_has_value(rss_irn->consumer_list, consumer)) {
+ if (!arch_irn_is_ignore(consumer) &&
+ !plist_has_value(rss_irn->consumer_list, consumer)) {
plist_insert_back(rss_irn->consumer_list, consumer);
DBG((rss->dbg, LEVEL_2, "\t\tconsumer %+F\n", consumer));
}
ir_node *consumer = get_edge_src_irn(edge);
if (is_Proj(consumer)) {
- //if (arch_get_irn_reg_class(consumer, -1) == rss->cls)
+ //if (arch_get_irn_reg_class_out(consumer) == rss->cls)
collect_consumer(rss, rss_irn, consumer, got_sink);
}
else
/**
* Adds the edge src -> tgt to the dvg. Checks if reverse edge is already there (asserts).
*/
-static INLINE void add_dvg_edge(rss_t *rss, dvg_t *dvg, const ir_node *src, const ir_node *tgt, int have_source) {
+static inline void add_dvg_edge(rss_t *rss, dvg_t *dvg, const ir_node *src, const ir_node *tgt, int have_source) {
rss_edge_t *dvg_edge;
rss_edge_t key;
static void update_dvg(rss_t *rss, dvg_t *dvg, rss_irn_t *src, rss_irn_t *tgt) {
int i, j, idx;
rss_edge_t *edge;
- rss_edge_t **arr = alloca(pset_count(dvg->edges) * sizeof(arr[0]));
+ rss_edge_t **arr = ALLOCAN(rss_edge_t*, pset_count(dvg->edges));
/*
Add an edge from serialization target to serialization src:
*/
static ir_nodeset_t *compute_maximal_antichain(rss_t *rss, dvg_t *dvg, int iteration) {
int n = ir_nodeset_size(&dvg->nodes);
- int *assignment = alloca(n * sizeof(assignment[0]));
- int *assignment_rev = alloca(n * sizeof(assignment_rev[0]));
- int *idx_map = alloca(n * sizeof(idx_map[0]));
+ int *assignment = ALLOCAN(int, n);
+ int *assignment_rev = ALLOCAN(int, n);
+ int *idx_map = ALLOCAN(int, n);
hungarian_problem_t *bp;
ir_nodeset_t *values, *temp;
ir_nodeset_iterator_t iter;
if (pset_count(dvg->edges) == 0)
return NULL;
- bp = hungarian_new(n, n, 1, HUNGARIAN_MATCH_NORMAL);
+ bp = hungarian_new(n, n, HUNGARIAN_MATCH_NORMAL);
/*
At first, we build an index map for the nodes in the DVG,
int n = ir_nodeset_size(sat_vals);
int n_idx = ARR_LEN_SAFE(rss->idx_map);
int i = 0;
- ir_node **val_arr = alloca(n * sizeof(val_arr[0]));
+ ir_node **val_arr = ALLOCAN(ir_node*, n);
bitset_t *bs_sv = bitset_alloca(n_idx);
bitset_t *bs_vdesc = bitset_alloca(n_idx);
bitset_t *bs_tmp = bitset_alloca(n_idx);
/* Get all live value at end of Block having current register class */
ir_nodeset_init(&rss->live_block);
- be_liveness_end_of_block(rss->liveness, rss->arch_env, rss->cls, rss->block, &rss->live_block);
+ be_liveness_end_of_block(rss->liveness, rss->cls, rss->block, &rss->live_block);
/* reset the list of interesting nodes */
plist_clear(rss->nodes);
if (be_is_Keep(irn))
continue;
- if (!arch_irn_is(rss->arch_env, irn, ignore) && arch_get_irn_reg_class(irn, -1) == cls) {
+ if (!arch_irn_is_ignore(irn) &&
+ arch_get_irn_reg_class_out(irn) == cls) {
plist_insert_back(rss->nodes, skip_Proj(irn));
}
//}
rss.h = heights_new(irg);
rss.nodes = plist_new();
rss.opts = &rss_options;
- rss.liveness = be_liveness(birg);
+ rss.liveness = be_liveness(irg);
be_liveness_assure_sets(rss.liveness);
irg_block_walk_graph(irg, NULL, process_block, &rss);
heights_free(rss.h);