static const arch_register_req_t *
be_node_get_irn_reg_req(const arch_irn_ops_t *self, arch_register_req_t *req, const ir_node *irn, int pos)
{
- int out_pos = redir_proj((const ir_node **) &irn, pos);
+ int out_pos = pos;
- if(pos < 0 && get_irn_mode(irn) == mode_T)
- return NULL;
+ if(pos < 0) {
+ if(get_irn_mode(irn) == mode_T)
+ return NULL;
- if(!is_be_node(irn))
- return NULL;
+ out_pos = redir_proj((const ir_node **) &irn, pos);
+ assert(is_be_node(irn));
+ return put_out_reg_req(req, irn, out_pos);
+ }
- req = pos >= 0 ? put_in_reg_req(req, irn, pos) : put_out_reg_req(req, irn, out_pos);
+ else {
+ return is_be_node(irn) ? put_in_reg_req(req, irn, pos) : NULL;
+ }
return req;
}
case dump_node_nodeattr_txt:
break;
case dump_node_info_txt:
+ fprintf(f, "reg class: %s\n", at->cls->name);
for(i = 0; i < at->n_outs; ++i) {
const arch_register_t *reg = at->reg_data[i].reg;
fprintf(f, "reg #%d: %s\n", i, reg ? reg->name : "n/a");
if(get_irn_be_opcode(irn) == beo_Spill) {
be_spill_attr_t *a = (be_spill_attr_t *) at;
ir_fprintf(f, "spill context: %+F\n", a->spill_ctx);
- ir_fprintf(f, "spill offset: %u\n", a->offset);
+ ir_fprintf(f, "spill offset: %04x (%u)\n", a->offset);
}
break;
}
}
n = pset_count(live);
+
+ if(n == 0)
+ return NULL;
+
nodes = malloc(n * sizeof(nodes[0]));
DBG((dbg, LEVEL_1, "live:\n"));