{ "firm", &firm_isa },
{ "ia32", &ia32_isa_if },
{ "arm", &arm_isa_if },
- { "ppc", &ppc32_isa_if },
+ { "ppc32", &ppc32_isa_if },
{ "mips", &mips_isa_if },
{ NULL, NULL }
};
LC_OPT_ENT_ENUM_MASK("dump", "dump irg on several occasions", &dump_var),
LC_OPT_ENT_ENUM_PTR("ra", "register allocator", &ra_var),
LC_OPT_ENT_ENUM_PTR("isa", "the instruction set architecture", &isa_var),
+ LC_OPT_ENT_NEGBOOL("noomitfp", "do not omit frame pointer", &be_omit_fp),
#ifdef WITH_ILP
LC_OPT_ENT_STR ("ilp.server", "the ilp server name", be_options.ilp_server, sizeof(be_options.ilp_server)),
phi_class_init();
}
-static be_main_env_t *be_init_env(be_main_env_t *env)
+static be_main_env_t *be_init_env(be_main_env_t *env, FILE *file_handle)
{
memset(env, 0, sizeof(*env));
obstack_init(&env->obst);
env->options = &be_options;
FIRM_DBG_REGISTER(env->dbg, "be.main");
- arch_env_init(env->arch_env, isa_if);
+ arch_env_init(env->arch_env, isa_if, file_handle);
/* Register the irn handler of the architecture */
if (arch_isa_get_irn_handler(env->arch_env->isa))
arch_isa_t *isa;
be_main_env_t env;
- be_init_env(&env);
+ be_init_env(&env, file_handle);
isa = arch_env_get_isa(env.arch_env);
cg_if = isa->impl->get_code_generator_if(isa);
/* get a code generator for this graph. */
- birg.cg = cg_if->init(file_handle, &birg);
+ birg.cg = cg_if->init(&birg);
/* create the code generator and generate code. */
prepare_graph(&birg);
dump(DUMP_FINAL, irg, "-end", dump_ir_block_graph_sched);
be_abi_free(birg.abi);
- free_ir_graph(irg);
+// free_ir_graph(irg);
}
be_done_env(&env);