#include "execfreq.h"
#include "bearch.h"
-
#include "be_t.h"
#include "bemodule.h"
#include "beutil.h"
#include "bestat.h"
#include "beverify.h"
#include "beprofile.h"
-#include "beblocksched.h"
#include "be_dbgout.h"
#ifdef WITH_ILP
{
be_opt_register();
be_init_modules();
- phi_class_init();
if (isa_if->get_params)
return isa_if->get_params();
/* reset the phi handler. */
be_phi_handler_reset(env->phi_handler);
+
+ set_irg_phase_state(irg, phase_backend);
}
#ifdef WITH_LIBCORE
static const char suffix[] = ".prof";
be_irg_t *birgs;
unsigned num_birgs;
-
- be_ra_timer_t *ra_timer;
+ ir_graph **irg_list, **backend_irg_list;
#ifdef WITH_LIBCORE
lc_timer_t *t_abi = NULL;
be_dbg_so(env.db_handle, cup_name);
be_dbg_types(env.db_handle);
+ /* backend may provide an ordered list of irgs where code should be generated for */
+ irg_list = NEW_ARR_F(ir_graph *, 0);
+ backend_irg_list = arch_isa_get_backend_irg_list(isa, &irg_list);
+
/* we might need 1 birg more for instrumentation constructor */
- num_birgs = get_irp_n_irgs();
+ num_birgs = backend_irg_list ? ARR_LEN(backend_irg_list) : get_irp_n_irgs();
birgs = alloca(sizeof(birgs[0]) * (num_birgs + 1));
/* First: initialize all birgs */
- for(i = 0; i < get_irp_n_irgs(); ++i) {
- ir_graph *irg = get_irp_irg(i);
-
+ for(i = 0; i < num_birgs; ++i) {
+ ir_graph *irg = backend_irg_list ? backend_irg_list[i] : get_irp_irg(i);
initialize_birg(&birgs[i], irg, &env);
}
+ DEL_ARR_F(irg_list);
/*
Get the filename for the profiling data.
initialize_birg(&birgs[num_birgs], prof_init_irg, &env);
num_birgs++;
set_method_img_section(get_irg_entity(prof_init_irg), section_constructors);
- }
- else {
+ } else {
be_profile_read(prof_filename);
}
/* For all graphs */
for (i = 0; i < num_birgs; ++i) {
- be_irg_t *birg = & birgs[i];
+ be_irg_t *birg = &birgs[i];
ir_graph *irg = birg->irg;
optimization_state_t state;
const arch_code_generator_if_t *cg_if;
}
BE_TIMER_POP(t_verify);
- /**
- * Create execution frequencies from profile data or estimate some
- */
- if (be_profile_has_data()) {
- birg->exec_freq = be_create_execfreqs_from_profile(irg);
- } else {
- birg->exec_freq = compute_execfreq(irg, 10);
- }
-
BE_TIMER_ONLY(num_nodes_b = get_num_reachable_nodes(irg));
/* Get the code generator interface. */
dump(DUMP_ABI, irg, "-abi", dump_ir_block_graph);
be_do_stat_nodes(irg, "02 Abi");
+ if (be_options.vrfy_option == BE_VRFY_WARN) {
+ be_check_dominance(irg);
+ be_verify_out_edges(irg);
+ } else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
+ assert(be_verify_out_edges(irg));
+ assert(be_check_dominance(irg) && "Dominance verification failed");
+ }
+
/* generate code */
BE_TIMER_PUSH(t_codegen);
arch_code_generator_prepare_graph(birg->cg);
be_do_stat_nodes(irg, "03 Prepare");
- /*
- Since the code generator made a lot of new nodes and skipped
- a lot of old ones, we should do dead node elimination here.
- Note that this requires disabling the edges here.
- */
- edges_deactivate(irg);
- //dead_node_elimination(irg);
- edges_activate(irg);
-
- /* Compute loop nesting information (for weighting copies) */
dump(DUMP_PREPARED, irg, "-prepared", dump_ir_block_graph);
BE_TIMER_ONLY(num_nodes_r = get_num_reachable_nodes(irg));
+ if (be_options.vrfy_option == BE_VRFY_WARN) {
+ be_check_dominance(irg);
+ be_verify_out_edges(irg);
+ } else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
+ assert(be_verify_out_edges(irg));
+ assert(be_check_dominance(irg) && "Dominance verification failed");
+ }
+
+ /**
+ * Create execution frequencies from profile data or estimate some
+ */
+ if (be_profile_has_data()) {
+ birg->exec_freq = be_create_execfreqs_from_profile(irg);
+ } else {
+ birg->exec_freq = compute_execfreq(irg, 10);
+ }
+
/* let backend prepare scheduling */
BE_TIMER_PUSH(t_codegen);
arch_code_generator_before_sched(birg->cg);
be_abi_fix_stack_bias(birg->abi);
BE_TIMER_POP(t_abi);
+ dump(DUMP_SCHED, irg, "-fix_stack_after_ra", dump_ir_block_graph_sched);
+
BE_TIMER_PUSH(t_finish);
arch_code_generator_finish(birg->cg);
BE_TIMER_POP(t_finish);
/* check schedule and register allocation */
BE_TIMER_PUSH(t_verify);
if (be_options.vrfy_option == BE_VRFY_WARN) {
- //irg_verify(irg, VRFY_ENFORCE_SSA);
+ irg_verify(irg, VRFY_ENFORCE_SSA);
be_check_dominance(irg);
be_verify_out_edges(irg);
be_verify_schedule(irg);
be_verify_register_allocation(env.arch_env, irg);
- }
- else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
- //assert(irg_verify(irg, VRFY_ENFORCE_SSA) && "irg verification failed");
- assert(be_verify_out_edges(irg));
+ be_verify_spillslots(env.arch_env, irg);
+ } else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
+ assert(irg_verify(irg, VRFY_ENFORCE_SSA) && "irg verification failed");
+ assert(be_verify_out_edges(irg) && "out edge verification failed");
assert(be_check_dominance(irg) && "Dominance verification failed");
assert(be_verify_schedule(irg) && "Schedule verification failed");
assert(be_verify_register_allocation(env.arch_env, irg)
&& "register allocation verification failed");
+ assert(be_verify_spillslots(env.arch_env, irg) && "Spillslot verification failed");
+
}
BE_TIMER_POP(t_verify);
arch_code_generator_done(birg->cg);
BE_TIMER_POP(t_emit);
- dump(DUMP_FINAL, irg, "-end", dump_ir_extblock_graph_sched);
+ dump(DUMP_FINAL, irg, "-end", dump_ir_block_graph_sched);
BE_TIMER_PUSH(t_abi);
be_abi_free(birg->abi);
LC_EMIT(t_sched);
LC_EMIT(t_constr);
LC_EMIT(t_regalloc);
- LC_EMIT_RA(ra_timer->t_prolog);
- LC_EMIT_RA(ra_timer->t_live);
- LC_EMIT_RA(ra_timer->t_spill);
- LC_EMIT_RA(ra_timer->t_spillslots);
- LC_EMIT_RA(ra_timer->t_color);
- LC_EMIT_RA(ra_timer->t_ifg);
- LC_EMIT_RA(ra_timer->t_copymin);
- LC_EMIT_RA(ra_timer->t_ssa);
- LC_EMIT_RA(ra_timer->t_epilog);
- LC_EMIT_RA(ra_timer->t_verify);
- LC_EMIT_RA(ra_timer->t_other);
+ if(global_ra_timer != NULL) {
+ LC_EMIT_RA(global_ra_timer->t_prolog);
+ LC_EMIT_RA(global_ra_timer->t_live);
+ LC_EMIT_RA(global_ra_timer->t_spill);
+ LC_EMIT_RA(global_ra_timer->t_spillslots);
+ LC_EMIT_RA(global_ra_timer->t_color);
+ LC_EMIT_RA(global_ra_timer->t_ifg);
+ LC_EMIT_RA(global_ra_timer->t_copymin);
+ LC_EMIT_RA(global_ra_timer->t_ssa);
+ LC_EMIT_RA(global_ra_timer->t_epilog);
+ LC_EMIT_RA(global_ra_timer->t_verify);
+ LC_EMIT_RA(global_ra_timer->t_other);
+ }
LC_EMIT(t_finish);
LC_EMIT(t_emit);
LC_EMIT(t_verify);
be_free_birg(birg);
/* switched off due to statistics (statistic module needs all irgs) */
+#if 0 /* STA needs irgs */
#ifdef FIRM_STATISTICS
if (! stat_is_active())
-#endif
+#endif /* FIRM_STATISTICS */
free_ir_graph(irg);
-
+#endif /* if 0 */
if(be_stat_ev_is_active()) {
be_stat_ev_pop();
}