* @date 25.11.2004
* @version $Id$
*/
-#ifdef HAVE_CONFIG_H
#include "config.h"
-#endif
#include <stdarg.h>
#include <stdio.h>
LC_OPT_ENT_BOOL ("omitleaffp", "omit frame pointer in leaf routines", &be_options.omit_leaf_fp),
LC_OPT_ENT_BOOL ("pic", "create PIC code", &be_options.pic),
LC_OPT_ENT_BOOL ("gprof", "create gprof profiling code", &be_options.gprof),
- LC_OPT_ENT_ENUM_PTR ("vrfy", "verify the backend irg", &vrfy_var),
+ LC_OPT_ENT_ENUM_PTR ("verify", "verify the backend irg", &vrfy_var),
LC_OPT_ENT_BOOL ("time", "get backend timing statistics", &be_options.timing),
LC_OPT_ENT_BOOL ("profile", "instrument the code for execution count profiling", &be_options.opt_profile),
LC_OPT_ENT_ENUM_PTR ("sched", "select a scheduler", &sched_var),
}
}
- if ( ((flags & ASM_CONSTRAINT_FLAG_MODIFIER_WRITE)
- && (flags & ASM_CONSTRAINT_FLAG_MODIFIER_NO_WRITE))
- || ((flags & ASM_CONSTRAINT_FLAG_MODIFIER_READ
- && (flags & ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ)))) {
+ if ((
+ flags & ASM_CONSTRAINT_FLAG_MODIFIER_WRITE &&
+ flags & ASM_CONSTRAINT_FLAG_MODIFIER_NO_WRITE
+ ) || (
+ flags & ASM_CONSTRAINT_FLAG_MODIFIER_READ &&
+ flags & ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ
+ )) {
flags |= ASM_CONSTRAINT_FLAG_INVALID;
}
- if (! (flags & (ASM_CONSTRAINT_FLAG_MODIFIER_READ
- | ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
- | ASM_CONSTRAINT_FLAG_MODIFIER_NO_WRITE
- | ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ))) {
+ if (!(flags & (ASM_CONSTRAINT_FLAG_MODIFIER_READ |
+ ASM_CONSTRAINT_FLAG_MODIFIER_WRITE |
+ ASM_CONSTRAINT_FLAG_MODIFIER_NO_WRITE |
+ ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ)
+ )) {
flags |= ASM_CONSTRAINT_FLAG_MODIFIER_READ;
}
return flags;
}
-bool be_is_valid_clobber(const char *clobber)
+int be_is_valid_clobber(const char *clobber)
{
/* memory is a valid clobber. (the frontend has to detect this case too,
* because it has to add memory edges to the asm) */
if (strcmp(clobber, "memory") == 0)
- return true;
+ return 1;
/* cc (condition code) is always valid */
if (strcmp(clobber, "cc") == 0)
- return true;
+ return 1;
return isa_if->is_valid_clobber(isa_if, clobber);
}
lc_opt_entry_t *be_grp;
static int run_once = 0;
- if (run_once) {
+ if (run_once)
return;
- }
- run_once = 1;
-
- be_init_modules();
+ run_once = 1;
be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
lc_opt_add_table(be_grp, be_main_options);
be_add_module_list_opt(be_grp, "isa", "the instruction set architecture",
&isa_ifs, (void**) &isa_if);
+
+ be_init_modules();
}
/* Parse one argument. */
int be_parse_arg(const char *arg) {
lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
if (strcmp(arg, "help") == 0 || (arg[0] == '?' && arg[1] == '\0')) {
- lc_opt_print_help(be_grp, stdout);
+ lc_opt_print_help_for_entry(be_grp, '-', stdout);
return -1;
}
return lc_opt_from_single_arg(be_grp, NULL, arg, NULL);
memset(asm_constraint_flags, 0, sizeof(asm_constraint_flags));
env->arch_env = arch_env_init(isa_if, file_handle, env);
- be_phi_handler_new(env);
+ be_phi_handler_new();
be_dbg_open();
return env;
dump(DUMP_INITIAL, irg, "-begin", dump_ir_block_graph);
- be_stat_init_irg(env->arch_env, irg);
- be_do_stat_nodes(irg, "01 Begin");
-
/* set the current graph (this is important for several firm functions) */
current_ir_graph = irg;
be_timing = (be_options.timing == BE_TIME_ON);
if (be_timing) {
- t_abi = ir_timer_register("time_beabi", "be abi introduction");
- t_codegen = ir_timer_register("time_codegen", "codegeneration");
- t_sched = ir_timer_register("time_sched", "scheduling");
- t_constr = ir_timer_register("time_constr", "assure constraints");
- t_finish = ir_timer_register("time_finish", "graph finish");
- t_emit = ir_timer_register("time_emiter", "code emiter");
- t_verify = ir_timer_register("time_verify", "graph verification");
- t_other = ir_timer_register("time_other", "other");
- t_heights = ir_timer_register("time_heights", "heights");
- t_live = ir_timer_register("time_liveness", "be liveness");
- t_execfreq = ir_timer_register("time_execfreq", "execfreq");
- t_ssa_constr = ir_timer_register("time_ssa_constr", "ssa reconstruction");
- t_ra_prolog = ir_timer_register("time_ra_prolog", "regalloc prolog");
- t_ra_epilog = ir_timer_register("time_ra_epilog", "regalloc epilog");
- t_ra_constr = ir_timer_register("time_ra_constr", "regalloc constraints");
- t_ra_spill = ir_timer_register("time_ra_spill", "spiller");
+ t_abi = ir_timer_register("bemain_time_beabi", "be abi introduction");
+ t_codegen = ir_timer_register("bemain_time_codegen", "codegeneration");
+ t_sched = ir_timer_register("bemain_time_sched", "scheduling");
+ t_constr = ir_timer_register("bemain_time_constr", "assure constraints");
+ t_finish = ir_timer_register("bemain_time_finish", "graph finish");
+ t_emit = ir_timer_register("bemain_time_emiter", "code emiter");
+ t_verify = ir_timer_register("bemain_time_verify", "graph verification");
+ t_other = ir_timer_register("bemain_time_other", "other");
+ t_heights = ir_timer_register("bemain_time_heights", "heights");
+ t_live = ir_timer_register("bemain_time_liveness", "be liveness");
+ t_execfreq = ir_timer_register("bemain_time_execfreq", "execfreq");
+ t_ssa_constr = ir_timer_register("bemain_time_ssa_constr", "ssa reconstruction");
+ t_ra_prolog = ir_timer_register("bemain_time_ra_prolog", "regalloc prolog");
+ t_ra_epilog = ir_timer_register("bemain_time_ra_epilog", "regalloc epilog");
+ t_ra_constr = ir_timer_register("bemain_time_ra_constr", "regalloc constraints");
+ t_ra_spill = ir_timer_register("bemain_time_ra_spill", "spiller");
t_ra_spill_apply
- = ir_timer_register("time_ra_spill_apply", "apply spills");
- t_ra_color = ir_timer_register("time_ra_color", "graph coloring");
- t_ra_ifg = ir_timer_register("time_ra_ifg", "interference graph");
- t_ra_copymin = ir_timer_register("time_ra_copymin", "copy minimization");
- t_ra_ssa = ir_timer_register("time_ra_ssadestr", "ssa destruction");
- t_ra_other = ir_timer_register("time_ra_other", "regalloc other");
+ = ir_timer_register("bemain_time_ra_spill_apply", "apply spills");
+ t_ra_color = ir_timer_register("bemain_time_ra_color", "graph coloring");
+ t_ra_ifg = ir_timer_register("bemain_time_ra_ifg", "interference graph");
+ t_ra_copymin = ir_timer_register("bemain_time_ra_copymin", "copy minimization");
+ t_ra_ssa = ir_timer_register("bemain_time_ra_ssadestr", "ssa destruction");
+ t_ra_other = ir_timer_register("bemain_time_ra_other", "regalloc other");
}
be_init_env(&env, file_handle);
arch_env = env.arch_env;
- /* backend may provide an ordered list of irgs where code should be generated for */
+ /* backend may provide an ordered list of irgs where code should be
+ * generated for */
irg_list = NEW_ARR_F(ir_graph *, 0);
backend_irg_list = arch_env_get_backend_irg_list(arch_env, &irg_list);
/* set the current graph (this is important for several firm functions) */
current_ir_graph = irg;
-#if 0
- {
- unsigned percent = 100*i/num_birgs;
- ir_printf("%u.%02u %+F\n", percent/100, percent%100, irg);
- }
-#endif
be_sched_init_phase(irg);
/* reset the phi handler. */
be_phi_handler_reset();
- stat_ev_ctx_push_fobj("bemain_irg", irg);
+ stat_ev_if {
+ stat_ev_ctx_push_fobj("bemain_irg", irg);
+ be_stat_ev("bemain_insns_start", be_count_insns(irg));
+ be_stat_ev("bemain_blocks_start", be_count_blocks(irg));
+ }
/* stop and reset timers */
BE_TIMER_PUSH(t_other); /* t_other */
BE_TIMER_POP(t_abi);
dump(DUMP_ABI, irg, "-abi", dump_ir_block_graph);
- be_do_stat_nodes(irg, "02 Abi");
if (be_options.vrfy_option == BE_VRFY_WARN) {
be_check_dominance(irg);
}
/* generate code */
- stat_ev_ctx_push_str("bemain_phase", "prepare");
BE_TIMER_PUSH(t_codegen);
arch_code_generator_prepare_graph(birg->cg);
BE_TIMER_POP(t_codegen);
- stat_ev_ctx_pop("bemain_phase");
/* reset the phi handler. */
be_phi_handler_reset();
- be_do_stat_nodes(irg, "03 Prepare");
-
dump(DUMP_PREPARED, irg, "-prepared", dump_ir_block_graph);
if (be_options.vrfy_option == BE_VRFY_WARN) {
*/
if (ir_profile_has_data())
birg->exec_freq = ir_create_execfreqs_from_profile(irg);
- else
+ else {
+ /* TODO: edges are corrupt for EDGE_KIND_BLOCK after the local
+ * optimize graph phase merges blocks in the x86 backend */
+ edges_deactivate(irg);
birg->exec_freq = compute_execfreq(irg, 10);
+ }
BE_TIMER_POP(t_execfreq);
/* be_live_chk_compare(birg); */
/* let backend prepare scheduling */
- stat_ev_ctx_push_str("bemain_phase", "before_sched");
BE_TIMER_PUSH(t_codegen);
arch_code_generator_before_sched(birg->cg);
BE_TIMER_POP(t_codegen);
- stat_ev_ctx_pop("bemain_phase");
/* schedule the irg */
BE_TIMER_PUSH(t_sched);
be_sched_vrfy(birg, be_options.vrfy_option);
BE_TIMER_POP(t_verify);
- be_do_stat_nodes(irg, "04 Schedule");
-
/* introduce patterns to assure constraints */
BE_TIMER_PUSH(t_constr);
/* we switch off optimizations here, because they might cause trouble */
set_opt_normalize(0);
set_opt_cse(0);
- assert(!get_opt_cse());
-
/* add Keeps for should_be_different constrained nodes */
/* beware: needs schedule due to usage of be_ssa_constr */
assure_constraints(birg);
BE_TIMER_POP(t_constr);
dump(DUMP_SCHED, irg, "-assured", dump_ir_block_graph_sched);
- be_do_stat_nodes(irg, "05 Constraints");
/* stuff needs to be done after scheduling but before register allocation */
BE_TIMER_PUSH(t_codegen);
be_sched_vrfy(birg, be_options.vrfy_option);
BE_TIMER_POP(t_verify);
- /* do some statistics */
- //be_do_stat_reg_pressure(birg);
-
-#ifdef FIRM_STATISTICS
- stat_ev_dbl("costs_before_ra", be_estimate_irg_costs(irg, arch_env, birg->exec_freq));
-#endif
+ stat_ev_if {
+ stat_ev_dbl("bemain_costs_before_ra",
+ be_estimate_irg_costs(irg, birg->exec_freq));
+ be_stat_ev("bemain_insns_before_ra", be_count_insns(irg));
+ be_stat_ev("bemain_blocks_before_ra", be_count_blocks(irg));
+ }
/* Do register allocation */
be_allocate_registers(birg);
#ifdef FIRM_STATISTICS
- stat_ev_dbl("costs_before_ra", be_estimate_irg_costs(irg, arch_env, birg->exec_freq));
+ stat_ev_dbl("bemain_costs_before_ra", be_estimate_irg_costs(irg, birg->exec_freq));
#endif
dump(DUMP_RA, irg, "-ra", dump_ir_block_graph_sched);
- be_do_stat_nodes(irg, "06 Register Allocation");
/* let the code generator prepare the graph for emitter */
BE_TIMER_PUSH(t_finish);
dump(DUMP_FINAL, irg, "-finish", dump_ir_block_graph_sched);
+ stat_ev_if {
+ be_stat_ev("bemain_insns_finish", be_count_insns(irg));
+ be_stat_ev("bemain_blocks_finish", be_count_blocks(irg));
+ }
+
/* check schedule and register allocation */
BE_TIMER_PUSH(t_verify);
if (be_options.vrfy_option == BE_VRFY_WARN) {
be_abi_free(birg->abi);
BE_TIMER_POP(t_abi);
- be_do_stat_nodes(irg, "07 Final");
restore_optimization_state(&state);
BE_TIMER_POP(t_other);
be_sched_free_phase(irg);
be_free_birg(birg);
-
- /* switched off due to statistics (statistic module needs all irgs) */
-#if 0 /* STA needs irgs */
-#ifdef FIRM_STATISTICS
- if (! stat_is_active())
-#endif /* FIRM_STATISTICS */
- free_ir_graph(irg);
-#endif /* if 0 */
stat_ev_ctx_pop("bemain_irg");
}
ir_profile_free();
/* The user specified another config file to read. do that now. */
if (config_file[0] != '\0') {
- FILE *f;
+ FILE *f = fopen(config_file, "rt");
- if ((f = fopen(config_file, "rt")) != NULL) {
+ if (f != NULL) {
lc_opt_from_file(config_file, f, NULL);
fclose(f);
+ } else {
+ fprintf(stderr, "Warning: Cannot open config file '%s'\n", config_file);
}
}
be_options.statev = 1;
stat_ev_begin(buf, be_options.filtev);
+ stat_ev_ctx_push_str("bemain_compilation_unit", cup_name);
}
#endif
ir_timer_stop(t);
ir_timer_leave_high_priority();
stat_ev_if {
- stat_ev_dbl("backend_time", ir_timer_elapsed_msec(t));
+ stat_ev_dbl("bemain_backend_time", ir_timer_elapsed_msec(t));
} else {
printf("%-20s: %lu msec\n", "BEMAINLOOP", ir_timer_elapsed_msec(t));
}
}
#ifdef FIRM_STATISTICS
- if (be_options.statev)
+ if (be_options.statev) {
+ stat_ev_ctx_pop("bemain_compilation_unit");
stat_ev_end();
+ }
#endif
}
else
bitset_clear_all(bs);
- assert(bitset_size(bs) == (unsigned)cls->n_regs);
- arch_put_non_ignore_regs(birg->main_env->arch_env, cls, bs);
+ assert(bitset_size(bs) == cls->n_regs);
+ arch_put_non_ignore_regs(cls, bs);
bitset_flip_all(bs);
be_abi_put_ignore_regs(birg->abi, cls, bs);
projects / libfirm / blobdiff