the delayed nodes are also counted in register pressure, subtract them form there

[libfirm] / ir / be / bemain.c

diff --git a/ir/be/bemain.c b/ir/be/bemain.c
index c9a0605..3cdbab6 100644 (file)
--- a/ir/be/bemain.c
+++ b/ir/be/bemain.c
@@ -373,8 +373,7 @@ static void be_main_loop(FILE *file_handle, const char *cup_name)
        static const char suffix[] = ".prof";
        be_irg_t *birgs;
        unsigned num_birgs;
-
-       be_ra_timer_t *ra_timer;
+       ir_graph **irg_list, **backend_irg_list;
 
 #ifdef WITH_LIBCORE
        lc_timer_t *t_abi      = NULL;
@@ -407,16 +406,20 @@ static void be_main_loop(FILE *file_handle, const char *cup_name)
        be_dbg_so(env.db_handle, cup_name);
        be_dbg_types(env.db_handle);
 
+       /* backend may provide an ordered list of irgs where code should be generated for */
+       irg_list         = NEW_ARR_F(ir_graph *, 0);
+       backend_irg_list = arch_isa_get_backend_irg_list(isa, &irg_list);
+
        /* we might need 1 birg more for instrumentation constructor */
-       num_birgs = get_irp_n_irgs();
+       num_birgs = backend_irg_list ? ARR_LEN(backend_irg_list) : get_irp_n_irgs();
        birgs     = alloca(sizeof(birgs[0]) * (num_birgs + 1));
 
        /* First: initialize all birgs */
-       for(i = 0; i < get_irp_n_irgs(); ++i) {
-               ir_graph *irg = get_irp_irg(i);
-
+       for(i = 0; i < num_birgs; ++i) {
+               ir_graph *irg = backend_irg_list ? backend_irg_list[i] : get_irp_irg(i);
                initialize_birg(&birgs[i], irg, &env);
        }
+       DEL_ARR_F(irg_list);
 
        /*
                Get the filename for the profiling data.
@@ -435,14 +438,13 @@ static void be_main_loop(FILE *file_handle, const char *cup_name)
                initialize_birg(&birgs[num_birgs], prof_init_irg, &env);
                num_birgs++;
                set_method_img_section(get_irg_entity(prof_init_irg), section_constructors);
-       }
-       else {
+       } else {
                be_profile_read(prof_filename);
        }
 
        /* For all graphs */
        for (i = 0; i < num_birgs; ++i) {
-               be_irg_t *birg = & birgs[i];
+               be_irg_t *birg = &birgs[i];
                ir_graph *irg  = birg->irg;
                optimization_state_t state;
                const arch_code_generator_if_t *cg_if;
@@ -510,8 +512,7 @@ static void be_main_loop(FILE *file_handle, const char *cup_name)
                if (be_options.vrfy_option == BE_VRFY_WARN) {
                        be_check_dominance(irg);
                        be_verify_out_edges(irg);
-               }
-               else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
+               } else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
                        assert(be_verify_out_edges(irg));
                        assert(be_check_dominance(irg) && "Dominance verification failed");
                }
@@ -523,15 +524,18 @@ static void be_main_loop(FILE *file_handle, const char *cup_name)
 
                be_do_stat_nodes(irg, "03 Prepare");
 
-               /* Compute loop nesting information (for weighting copies) */
+               /* Transformation may produce nodes only reachable via out edges, kill them. */
+#if 1
+               edges_deactivate(irg);
+               edges_activate(irg);
+#endif
                dump(DUMP_PREPARED, irg, "-prepared", dump_ir_block_graph);
                BE_TIMER_ONLY(num_nodes_r = get_num_reachable_nodes(irg));
 
                if (be_options.vrfy_option == BE_VRFY_WARN) {
                        be_check_dominance(irg);
                        be_verify_out_edges(irg);
-               }
-               else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
+               } else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
                        assert(be_verify_out_edges(irg));
                        assert(be_check_dominance(irg) && "Dominance verification failed");
                }
@@ -657,19 +661,21 @@ static void be_main_loop(FILE *file_handle, const char *cup_name)
                /* check schedule and register allocation */
                BE_TIMER_PUSH(t_verify);
                if (be_options.vrfy_option == BE_VRFY_WARN) {
-                       //irg_verify(irg, VRFY_ENFORCE_SSA);
+                       irg_verify(irg, VRFY_ENFORCE_SSA);
                        be_check_dominance(irg);
                        be_verify_out_edges(irg);
                        be_verify_schedule(irg);
                        be_verify_register_allocation(env.arch_env, irg);
-               }
-               else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
-                       //assert(irg_verify(irg, VRFY_ENFORCE_SSA) && "irg verification failed");
-                       assert(be_verify_out_edges(irg));
+                       be_verify_spillslots(env.arch_env, irg);
+               } else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
+                       assert(irg_verify(irg, VRFY_ENFORCE_SSA) && "irg verification failed");
+                       assert(be_verify_out_edges(irg) && "out edge verification failed");
                        assert(be_check_dominance(irg) && "Dominance verification failed");
                        assert(be_verify_schedule(irg) && "Schedule verification failed");
                        assert(be_verify_register_allocation(env.arch_env, irg)
                               && "register allocation verification failed");
+                       assert(be_verify_spillslots(env.arch_env, irg) && "Spillslot verification failed");
+
                }
                BE_TIMER_POP(t_verify);
 
@@ -714,17 +720,19 @@ static void be_main_loop(FILE *file_handle, const char *cup_name)
                        LC_EMIT(t_sched);
                        LC_EMIT(t_constr);
                        LC_EMIT(t_regalloc);
-                       LC_EMIT_RA(ra_timer->t_prolog);
-                       LC_EMIT_RA(ra_timer->t_live);
-                       LC_EMIT_RA(ra_timer->t_spill);
-                       LC_EMIT_RA(ra_timer->t_spillslots);
-                       LC_EMIT_RA(ra_timer->t_color);
-                       LC_EMIT_RA(ra_timer->t_ifg);
-                       LC_EMIT_RA(ra_timer->t_copymin);
-                       LC_EMIT_RA(ra_timer->t_ssa);
-                       LC_EMIT_RA(ra_timer->t_epilog);
-                       LC_EMIT_RA(ra_timer->t_verify);
-                       LC_EMIT_RA(ra_timer->t_other);
+                       if(global_ra_timer != NULL) {
+                               LC_EMIT_RA(global_ra_timer->t_prolog);
+                               LC_EMIT_RA(global_ra_timer->t_live);
+                               LC_EMIT_RA(global_ra_timer->t_spill);
+                               LC_EMIT_RA(global_ra_timer->t_spillslots);
+                               LC_EMIT_RA(global_ra_timer->t_color);
+                               LC_EMIT_RA(global_ra_timer->t_ifg);
+                               LC_EMIT_RA(global_ra_timer->t_copymin);
+                               LC_EMIT_RA(global_ra_timer->t_ssa);
+                               LC_EMIT_RA(global_ra_timer->t_epilog);
+                               LC_EMIT_RA(global_ra_timer->t_verify);
+                               LC_EMIT_RA(global_ra_timer->t_other);
+                       }
                        LC_EMIT(t_finish);
                        LC_EMIT(t_emit);
                        LC_EMIT(t_verify);