unsigned num_birgs;
ir_graph **irg_list, **backend_irg_list;
- be_ra_timer_t *ra_timer;
-
#ifdef WITH_LIBCORE
lc_timer_t *t_abi = NULL;
lc_timer_t *t_codegen = NULL;
initialize_birg(&birgs[num_birgs], prof_init_irg, &env);
num_birgs++;
set_method_img_section(get_irg_entity(prof_init_irg), section_constructors);
- }
- else {
+ } else {
be_profile_read(prof_filename);
}
if (be_options.vrfy_option == BE_VRFY_WARN) {
be_check_dominance(irg);
be_verify_out_edges(irg);
- }
- else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
+ } else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
assert(be_verify_out_edges(irg));
assert(be_check_dominance(irg) && "Dominance verification failed");
}
be_do_stat_nodes(irg, "03 Prepare");
/* Transformation may produce nodes only reachable via out edges, kill them. */
- be_kill_dead_nodes(irg);
+#if 1
+ edges_deactivate(irg);
+ edges_activate(irg);
+#endif
dump(DUMP_PREPARED, irg, "-prepared", dump_ir_block_graph);
BE_TIMER_ONLY(num_nodes_r = get_num_reachable_nodes(irg));
if (be_options.vrfy_option == BE_VRFY_WARN) {
be_check_dominance(irg);
be_verify_out_edges(irg);
- }
- else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
+ } else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
assert(be_verify_out_edges(irg));
assert(be_check_dominance(irg) && "Dominance verification failed");
}
/* check schedule and register allocation */
BE_TIMER_PUSH(t_verify);
if (be_options.vrfy_option == BE_VRFY_WARN) {
- //irg_verify(irg, VRFY_ENFORCE_SSA);
+ irg_verify(irg, VRFY_ENFORCE_SSA);
be_check_dominance(irg);
be_verify_out_edges(irg);
be_verify_schedule(irg);
be_verify_register_allocation(env.arch_env, irg);
- }
- else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
- //assert(irg_verify(irg, VRFY_ENFORCE_SSA) && "irg verification failed");
- assert(be_verify_out_edges(irg));
+ be_verify_spillslots(env.arch_env, irg);
+ } else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
+ assert(irg_verify(irg, VRFY_ENFORCE_SSA) && "irg verification failed");
+ assert(be_verify_out_edges(irg) && "out edge verification failed");
assert(be_check_dominance(irg) && "Dominance verification failed");
assert(be_verify_schedule(irg) && "Schedule verification failed");
assert(be_verify_register_allocation(env.arch_env, irg)
&& "register allocation verification failed");
+ assert(be_verify_spillslots(env.arch_env, irg) && "Spillslot verification failed");
+
}
BE_TIMER_POP(t_verify);
LC_EMIT(t_sched);
LC_EMIT(t_constr);
LC_EMIT(t_regalloc);
- LC_EMIT_RA(ra_timer->t_prolog);
- LC_EMIT_RA(ra_timer->t_live);
- LC_EMIT_RA(ra_timer->t_spill);
- LC_EMIT_RA(ra_timer->t_spillslots);
- LC_EMIT_RA(ra_timer->t_color);
- LC_EMIT_RA(ra_timer->t_ifg);
- LC_EMIT_RA(ra_timer->t_copymin);
- LC_EMIT_RA(ra_timer->t_ssa);
- LC_EMIT_RA(ra_timer->t_epilog);
- LC_EMIT_RA(ra_timer->t_verify);
- LC_EMIT_RA(ra_timer->t_other);
+ if(global_ra_timer != NULL) {
+ LC_EMIT_RA(global_ra_timer->t_prolog);
+ LC_EMIT_RA(global_ra_timer->t_live);
+ LC_EMIT_RA(global_ra_timer->t_spill);
+ LC_EMIT_RA(global_ra_timer->t_spillslots);
+ LC_EMIT_RA(global_ra_timer->t_color);
+ LC_EMIT_RA(global_ra_timer->t_ifg);
+ LC_EMIT_RA(global_ra_timer->t_copymin);
+ LC_EMIT_RA(global_ra_timer->t_ssa);
+ LC_EMIT_RA(global_ra_timer->t_epilog);
+ LC_EMIT_RA(global_ra_timer->t_verify);
+ LC_EMIT_RA(global_ra_timer->t_other);
+ }
LC_EMIT(t_finish);
LC_EMIT(t_emit);
LC_EMIT(t_verify);