if (in_out) {
for (i = 0; i < n; i++) {
/* out register matches */
- if (pairs[i].out_reg->index == reg_idx)
+ if ((int) pairs[i].out_reg->index == reg_idx)
return i;
}
}
else {
for (i = 0; i < n; i++) {
/* in register matches */
- if (pairs[i].in_reg->index == reg_idx)
+ if ((int) pairs[i].in_reg->index == reg_idx)
return i;
}
}
node = sched_prev(perm);
n_moved = 0;
while(!sched_is_begin(node)) {
- int input = -1;
- ir_node *proj;
+ const arch_register_req_t *req;
+ int input = -1;
+ ir_node *proj;
foreach_out_edge(perm, edge) {
ir_node *out = get_edge_src_irn(edge);
break;
if(arch_irn_is(aenv, node, modify_flags))
break;
+ if(is_Proj(node)) {
+ req = arch_get_register_req(aenv, get_Proj_pred(node),
+ -1 - get_Proj_proj(node));
+ } else {
+ req = arch_get_register_req(aenv, node, -1);
+ }
+ if(req->type != arch_register_req_type_normal)
+ break;
for(i = get_irn_arity(node) - 1; i >= 0; --i) {
ir_node *opop = get_irn_n(node, i);
if (arch_irn_consider_in_reg_alloc(aenv, cls, opop)) {