* @author Sebastian Hack
* @cvs-id $Id$
*
- * Copyright (C) 2005 Universitaet Karlsruhe
+ * Copyright (C) 2005-2006 Universitaet Karlsruhe
* Released under the GPL
*
* Driver for the chordal register allocator.
#include <libcore/lc_timing.h>
#endif /* WITH_LIBCORE */
+#include "ircons_t.h"
#include "irmode_t.h"
#include "irgraph_t.h"
#include "irprintf_t.h"
BE_CH_VRFY_WARN,
};
+/** Enable extreme live range splitting. */
+static int be_elr_split = 0;
+
+/** Assumed loop iteration count for execution frequency estimation. */
+static int be_loop_weight = 9;
+
+#ifdef WITH_LIBCORE
static be_ra_timer_t ra_timer = {
NULL,
NULL,
NULL,
NULL,
NULL,
+ NULL,
};
-#ifdef WITH_LIBCORE
static const lc_opt_enum_int_items_t spill_items[] = {
{ "morgan", BE_CH_SPILL_MORGAN },
{ "belady", BE_CH_SPILL_BELADY },
};
static const lc_opt_enum_int_items_t dump_items[] = {
- { "spill", BE_CH_DUMP_SPILL },
- { "live", BE_CH_DUMP_LIVE },
- { "color", BE_CH_DUMP_COLOR },
- { "copymin", BE_CH_DUMP_COPYMIN },
- { "ssadestr", BE_CH_DUMP_SSADESTR },
- { "tree", BE_CH_DUMP_TREE_INTV },
- { "constr", BE_CH_DUMP_CONSTR },
- { "lower", BE_CH_DUMP_LOWER },
- { "appel", BE_CH_DUMP_APPEL },
- { "all", BE_CH_DUMP_ALL },
+ { "spill", BE_CH_DUMP_SPILL },
+ { "live", BE_CH_DUMP_LIVE },
+ { "color", BE_CH_DUMP_COLOR },
+ { "copymin", BE_CH_DUMP_COPYMIN },
+ { "ssadestr", BE_CH_DUMP_SSADESTR },
+ { "tree", BE_CH_DUMP_TREE_INTV },
+ { "constr", BE_CH_DUMP_CONSTR },
+ { "lower", BE_CH_DUMP_LOWER },
+ { "spillslots", BE_CH_DUMP_SPILLSLOTS },
+ { "appel", BE_CH_DUMP_APPEL },
+ { "all", BE_CH_DUMP_ALL },
{ NULL, 0 }
};
&options.vrfy_option, be_ch_vrfy_items
};
-/** Enable extreme live range splitting. */
-static int be_elr_split = 0;
-
-/** Assumed loop iteration count for execution frequency estimation. */
-static int be_loop_weight = 9;
-
static const lc_opt_table_entry_t be_chordal_options[] = {
LC_OPT_ENT_ENUM_INT ("spill", "spill method (belady, morgan or remat)", &spill_var),
LC_OPT_ENT_ENUM_PTR ("ifg", "interference graph flavour (std, fast, clique, pointer, list, check)", &ifg_flavor_var),
{ NULL }
};
+extern void be_spill_remat_register_options(lc_opt_entry_t *ent);
+
+
static void be_ra_chordal_register_options(lc_opt_entry_t *grp)
{
static int run_once = 0;
chordal_grp = lc_opt_get_grp(grp, "chordal");
lc_opt_add_table(chordal_grp, be_chordal_options);
- }
- co_register_options(chordal_grp);
- be_java_coal_register_options(chordal_grp);
+ co_register_options(chordal_grp);
+ be_java_coal_register_options(chordal_grp);
+#ifdef WITH_ILP
+ be_spill_remat_register_options(chordal_grp);
+#endif
+ }
}
#endif /* WITH_LIBCORE */
const arch_env_t *aenv = cenv->birg->main_env->arch_env;
const ir_edge_t *edge, *ne;
ir_node *block;
+ ir_node *spill;
if (! be_is_Reload(irn))
return;
+ // only use memory operands, if the reload is only used by 1 node
+ if(get_irn_n_edges(irn) > 1)
+ return;
+
+ spill = be_get_Reload_mem(irn);
block = get_nodes_block(irn);
foreach_out_edge_safe(irn, edge, ne) {
if (get_nodes_block(src) == block && arch_possible_memory_operand(aenv, src, pos)) {
DBG((cenv->dbg, LEVEL_3, "performing memory operand %+F at %+F\n", irn, src));
- arch_perform_memory_operand(aenv, src, irn, pos);
+ arch_perform_memory_operand(aenv, src, spill, pos);
}
}
irg_walk_graph(chordal_env->irg, NULL, memory_operand_walker, chordal_env);
}
+#ifdef WITH_LIBCORE
/**
- * Performs chordal register allocation for each register class on given irg.
- *
- * @param bi Backend irg object
- * @return Structure containing timer for the single phases or NULL if no timing requested.
+ * Initialize all timers.
*/
-static be_ra_timer_t *be_ra_chordal_main(const be_irg_t *bi)
+static void be_init_timer(be_options_t *main_opts)
{
- const be_main_env_t *main_env = bi->main_env;
- const arch_isa_t *isa = arch_env_get_isa(main_env->arch_env);
- ir_graph *irg = bi->irg;
- be_options_t *main_opts = main_env->options;
- int splitted = 0;
-
- int j, m;
- be_chordal_env_t chordal_env;
-
if (main_opts->timing == BE_TIME_ON) {
ra_timer.t_prolog = lc_timer_register("ra_prolog", "regalloc prolog");
ra_timer.t_epilog = lc_timer_register("ra_epilog", "regalloc epilog");
ra_timer.t_live = lc_timer_register("ra_liveness", "be liveness");
ra_timer.t_spill = lc_timer_register("ra_spill", "spiller");
+ ra_timer.t_spillslots = lc_timer_register("ra_spillslots", "spillslots");
ra_timer.t_color = lc_timer_register("ra_color", "graph coloring");
ra_timer.t_ifg = lc_timer_register("ra_ifg", "interference graph");
ra_timer.t_copymin = lc_timer_register("ra_copymin", "copy minimization");
LC_STOP_AND_RESET_TIMER(ra_timer.t_epilog);
LC_STOP_AND_RESET_TIMER(ra_timer.t_live);
LC_STOP_AND_RESET_TIMER(ra_timer.t_spill);
+ LC_STOP_AND_RESET_TIMER(ra_timer.t_spillslots);
LC_STOP_AND_RESET_TIMER(ra_timer.t_color);
LC_STOP_AND_RESET_TIMER(ra_timer.t_ifg);
LC_STOP_AND_RESET_TIMER(ra_timer.t_copymin);
LC_STOP_AND_RESET_TIMER(ra_timer.t_verify);
LC_STOP_AND_RESET_TIMER(ra_timer.t_other);
}
+}
-#define BE_TIMER_PUSH(timer) \
- if (main_opts->timing == BE_TIME_ON) { \
- int res = lc_timer_push(timer); \
- if (options.vrfy_option == BE_CH_VRFY_ASSERT) \
- assert(res && "Timer already on stack, cannot be pushed twice."); \
- else if (options.vrfy_option == BE_CH_VRFY_WARN && ! res) \
- fprintf(stderr, "Timer %s already on stack, cannot be pushed twice.\n", \
- lc_timer_get_name(timer)); \
+#define BE_TIMER_INIT(main_opts) be_init_timer(main_opts)
+
+#define BE_TIMER_PUSH(timer) \
+ if (main_opts->timing == BE_TIME_ON) { \
+ if (! lc_timer_push(timer)) { \
+ if (options.vrfy_option == BE_CH_VRFY_ASSERT) \
+ assert(!"Timer already on stack, cannot be pushed twice."); \
+ else if (options.vrfy_option == BE_CH_VRFY_WARN) \
+ fprintf(stderr, "Timer %s already on stack, cannot be pushed twice.\n", \
+ lc_timer_get_name(timer)); \
+ } \
}
#define BE_TIMER_POP(timer) \
if (main_opts->timing == BE_TIME_ON) { \
lc_timer_get_name(tmp), lc_timer_get_name(timer)); \
timer = tmp; \
}
+#else
+
+#define BE_TIMER_INIT(main_opts)
+#define BE_TIMER_PUSH(timer)
+#define BE_TIMER_POP(timer)
+
+#endif /* WITH_LIBCORE */
+
+/**
+ * Performs chordal register allocation for each register class on given irg.
+ *
+ * @param bi Backend irg object
+ * @return Structure containing timer for the single phases or NULL if no timing requested.
+ */
+static be_ra_timer_t *be_ra_chordal_main(const be_irg_t *bi)
+{
+ const be_main_env_t *main_env = bi->main_env;
+ const arch_isa_t *isa = arch_env_get_isa(main_env->arch_env);
+ ir_graph *irg = bi->irg;
+ be_options_t *main_opts = main_env->options;
+ int splitted = 0;
+ int j, m;
+ be_chordal_env_t chordal_env;
+
+ BE_TIMER_INIT(main_opts);
BE_TIMER_PUSH(ra_timer.t_other);
BE_TIMER_PUSH(ra_timer.t_prolog);
/* Perform the following for each register class. */
for (j = 0, m = arch_isa_get_n_reg_class(isa); j < m; ++j) {
- //FILE *f;
- copy_opt_t *co = NULL;
-
chordal_env.cls = arch_isa_get_reg_class(isa, j);
chordal_env.border_heads = pmap_create();
chordal_env.ignore_colors = bitset_malloc(chordal_env.cls->n_regs);
);
dump(BE_CH_DUMP_SPILL, irg, chordal_env.cls, "-spill", dump_ir_block_graph_sched);
+
check_for_memory_operands(&chordal_env);
+
be_abi_fix_stack_nodes(bi->abi, chordal_env.lv);
BE_TIMER_PUSH(ra_timer.t_verify);
/* verify schedule and register pressure */
if (options.vrfy_option == BE_CH_VRFY_WARN) {
be_verify_schedule(irg);
- be_verify_register_pressure(chordal_env.birg->main_env->arch_env, chordal_env.cls, irg);
+ be_verify_register_pressure(chordal_env.birg, chordal_env.cls, irg);
}
else if (options.vrfy_option == BE_CH_VRFY_ASSERT) {
assert(be_verify_schedule(irg) && "Schedule verification failed");
- assert(be_verify_register_pressure(chordal_env.birg->main_env->arch_env, chordal_env.cls, irg)
+ assert(be_verify_register_pressure(chordal_env.birg, chordal_env.cls, irg)
&& "Register pressure verification failed");
}
BE_TIMER_POP(ra_timer.t_verify);
bitset_free(chordal_env.ignore_colors);
}
+ BE_TIMER_PUSH(ra_timer.t_spillslots);
+
be_coalesce_spillslots(&chordal_env);
+ dump(BE_CH_DUMP_SPILLSLOTS, irg, NULL, "-spillslots", dump_ir_block_graph_sched);
+
+ BE_TIMER_POP(ra_timer.t_spillslots);
+
+ BE_TIMER_PUSH(ra_timer.t_verify);
+
+ /* verify spillslots */
+ if (options.vrfy_option == BE_CH_VRFY_WARN) {
+ be_verify_spillslots(main_env->arch_env, irg);
+ }
+ else if (options.vrfy_option == BE_CH_VRFY_ASSERT) {
+ assert(be_verify_spillslots(main_env->arch_env, irg) && "Spillslot verification failed");
+ }
+ BE_TIMER_POP(ra_timer.t_verify);
BE_TIMER_PUSH(ra_timer.t_epilog);
BE_TIMER_POP(ra_timer.t_epilog);
BE_TIMER_POP(ra_timer.t_other);
-#undef BE_TIMER_PUSH
-#undef BE_TIMER_POP
-
+#ifdef WITH_LIBCORE
return main_opts->timing == BE_TIME_ON ? &ra_timer : NULL;
+#endif /* WITH_LIBCORE */
+ return NULL;
}
const be_ra_t be_ra_chordal_allocator = {
#ifdef WITH_LIBCORE
be_ra_chordal_register_options,
-#endif
be_ra_chordal_main
+#else
+ 0
+#endif
};
projects / libfirm / blobdiff