/**
* Perform things which need to be done per register class before spilling.
*/
-static void pre_spill(const arch_isa_t *isa, int cls_idx, post_spill_env_t *pse) {
- be_chordal_env_t *chordal_env = &pse->cenv;
- be_irg_t *birg = pse->birg;
- node_stat_t node_stat;
+static void pre_spill(post_spill_env_t *pse, const arch_register_class_t *cls)
+{
+ be_chordal_env_t *chordal_env = &pse->cenv;
+ be_irg_t *birg = pse->birg;
+ ir_graph *irg = be_get_birg_irg(birg);
+ const be_main_env_t *main_env = birg->main_env;
+ node_stat_t node_stat;
- pse->cls = arch_isa_get_reg_class(isa, cls_idx);
- chordal_env->cls = pse->cls;
+ pse->cls = cls;
+ chordal_env->cls = cls;
chordal_env->border_heads = pmap_create();
chordal_env->ignore_colors = bitset_malloc(chordal_env->cls->n_regs);
be_assure_liveness(birg);
be_liveness_assure_chk(be_get_birg_liveness(birg));
- stat_ev_ctx_push("cls", pse->cls->name);
- stat_ev_dbl("phis_before_spill", node_stat.n_phis);
+ stat_ev_ctx_push_str("cls", pse->cls->name);
stat_ev_do(node_stats(birg, pse->cls, &node_stat));
+ stat_ev_do(pse->pre_spill_cost = be_estimate_irg_costs(irg, main_env->arch_env, birg->exec_freq));
+ stat_ev_dbl("phis_before_spill", node_stat.n_phis);
/* put all ignore registers into the ignore register set. */
be_put_ignore_regs(birg, pse->cls, chordal_env->ignore_colors);
be_pre_spill_prepare_constr(chordal_env);
dump(BE_CH_DUMP_CONSTR, birg->irg, pse->cls, "-constr-pre", dump_ir_block_graph_sched);
- stat_ev_ctx_pop();
+ stat_ev_ctx_pop("cls");
}
/**
/* some special classes contain only ignore regs, no work to be done */
if (allocatable_regs > 0) {
- stat_ev_ctx_push("cls", pse->cls->name);
+ stat_ev_ctx_push_str("cls", pse->cls->name);
stat_ev_do(node_stats(birg, pse->cls, &node_stat));
- stat_ev_dbl("spillcosts", be_estimate_irg_costs(irg, main_env->arch_env, birg->exec_freq) - pse->pre_spill_cost);
stat_ev_dbl("phis_after_spill", node_stat.n_phis);
stat_ev_dbl("mem_phis", node_stat.n_mem_phis);
stat_ev_dbl("reloads", node_stat.n_reloads);
stat_ev_dbl("spills", node_stat.n_spills);
+ stat_ev_dbl("spillcosts", be_estimate_irg_costs(irg, main_env->arch_env, birg->exec_freq) - pse->pre_spill_cost);
/*
If we have a backend provided spiller, post spill is
BE_TIMER_PUSH(ra_timer.t_ssa);
/* ssa destruction */
+ stat_ev_ctx_push_str("berachordal_phase", "ssadestr");
be_ssa_destruction(chordal_env);
+ stat_ev_ctx_pop("berachordal_phase");
BE_TIMER_POP(ra_timer.t_ssa);
stat_ev_do(node_stats(birg, pse->cls, &node_stat));
stat_ev_dbl("perms_after_coal", node_stat.n_perms);
stat_ev_dbl("copies_after_coal", node_stat.n_copies);
- stat_ev_ctx_pop();
+ stat_ev_ctx_pop("cls");
/* the ifg exists only if there are allocatable regs */
be_ifg_free(chordal_env->ifg);
be_stat_ev("insns_before", count_insns(irg));
+
+
if (! arch_code_generator_has_spiller(birg->cg)) {
/* use one of the generic spiller */
/* Perform the following for each register class. */
for (j = 0, m = arch_isa_get_n_reg_class(isa); j < m; ++j) {
post_spill_env_t pse;
+ const arch_register_class_t *cls
+ = arch_isa_get_reg_class(isa, j);
+
+ if(arch_register_class_flags(cls) & arch_register_class_flag_manual_ra)
+ continue;
+
memcpy(&pse.cenv, &chordal_env, sizeof(chordal_env));
pse.birg = birg;
- pre_spill(isa, j, &pse);
+ pre_spill(&pse, cls);
+
+#if 0
+ /* this is a hack, TODO remove me later */
+ if(j == 2) {
+ be_do_stat_reg_pressure(birg);
+ }
+#endif
BE_TIMER_PUSH(ra_timer.t_spill);
- be_do_spill(birg, pse.cls);
+ be_do_spill(birg, cls);
BE_TIMER_POP(ra_timer.t_spill);
- dump(BE_CH_DUMP_SPILL, irg, pse.cls, "-spill", dump_ir_block_graph_sched);
+ dump(BE_CH_DUMP_SPILL, irg, pse.cls, "-spill",
+ dump_ir_block_graph_sched);
post_spill(&pse, 0);
}
for (j = 0; j < m; ++j) {
memcpy(&pse[j].cenv, &chordal_env, sizeof(chordal_env));
pse[j].birg = birg;
- pre_spill(isa, j, &pse[j]);
+ pre_spill(&pse[j], pse[j].cls);
}
BE_TIMER_PUSH(ra_timer.t_spill);
}
}
+
be_verify_register_allocation(birg);
BE_TIMER_PUSH(ra_timer.t_epilog);