DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-#define NO_COLOR (-1)
-
#define DUMP_INTERVALS
-typedef struct _be_chordal_alloc_env_t {
+typedef struct be_chordal_alloc_env_t {
be_chordal_env_t *chordal_env;
pset *pre_colored; /**< Set of precolored nodes. */
- bitset_t *live; /**< A liveness bitset. */
+ bitset_t *live; /**< A liveness bitset. */
bitset_t *tmp_colors; /**< An auxiliary bitset which is as long as the number of colors in the class. */
- bitset_t *colors; /**< The color mask. */
+ bitset_t *colors; /**< The color mask. */
bitset_t *in_colors; /**< Colors used by live in values. */
int colors_n; /**< The number of colors. */
} be_chordal_alloc_env_t;
{
bitset_t *tmp = alloc_env->tmp_colors;
bitset_copy(tmp, colors);
- bitset_or(tmp, alloc_env->chordal_env->ignore_colors);
- return bitset_next_clear(tmp, 0);
+ bitset_flip_all(tmp);
+ bitset_and(tmp, alloc_env->chordal_env->allocatable_regs);
+ return bitset_next_set(tmp, 0);
}
static bitset_t *get_decisive_partner_regs(bitset_t *bs, const be_operand_t *o1, const be_operand_t *o2)
}
static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env,
- ir_node *irn, int *silent)
+ ir_node *irn)
{
int n_regs;
bitset_t *bs;
int *assignment;
pmap *partners;
int i, n_alloc;
- unsigned col;
+ size_t col;
const ir_edge_t *edge;
ir_node *perm = NULL;
//int match_res, cost;
void *base = obstack_base(env->obst);
be_insn_t *insn = chordal_scan_insn(env, irn);
ir_node *res = insn->next_insn;
- int be_silent = *silent;
bipartite_t *bp;
if (insn->pre_colored) {
pset_insert_ptr(alloc_env->pre_colored, insn->ops[i].carrier);
}
- /*
- * If the current node is a barrier toggle the silent flag.
- * If we are in the start block, we are ought to be silent at the beginning,
- * so the toggling activates the constraint handling but skips the barrier.
- * If we are in the end block we handle the in requirements of the barrier
- * and set the rest to silent.
- */
- if (be_is_Barrier(irn))
- *silent = !*silent;
-
- if (be_silent)
- goto end;
-
/*
* Perms inserted before the constraint handling phase are considered to be
* correctly precolored. These Perms arise during the ABI handling phase.
alloc_nodes[n_alloc] = proj;
pmap_insert(partners, proj, NULL);
- bitset_clear_all(bs);
- arch_put_non_ignore_regs(env->cls, bs);
- bitset_andnot(bs, env->ignore_colors);
- bitset_foreach(bs, col) {
+ bitset_foreach(env->allocatable_regs, col) {
//hungarian_add(bp, n_alloc, col, 1);
bipartite_add(bp, n_alloc, col);
}
assert(assignment[i] >= 0 && "there must have been a register assigned (node not register pressure faithful?)");
reg = arch_register_for_index(env->cls, assignment[i]);
- assert(! (reg->type & arch_register_type_ignore));
irn = alloc_nodes[i];
if (irn != NULL) {
DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", irn, reg->name));
}
- irn = pmap_get(partners, alloc_nodes[i]);
+ irn = (ir_node*)pmap_get(partners, alloc_nodes[i]);
if (irn != NULL) {
arch_set_irn_register(irn, reg);
(void) pset_hinsert_ptr(alloc_env->pre_colored, irn);
*/
static void constraints(ir_node *bl, void *data)
{
- /*
- * Start silent in the start block.
- * The silence remains until the first barrier is seen.
- * Each other block is begun loud.
- */
- int silent = bl == get_irg_start_block(get_irn_irg(bl));
- be_chordal_alloc_env_t *env = data;
+ be_chordal_alloc_env_t *env = (be_chordal_alloc_env_t*)data;
ir_node *irn;
- /*
- * If the block is the start block search the barrier and
- * start handling constraints from there.
- */
for (irn = sched_first(bl); !sched_is_end(irn);) {
- irn = handle_constraints(env, irn, &silent);
+ irn = handle_constraints(env, irn);
}
}
static void assign(ir_node *block, void *env_ptr)
{
- be_chordal_alloc_env_t *alloc_env = env_ptr;
+ be_chordal_alloc_env_t *alloc_env = (be_chordal_alloc_env_t*)env_ptr;
be_chordal_env_t *env = alloc_env->chordal_env;
bitset_t *live = alloc_env->live;
bitset_t *colors = alloc_env->colors;
*/
if (b->is_def && !be_is_live_in(lv, block, irn)) {
const arch_register_t *reg;
- int col = NO_COLOR;
+ int col;
if (ignore || pset_find_ptr(alloc_env->pre_colored, irn)) {
reg = arch_get_irn_register(irn);
col = get_next_free_reg(alloc_env, colors);
reg = arch_register_for_index(env->cls, col);
assert(arch_get_irn_register(irn) == NULL && "This node must not have been assigned a register yet");
- assert(!arch_register_type_is(reg, ignore) && "Must not assign ignore register");
}
bitset_set(colors, col);
assert(reg && "Register must have been assigned");
col = arch_register_get_index(reg);
-#ifndef NDEBUG
- if (!arch_register_type_is(reg, ignore)) {
- assert(bitset_is_set(live, nr) && "Cannot have a non live use");
- }
-#endif
bitset_clear(colors, col);
bitset_clear(live, nr);
del_pset(env.pre_colored);
}
-BE_REGISTER_MODULE_CONSTRUCTOR(be_init_chordal);
+BE_REGISTER_MODULE_CONSTRUCTOR(be_init_chordal)
void be_init_chordal(void)
{
static be_ra_chordal_coloring_t coloring = {