pset *pre_colored; /**< Set of precolored nodes. */
bitset_t *live; /**< A liveness bitset. */
bitset_t *colors; /**< The color mask. */
- bitset_t *ignore_colors; /**< A mask of colors which shall be not used in allocation (ignored). */
bitset_t *in_colors; /**< Colors used by live in values. */
int colors_n; /**< The number of colors. */
} be_chordal_alloc_env_t;
*/
static INLINE int has_reg_class(const be_chordal_env_t *env, const ir_node *irn)
{
- return arch_irn_has_reg_class(env->main_env->arch_env, irn, -1, env->cls);
+ // return arch_irn_has_reg_class(env->main_env->arch_env, irn, -1, env->cls);
+ return arch_irn_consider_in_reg_alloc(env->birg->main_env->arch_env, env->cls, irn);
}
#define has_limited_constr(req, irn) \
static insn_t *scan_insn(be_chordal_env_t *env, ir_node *irn, struct obstack *obst)
{
- const arch_env_t *arch_env = env->main_env->arch_env;
+ const arch_env_t *arch_env = env->birg->main_env->arch_env;
operand_t o;
insn_t *insn;
int i, n;
int has_constraint = arch_register_req_is(&op->req, limited);
if(!values_interfere(op->carrier, op->irn) && !op->partner && (!has_constraint || can_be_constrained)) {
- if(arch_register_req_is(&op->req, should_be_same) && op->req.other == op->carrier)
+ if(arch_register_req_is(&op->req, should_be_same) && op->req.other_same == op->carrier)
return op;
else
res = op;
if(insn->has_constraints) {
firm_dbg_module_t *dbg = firm_dbg_register("firm.be.chordal.constr");
- const arch_env_t *aenv = env->main_env->arch_env;
+ const arch_env_t *aenv = env->birg->main_env->arch_env;
int n_regs = env->cls->n_regs;
bitset_t *bs = bitset_alloca(n_regs);
+ bitset_t *non_ignore = bitset_alloca(n_regs);
ir_node **alloc_nodes = alloca(n_regs * sizeof(alloc_nodes[0]));
bipartite_t *bp = bipartite_new(n_regs, n_regs);
int *assignment = alloca(n_regs * sizeof(assignment[0]));
const ir_edge_t *edge;
ir_node *perm = insert_Perm_after(aenv, env->cls, env->dom_front, sched_prev(irn));
+ arch_put_non_ignore_regs(aenv, env->cls, non_ignore);
+
/* Registers are propagated by insert_Perm_after(). Clean them here! */
if(perm) {
foreach_out_edge(perm, edge) {
/*
* If there was no Perm made, nothing was alive in this register class.
* This means, that the node has no operands, thus no input constraints.
- * so it had output constraints. The other results then can be assigned freeliy.
+ * so it had output constraints. The other results then can be assigned freely.
*/
pair_up_operands(insn);
for(i = 0, n_alloc = 0; i < insn->n_ops; ++i) {
operand_t *op = &insn->ops[i];
- if(arch_register_req_is(&op->req, limited)) {
+ if(arch_register_req_is(&op->req, limited) && arch_irn_consider_in_reg_alloc(aenv, env->cls, op->carrier)) {
+ const arch_register_t *reg = arch_get_irn_register(aenv, op->carrier);
+
pmap_insert(partners, op->carrier, op->partner ? op->partner->carrier : NULL);
alloc_nodes[n_alloc] = op->carrier;
bitset_clear_all(bs);
op->req.limited(op->req.limited_env, bs);
- bitset_andnot(bs, alloc_env->ignore_colors);
+ assert((!reg || bitset_is_set(bs, reg->index)) && "color of pre-colored node is not in its allowed colors");
+ bitset_and(bs, non_ignore);
+
+ /* if the node is pre-colored, explicitly allow the color with which it is pre-colored. */
+ if(reg) {
+ bitset_set(bs, reg->index);
+ }
+
+ DBG((dbg, LEVEL_2, "\tallowed registers for %+F: %B\n", op->carrier, bs));
bitset_foreach(bs, col)
bipartite_add(bp, n_alloc, col);
}
if(perm) {
+ /* Make the input constraints of the node to output constraints of the Perm's Projs */
+ for(i = insn->use_start; i < insn->n_ops; ++i) {
+ operand_t *op = &insn->ops[i];
+
+ /*
+ If the operand is an "in" operand, constrained and the carrier is a Proj to the Perm,
+ then copy the in constraint to the Perm's out constraint
+ */
+ if(arch_register_req_is(&op->req, limited) && is_Proj(op->carrier) && perm == get_Proj_pred(op->carrier))
+ be_set_constr_limited(perm, BE_OUT_POS(get_Proj_proj(op->carrier)), &op->req);
+ }
+
foreach_out_edge(perm, edge) {
ir_node *proj = get_edge_src_irn(edge);
bitset_clear_all(bs);
arch_get_allocatable_regs(aenv, proj, -1, bs);
- bitset_andnot(bs, alloc_env->ignore_colors);
+ bitset_and(bs, non_ignore);
bitset_foreach(bs, col)
bipartite_add(bp, n_alloc, col);
bipartite_matching(bp, assignment);
+ /* Assign colors obtained from the matching. */
for(i = 0; i < n_alloc; ++i) {
int j;
ir_node *nodes[2];
- const arch_register_t *reg = arch_register_for_index(env->cls, assignment[i]);
+ const arch_register_t *reg;
+
+ assert(assignment[i] >= 0 && "there must have been a register assigned");
+ reg = arch_register_for_index(env->cls, assignment[i]);
nodes[0] = alloc_nodes[i];
nodes[1] = pmap_get(partners, alloc_nodes[i]);
}
+ /* Allocate the non-constrained Projs of the Perm. */
if(perm) {
bitset_clear_all(bs);
+
+ /* Put the colors of all Projs in a bitset. */
foreach_out_edge(perm, edge) {
ir_node *proj = get_edge_src_irn(edge);
const arch_register_t *reg = arch_get_irn_register(aenv, proj);
bitset_set(bs, reg->index);
}
- // bitset_or(bs, alloc_env->ignore_colors);
+ /* Assign the not yet assigned Projs of the Perm a suitable color. */
foreach_out_edge(perm, edge) {
ir_node *proj = get_edge_src_irn(edge);
const arch_register_t *reg = arch_get_irn_register(aenv, proj);
{
firm_dbg_module_t *dbg = firm_dbg_register("firm.be.chordal.constr");
be_chordal_alloc_env_t *env = data;
- arch_env_t *arch_env = env->chordal_env->main_env->arch_env;
+ arch_env_t *arch_env = env->chordal_env->birg->main_env->arch_env;
ir_node *irn;
for(irn = sched_first(bl); !sched_is_end(irn);) {
be_chordal_alloc_env_t *alloc_env = env_ptr;
be_chordal_env_t *env = alloc_env->chordal_env;
+ const arch_env_t *arch_env = env->birg->main_env->arch_env;
bitset_t *live = alloc_env->live;
firm_dbg_module_t *dbg = env->dbg;
ir_node *irn;
bitset_t *live = alloc_env->live;
bitset_t *colors = alloc_env->colors;
bitset_t *in_colors = alloc_env->in_colors;
- const arch_env_t *arch_env = env->main_env->arch_env;
+ const arch_env_t *arch_env = env->birg->main_env->arch_env;
const ir_node *irn;
border_t *b;
struct list_head *head = get_block_border_head(env, block);
pset *live_in = put_live_in(block, pset_new_ptr_default());
- bitset_clear_all(live);
bitset_clear_all(colors);
+ bitset_clear_all(live);
bitset_clear_all(in_colors);
DBG((dbg, LEVEL_4, "Assigning colors for block %+F\n", block));
}
/*
- * Mind that the sequence of defs from back to front defines a perfect
+ * Mind that the sequence
+ * of defs from back to front defines a perfect
* elimination order. So, coloring the definitions from first to last
* will work.
*/
del_pset(live_in);
}
-
-
void be_ra_chordal_color(be_chordal_env_t *chordal_env)
{
- int i;
+ be_chordal_alloc_env_t env;
+ char buf[256];
+
int colors_n = arch_register_class_n_regs(chordal_env->cls);
ir_graph *irg = chordal_env->irg;
- be_chordal_alloc_env_t env;
if(get_irg_dom_state(irg) != dom_consistent)
compute_doms(irg);
env.chordal_env = chordal_env;
env.colors_n = colors_n;
env.colors = bitset_malloc(colors_n);
- env.ignore_colors = bitset_malloc(colors_n);
env.in_colors = bitset_malloc(colors_n);
env.pre_colored = pset_new_ptr_default();
- bitset_clear_all(env.ignore_colors);
-#if 0
- for(i = 0; i < chordal_env->cls->n_regs; ++i) {
- const arch_register_t *reg = &chordal_env->cls->regs[i];
- if(arch_register_type_is(reg, ignore))
- bitset_set(env.ignore_colors, reg->index);
- }
-#endif
-
/* Handle register targeting constraints */
dom_tree_walk_irg(irg, constraints, NULL, &env);
- {
- char buf[128];
+ if(chordal_env->opts->dump_flags & BE_CH_DUMP_CONSTR) {
snprintf(buf, sizeof(buf), "-%s-constr", chordal_env->cls->name);
dump_ir_block_graph_sched(chordal_env->irg, buf);
}
be_numbering_done(irg);
-#ifdef DUMP_INTERVALS
- {
- char buf[128];
+ if(chordal_env->opts->dump_flags & BE_CH_DUMP_TREE_INTV) {
plotter_t *plotter;
-
ir_snprintf(buf, sizeof(buf), "ifg_%s_%F.eps", chordal_env->cls->name, irg);
plotter = new_plotter_ps(buf);
-
draw_interval_tree(&draw_chordal_def_opts, chordal_env, plotter);
plotter_free(plotter);
}
-#endif
free(env.live);
free(env.colors);
free(env.in_colors);
- free(env.ignore_colors);
-
del_pset(env.pre_colored);
}