/*
- * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
*
* This file is part of libFirm.
*
* @date 08.12.2004
* @version $Id$
*/
-#ifdef HAVE_CONFIG_H
#include "config.h"
-#endif
#include <ctype.h>
#include "irtools.h"
#include "irbitset.h"
#include "debug.h"
-#include "xmalloc.h"
#include "iredges.h"
#include "beutil.h"
#define DUMP_INTERVALS
-/* new style assign routine without borders. */
-#undef NEW_STYLE_ASSIGN
-
typedef struct _be_chordal_alloc_env_t {
be_chordal_env_t *chordal_env;
- pset *pre_colored; /**< Set of precolored nodes. */
- bitset_t *live; /**< A liveness bitset. */
- bitset_t *tmp_colors; /**< An auxiliary bitset which is as long as the number of colors in the class. */
- bitset_t *colors; /**< The color mask. */
- bitset_t *in_colors; /**< Colors used by live in values. */
- int colors_n; /**< The number of colors. */
+ pset *pre_colored; /**< Set of precolored nodes. */
+ bitset_t *live; /**< A liveness bitset. */
+ bitset_t *tmp_colors; /**< An auxiliary bitset which is as long as the number of colors in the class. */
+ bitset_t *colors; /**< The color mask. */
+ bitset_t *in_colors; /**< Colors used by live in values. */
+ int colors_n; /**< The number of colors. */
} be_chordal_alloc_env_t;
#include "fourcc.h"
* @param is_def Is the border a use or a def.
* @return The created border.
*/
-static INLINE border_t *border_add(be_chordal_env_t *env, struct list_head *head,
+static inline border_t *border_add(be_chordal_env_t *env, struct list_head *head,
ir_node *irn, unsigned step, unsigned pressure,
unsigned is_def, unsigned is_real)
{
else {
b = get_irn_link(irn);
- assert(b && b->magic == BORDER_FOURCC && "Illegal border encountered");
+ DEBUG_ONLY(assert(b && b->magic == BORDER_FOURCC && "Illegal border encountered"));
}
b->pressure = pressure;
* @param irn The node.
* @return 1, if the node is of that register class, 0 if not.
*/
-static INLINE int has_reg_class(const be_chordal_env_t *env, const ir_node *irn)
+static inline int has_reg_class(const be_chordal_env_t *env, const ir_node *irn)
{
- return arch_irn_consider_in_reg_alloc(env->birg->main_env->arch_env, env->cls, irn);
+ return arch_irn_consider_in_reg_alloc(env->cls, irn);
}
-#define has_limited_constr(req, irn) \
- (arch_get_register_req(arch_env, (req), irn, -1) && (req)->type == arch_register_req_type_limited)
-
static int get_next_free_reg(const be_chordal_alloc_env_t *alloc_env, bitset_t *colors)
{
bitset_t *tmp = alloc_env->tmp_colors;
be_insn_env_t ie;
ie.ignore_colors = env->ignore_colors;
- ie.aenv = env->birg->main_env->arch_env;
ie.obst = env->obst;
ie.cls = env->cls;
return be_scan_insn(&ie, irn);
static ir_node *prepare_constr_insn(be_chordal_env_t *env, ir_node *irn)
{
- const be_irg_t *birg = env->birg;
- const arch_env_t *aenv = birg->main_env->arch_env;
bitset_t *tmp = bitset_alloca(env->cls->n_regs);
bitset_t *def_constr = bitset_alloca(env->cls->n_regs);
ir_node *bl = get_nodes_block(irn);
- be_lv_t *lv = env->birg->lv;
+ const be_irg_t *birg = env->birg;
+ be_lv_t *lv = birg->lv;
be_insn_t *insn;
int i, j;
const arch_register_t *reg;
const arch_register_req_t *req;
- if (arch_get_irn_reg_class(aenv, irn, i) != env->cls)
+ req = arch_get_register_req(irn, i);
+ if (req->cls != env->cls)
continue;
- reg = arch_get_irn_register(aenv, op);
+ reg = arch_get_irn_register(op);
if (reg == NULL || !arch_register_type_is(reg, ignore))
continue;
if(arch_register_type_is(reg, joker))
continue;
- req = arch_get_register_req(aenv, irn, i);
if (!arch_register_req_is(req, limited))
continue;
if(a_op->carrier != op->carrier || !a_op->has_constraints)
continue;
+ /* if the constraint is the same, no copy is necessary
+ * TODO generalise unequal but overlapping constraints */
+ if (a_op->req == op->req)
+ continue;
+
if (be_is_Copy(get_irn_n(insn->irn, a_op->pos)))
continue;
}
}
- /* collect all registers occuring in out constraints. */
+ /* collect all registers occurring in out constraints. */
for(i = 0; i < insn->use_start; ++i) {
be_operand_t *op = &insn->ops[i];
if(op->has_constraints)
Check, if
1) the operand is constrained.
2) lives through the node.
- 3) is constrained to a register occuring in out constraints.
+ 3) is constrained to a register occurring in out constraints.
*/
if(!op->has_constraints ||
!values_interfere(birg, insn->irn, op->carrier) ||
static void pair_up_operands(const be_chordal_alloc_env_t *alloc_env, be_insn_t *insn)
{
const be_chordal_env_t *env = alloc_env->chordal_env;
-
- int n_uses = be_insn_n_uses(insn);
- int n_defs = be_insn_n_defs(insn);
- bitset_t *bs = bitset_alloca(env->cls->n_regs);
- int *pairing = alloca(MAX(n_defs, n_uses) * sizeof(pairing[0]));
-
- int i, j;
+ bitset_t *bs = bitset_alloca(env->cls->n_regs);
+ int i;
+ int j;
/*
For each out operand, try to find an in operand which can be assigned the
if (smallest >= 0) {
be_operand_t *partner = &insn->ops[smallest];
-
for(i = insn->use_start; i < insn->n_ops; ++i) {
if(insn->ops[i].carrier == partner->carrier)
insn->ops[i].partner = out_op;
be_insn_t **the_insn)
{
be_chordal_env_t *env = alloc_env->chordal_env;
- const arch_env_t *aenv = env->birg->main_env->arch_env;
be_insn_t *insn = *the_insn;
ir_node *perm = NULL;
bitset_t *out_constr = bitset_alloca(env->cls->n_regs);
be_stat_ev("constr_perm", get_irn_arity(perm));
foreach_out_edge(perm, edge) {
ir_node *proj = get_edge_src_irn(edge);
- arch_set_irn_register(aenv, proj, NULL);
+ arch_set_irn_register(proj, NULL);
}
/*
the Perm. Recomputing liveness is also a good idea if a Perm is inserted, since
the live sets may change.
*/
- // be_liveness_recompute(lv);
obstack_free(env->obst, insn);
*the_insn = insn = chordal_scan_insn(env, insn->irn);
static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env,
ir_node *irn, int *silent)
{
- const arch_env_t *aenv;
int n_regs;
bitset_t *bs;
ir_node **alloc_nodes;
bitset_pos_t col;
const ir_edge_t *edge;
ir_node *perm = NULL;
- int match_res, cost;
+ //int match_res, cost;
be_chordal_env_t *env = alloc_env->chordal_env;
void *base = obstack_base(env->obst);
be_insn_t *insn = chordal_scan_insn(env, irn);
if(!insn->has_constraints)
goto end;
- aenv = env->birg->main_env->arch_env;
n_regs = env->cls->n_regs;
bs = bitset_alloca(n_regs);
- alloc_nodes = alloca(n_regs * sizeof(alloc_nodes[0]));
+ alloc_nodes = ALLOCAN(ir_node*, n_regs);
//bp = hungarian_new(n_regs, n_regs, 2, HUNGARIAN_MATCH_PERFECT);
bp = bipartite_new(n_regs, n_regs);
- assignment = alloca(n_regs * sizeof(assignment[0]));
+ assignment = ALLOCAN(int, n_regs);
partners = pmap_create();
/*
pmap_insert(partners, proj, NULL);
bitset_clear_all(bs);
- arch_put_non_ignore_regs(aenv, env->cls, bs);
+ arch_put_non_ignore_regs(env->cls, bs);
bitset_andnot(bs, env->ignore_colors);
bitset_foreach(bs, col) {
//hungarian_add(bp, n_alloc, col, 1);
irn = alloc_nodes[i];
if (irn != NULL) {
- arch_set_irn_register(aenv, irn, reg);
+ arch_set_irn_register(irn, reg);
(void) pset_hinsert_ptr(alloc_env->pre_colored, irn);
DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", irn, reg->name));
}
irn = pmap_get(partners, alloc_nodes[i]);
if (irn != NULL) {
- arch_set_irn_register(aenv, irn, reg);
+ arch_set_irn_register(irn, reg);
(void) pset_hinsert_ptr(alloc_env->pre_colored, irn);
DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", irn, reg->name));
}
/* Put the colors of all Projs in a bitset. */
foreach_out_edge(perm, edge) {
ir_node *proj = get_edge_src_irn(edge);
- const arch_register_t *reg = arch_get_irn_register(aenv, proj);
+ const arch_register_t *reg = arch_get_irn_register(proj);
if(reg != NULL)
bitset_set(bs, reg->index);
/* Assign the not yet assigned Projs of the Perm a suitable color. */
foreach_out_edge(perm, edge) {
ir_node *proj = get_edge_src_irn(edge);
- const arch_register_t *reg = arch_get_irn_register(aenv, proj);
+ const arch_register_t *reg = arch_get_irn_register(proj);
DBG((dbg, LEVEL_2, "\tchecking reg of %+F: %s\n", proj, reg ? reg->name : "<none>"));
col = get_next_free_reg(alloc_env, bs);
reg = arch_register_for_index(env->cls, col);
bitset_set(bs, reg->index);
- arch_set_irn_register(aenv, proj, reg);
+ arch_set_irn_register(proj, reg);
pset_insert_ptr(alloc_env->pre_colored, proj);
DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", proj, reg->name));
}
bitset_t *live = alloc_env->live;
bitset_t *colors = alloc_env->colors;
bitset_t *in_colors = alloc_env->in_colors;
- const arch_env_t *arch_env = env->birg->main_env->arch_env;
struct list_head *head = get_block_border_head(env, block);
be_lv_t *lv = env->birg->lv;
- pset *live_in = be_lv_pset_put_in(lv, block, pset_new_ptr_default());
const ir_node *irn;
border_t *b;
+ int idx;
bitset_clear_all(colors);
bitset_clear_all(live);
* Since their colors have already been assigned (The dominators were
* allocated before), we have to mark their colors as used also.
*/
- foreach_pset(live_in, irn) {
+ be_lv_foreach(lv, block, be_lv_state_in, idx) {
+ irn = be_lv_get_irn(lv, block, idx);
if(has_reg_class(env, irn)) {
- const arch_register_t *reg = arch_get_irn_register(arch_env, irn);
+ const arch_register_t *reg = arch_get_irn_register(irn);
int col;
assert(reg && "Node must have been assigned a register");
list_for_each_entry_reverse(border_t, b, head, list) {
ir_node *irn = b->irn;
int nr = get_irn_idx(irn);
- int ignore = arch_irn_is(arch_env, irn, ignore);
+ int ignore = arch_irn_is_ignore(irn);
/*
* Assign a color, if it is a local def. Global defs already have a
int col = NO_COLOR;
if(ignore || pset_find_ptr(alloc_env->pre_colored, irn)) {
- reg = arch_get_irn_register(arch_env, irn);
+ reg = arch_get_irn_register(irn);
col = reg->index;
assert(!bitset_is_set(colors, col) && "pre-colored register must be free");
} else {
col = get_next_free_reg(alloc_env, colors);
reg = arch_register_for_index(env->cls, col);
- assert(arch_get_irn_register(arch_env, irn) == NULL && "This node must not have been assigned a register yet");
+ assert(arch_get_irn_register(irn) == NULL && "This node must not have been assigned a register yet");
assert(!arch_register_type_is(reg, ignore) && "Must not assign ignore register");
}
bitset_set(colors, col);
- arch_set_irn_register(arch_env, irn, reg);
+ arch_set_irn_register(irn, reg);
DBG((dbg, LEVEL_1, "\tassigning register %s(%d) to %+F\n", arch_register_get_name(reg), col, irn));
/* Clear the color upon a use. */
else if(!b->is_def) {
- const arch_register_t *reg = arch_get_irn_register(arch_env, irn);
+ const arch_register_t *reg = arch_get_irn_register(irn);
int col;
assert(reg && "Register must have been assigned");
bitset_clear(live, nr);
}
}
-
- del_pset(live_in);
-}
-
-/**
- * A new assign...
- */
-static void assign_new(ir_node *block, be_chordal_alloc_env_t *alloc_env, bitset_t *live_end_dom)
-{
- be_chordal_env_t *env = alloc_env->chordal_env;
- bitset_t *colors = alloc_env->colors;
- bitset_t *in_colors = alloc_env->in_colors;
- bitset_t *live = bitset_irg_malloc(env->irg);
- const arch_env_t *arch_env = env->birg->main_env->arch_env;
- be_irg_t *birg = env->birg;
-
- bitset_pos_t elm;
- ir_node *irn;
-
- bitset_clear_all(colors);
- bitset_clear_all(in_colors);
-
- /*
- * All variables which are live in to this block are live out
- * of the immediate dominator thanks to SSA properties. As we
- * have already visited the immediate dominator, we know these
- * variables. The only tjing left is to check wheather they are live
- * in here (they also could be phi arguments to some ohi not
- * in this block, hence we have to check).
- */
- bitset_foreach (live_end_dom, elm) {
- ir_node *irn = get_idx_irn(env->irg, elm);
- if (be_is_live_in(birg->lv, block, irn)) {
- const arch_register_t *reg = arch_get_irn_register(arch_env, irn);
- int col;
-
- assert(be_is_live_in(env->birg->lv, block, irn));
- assert(reg && "Node must have been assigned a register");
- col = arch_register_get_index(reg);
-
- DBG((dbg, LEVEL_4, "%+F has reg %s\n", irn, reg->name));
-
- /* Mark the color of the live in value as used. */
- bitset_set(colors, col);
- bitset_set(in_colors, col);
-
- /* Mark the value live in. */
- bitset_set(live, elm);
- }
-
- else {
- assert(!be_is_live_in(env->birg->lv, block, irn));
- }
- }
-
- /*
- * Mind that the sequence of defs from back to front defines a perfect
- * elimination order. So, coloring the definitions from first to last
- * will work.
- */
- sched_foreach (block, irn) {
- int nr = get_irn_idx(irn);
- int ignore = arch_irn_is(arch_env, irn, ignore);
-
- /* Clear the color upon a last use. */
- if(!is_Phi(irn)) {
- int i;
- for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
- ir_node *op = get_irn_n(irn, i);
-
- /*
- * If the reg class matches and the operand is not live after
- * the node, irn is a last use of op and the register can
- * be freed.
- */
- if (has_reg_class(env, op)) {
- if (!be_lv_chk_after_irn(birg, op, irn)) {
- const arch_register_t *reg = arch_get_irn_register(arch_env, op);
- int col;
-
- assert(reg && "Register must have been assigned");
- col = arch_register_get_index(reg);
- bitset_clear(colors, col);
- bitset_clear(live, nr);
- }
- }
- }
- }
-
- if (has_reg_class(env, irn)) {
- const arch_register_t *reg;
- int col = NO_COLOR;
-
- /*
- * Assign a color, if it is a local def. Global defs already have a
- * color.
- */
- if(ignore || pset_find_ptr(alloc_env->pre_colored, irn)) {
- reg = arch_get_irn_register(arch_env, irn);
- col = reg->index;
- assert(!bitset_is_set(colors, col) && "pre-colored register must be free");
- } else {
- col = get_next_free_reg(alloc_env, colors);
- reg = arch_register_for_index(env->cls, col);
- assert(arch_get_irn_register(arch_env, irn) == NULL && "This node must not have been assigned a register yet");
- assert(!arch_register_type_is(reg, ignore) && "Must not assign ignore register");
- }
-
- bitset_set(colors, col);
- arch_set_irn_register(arch_env, irn, reg);
-
- DBG((dbg, LEVEL_1, "\tassigning register %s(%d) to %+F\n", arch_register_get_name(reg), col, irn));
-
- assert(!bitset_is_set(live, nr) && "Value's definition must not have been encountered");
- bitset_set(live, nr);
- }
-
- }
-
- dominates_for_each (block, irn) {
- assign_new(irn, alloc_env, live);
- }
-
- bitset_free(live);
}
void be_ra_chordal_color(be_chordal_env_t *chordal_env)
int colors_n = arch_register_class_n_regs(cls);
ir_graph *irg = chordal_env->irg;
- int allocatable_regs = colors_n - be_put_ignore_regs(birg, cls, NULL);
- /* some special classes contain only ignore regs, no work to be done */
- if(allocatable_regs == 0)
- return;
-
- be_assure_dom_front(birg);
lv = be_assure_liveness(birg);
be_liveness_assure_sets(lv);
be_liveness_assure_chk(lv);
env.in_colors = bitset_alloca(colors_n);
env.pre_colored = pset_new_ptr_default();
+ BE_TIMER_PUSH(t_constr);
+
/* Handle register targeting constraints */
dom_tree_walk_irg(irg, constraints, NULL, &env);
be_dump(chordal_env->irg, buf, dump_ir_block_graph_sched);
}
+ BE_TIMER_POP(t_constr);
+
env.live = bitset_malloc(get_irg_last_idx(chordal_env->irg));
/* First, determine the pressure */
dom_tree_walk_irg(irg, pressure, NULL, &env);
/* Assign the colors */
-#ifdef NEW_STYLE_ASSIGN
- assign_new(get_irg_start_block(irg), &env, env.live);
-#else
dom_tree_walk_irg(irg, assign, NULL, &env);
-#endif
if(chordal_env->opts->dump_flags & BE_CH_DUMP_TREE_INTV) {
plotter_t *plotter;