-#ifndef _FIRM_BEARCH_H
-#define _FIRM_BEARCH_H
+/*
+ * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
+/**
+ * @file
+ * @brief Processor architecture specification.
+ * @author Sebastian Hack
+ */
+#ifndef FIRM_BE_BEARCH_H
+#define FIRM_BE_BEARCH_H
+#include <stdbool.h>
-#ifdef WITH_LIBCORE
-#include <libcore/lc_opts.h>
-#endif
+#include "firm_types.h"
+#include "raw_bitset.h"
-#include "type.h"
-
-#include "irnode.h"
-#include "irmode.h"
-
-#include "bitset.h"
-#include "hashptr.h"
-#include "fourcc.h"
-#include "set.h"
-#include "list.h"
-#include "ident.h"
-
-#include "belistsched.h"
-#include "beabi_t.h"
-#include "be_t.h"
-
-typedef struct _arch_register_class_t arch_register_class_t;
-typedef struct _arch_register_t arch_register_t;
-typedef struct _arch_isa_if_t arch_isa_if_t;
-typedef struct _arch_isa_t arch_isa_t;
-typedef struct _arch_env_t arch_env_t;
-typedef struct _arch_irn_ops_if_t arch_irn_ops_if_t;
-typedef struct _arch_irn_ops_t arch_irn_ops_t;
-typedef struct _arch_irn_handler_t arch_irn_handler_t;
-typedef struct _arch_code_generator_t arch_code_generator_t;
-typedef struct _arch_code_generator_if_t arch_code_generator_if_t;
-
-struct _be_node_factory_t;
-
-typedef enum _arch_register_type_t {
- arch_register_type_none = 0,
- arch_register_type_caller_save = 1, /**< The register must be saved by the caller
- upon a function call. It thus can be overwritten
- in the called function. */
- arch_register_type_callee_save = 2, /**< The register must be saved by the caller
- upon a function call. It thus can be overwritten
- in the called function. */
- arch_register_type_ignore = 4, /**< Do not consider this register when allocating. */
-} arch_register_type_t;
+#include "be_types.h"
+#include "beinfo.h"
+#include "be.h"
/**
- * Convenience macro to check for register type.
- * @param req A pointer to register.
- * @param kind The kind of type to check for (see arch_register_type_t).
- * @return 1, If register is of given kind, 0 if not.
+ * this constant is returned by the get_sp_bias functions if the stack
+ * is reset (usually because the frame pointer is copied to the stack
+ * pointer
*/
-#define arch_register_type_is(reg, kind) \
- (((reg)->type & arch_register_type_ ## kind) != 0)
+#define SP_BIAS_RESET INT_MIN
+
+typedef enum arch_register_class_flags_t {
+ arch_register_class_flag_none = 0,
+ /** don't do automatic register allocation for this class */
+ arch_register_class_flag_manual_ra = 1U << 0,
+ /** the register models an abstract state (example: fpu rounding mode) */
+ arch_register_class_flag_state = 1U << 1
+} arch_register_class_flags_t;
+ENUM_BITSET(arch_register_class_flags_t)
+
+typedef enum arch_register_type_t {
+ arch_register_type_none = 0,
+ /** Do not consider this register when allocating. */
+ arch_register_type_ignore = 1U << 0,
+ /** This is just a virtual register. Virtual registers fulfill any register
+ * constraints as long as the register class matches. It is a allowed to
+ * have multiple definitions for the same virtual register at a point */
+ arch_register_type_virtual = 1U << 1,
+ /** The register represents a state that should be handled by bestate
+ * code */
+ arch_register_type_state = 1U << 2,
+} arch_register_type_t;
+ENUM_BITSET(arch_register_type_t)
/**
- * A register.
+ * Different types of register allocation requirements.
*/
-struct _arch_register_t {
- const char *name; /**< The name of the register. */
- const arch_register_class_t *reg_class; /**< The class the register belongs to. */
- int index; /**< The index of the register in the class. */
- arch_register_type_t type; /**< The type of the register. */
- void *data; /**< Custom data. */
-};
+typedef enum arch_register_req_type_t {
+ /** No register requirement. */
+ arch_register_req_type_none = 0,
+ /** All registers in the class are allowed. */
+ arch_register_req_type_normal = 1U << 0,
+ /** Only a real subset of the class is allowed. */
+ arch_register_req_type_limited = 1U << 1,
+ /** The register should be equal to another one at the node. */
+ arch_register_req_type_should_be_same = 1U << 2,
+ /** The register must be unequal from some other at the node. */
+ arch_register_req_type_must_be_different = 1U << 3,
+ /** The registernumber should be aligned (in case of multiregister values)*/
+ arch_register_req_type_aligned = 1U << 4,
+ /** ignore while allocating registers */
+ arch_register_req_type_ignore = 1U << 5,
+ /** the output produces a new value for the stack pointer
+ * (this is not really a constraint but a marker to guide the stackpointer
+ * rewiring logic) */
+ arch_register_req_type_produces_sp = 1U << 6,
+} arch_register_req_type_t;
+ENUM_BITSET(arch_register_req_type_t)
-static INLINE const arch_register_class_t *
-_arch_register_get_class(const arch_register_t *reg)
-{
- return reg->reg_class;
-}
+extern arch_register_req_t const arch_no_requirement;
+#define arch_no_register_req (&arch_no_requirement)
-static INLINE int _arch_register_get_index(const arch_register_t *reg)
-{
- return reg->index;
-}
+void arch_dump_register_reqs(FILE *F, const ir_node *node);
+void arch_dump_reqs_and_registers(FILE *F, const ir_node *node);
-#define arch_register_get_class(reg) _arch_register_get_class(reg)
-#define arch_register_get_index(reg) _arch_register_get_index(reg)
-#define arch_register_get_name(reg) ((reg)->name)
+void arch_set_frame_offset(ir_node *irn, int bias);
+
+ir_entity *arch_get_frame_entity(const ir_node *irn);
+int arch_get_sp_bias(ir_node *irn);
+
+int arch_get_op_estimated_cost(const ir_node *irn);
+int arch_possible_memory_operand(const ir_node *irn,
+ unsigned int i);
+void arch_perform_memory_operand(ir_node *irn, ir_node *spill,
+ unsigned int i);
/**
- * A class of registers.
- * Like general purpose or floating point.
+ * Get the register allocated for a value.
*/
-struct _arch_register_class_t {
- const char *name; /**< The name of the register class. */
- int n_regs; /**< Number of registers in this class. */
- ir_mode *mode; /**< The mode of the register class. */
- const arch_register_t *regs; /**< The array of registers. */
-};
+const arch_register_t *arch_get_irn_register(const ir_node *irn);
-#define arch_register_class_n_regs(cls) ((cls)->n_regs)
+/**
+ * Assign register to a value
+ */
+void arch_set_irn_register(ir_node *irn, const arch_register_t *reg);
/**
- * Put all registers in a class into a bitset.
- * @param cls The class.
- * @param bs The bitset. May be NULL.
- * @return The number of registers in the class.
+ * Set the register for a certain output operand.
*/
-extern int arch_register_class_put(const arch_register_class_t *cls, bitset_t *bs);
+void arch_set_irn_register_out(ir_node *irn, unsigned pos, const arch_register_t *r);
+
+const arch_register_t *arch_get_irn_register_out(const ir_node *irn, unsigned pos);
+const arch_register_t *arch_get_irn_register_in(const ir_node *irn, int pos);
-static INLINE const arch_register_t *
-_arch_register_for_index(const arch_register_class_t *cls, int idx)
+/**
+ * Get register constraints for an operand at position @p
+ */
+static inline const arch_register_req_t *arch_get_irn_register_req_in(
+ const ir_node *node, int pos)
{
- assert(0 <= idx && idx < cls->n_regs);
- return &cls->regs[idx];
+ const backend_info_t *info = be_get_info(node);
+ return info->in_reqs[pos];
}
-#define arch_register_for_index(cls, idx) \
- _arch_register_for_index(cls, idx)
-
-typedef enum _arch_operand_type_t {
- arch_operand_type_invalid,
- arch_operand_type_memory,
- arch_operand_type_register,
- arch_operand_type_immediate,
- arch_operand_type_symconst,
- arch_operand_type_last
-} arch_operand_type_t;
-
/**
- * Different types of register allocation requirements.
+ * Get register constraint for a produced result (the @p pos result)
*/
-typedef enum _arch_register_req_type_t {
- arch_register_req_type_none = 0, /**< No register requirement. */
-
- arch_register_req_type_normal = 1, /**< All registers in the class
- are allowed. */
+static inline const arch_register_req_t *arch_get_irn_register_req_out(
+ const ir_node *node, unsigned pos)
+{
+ const backend_info_t *info = be_get_info(node);
+ return info->out_infos[pos].req;
+}
- arch_register_req_type_limited = 2, /**< Only a real subset of
- the class is allowed. */
+static inline void arch_set_irn_register_req_out(ir_node *node, unsigned pos,
+ const arch_register_req_t *req)
+{
+ backend_info_t *info = be_get_info(node);
+ assert(pos < (unsigned)ARR_LEN(info->out_infos));
+ info->out_infos[pos].req = req;
+}
- arch_register_req_type_should_be_same = 4, /**< The register should be equal
- another one at the node. */
+static inline void arch_set_irn_register_reqs_in(ir_node *node,
+ const arch_register_req_t **reqs)
+{
+ backend_info_t *info = be_get_info(node);
+ info->in_reqs = reqs;
+}
- arch_register_req_type_should_be_different = 8, /**< The register must be unequal
- to some other at the node. */
+static inline const arch_register_req_t **arch_get_irn_register_reqs_in(
+ const ir_node *node)
+{
+ backend_info_t *info = be_get_info(node);
+ return info->in_reqs;
+}
-} arch_register_req_type_t;
+static inline reg_out_info_t *get_out_info(const ir_node *node)
+{
+ size_t pos = 0;
+ const backend_info_t *info;
+ assert(get_irn_mode(node) != mode_T);
+ if (is_Proj(node)) {
+ pos = get_Proj_proj(node);
+ node = get_Proj_pred(node);
+ }
+
+ info = be_get_info(node);
+ assert(pos < ARR_LEN(info->out_infos));
+ return &info->out_infos[pos];
+}
-/**
- * Convenience macro to check for set constraints.
- * @param req A pointer to register requirements.
- * @param kind The kind of constraint to check for (see arch_register_req_type_t).
- * @return 1, If the kind of constraint is present, 0 if not.
- */
-#define arch_register_req_is(req, kind) \
- (((req)->type & (arch_register_req_type_ ## kind)) != 0)
+static inline const arch_register_req_t *arch_get_irn_register_req(const ir_node *node)
+{
+ reg_out_info_t *out = get_out_info(node);
+ return out->req;
+}
/**
- * Expresses requirements to register allocation for an operand.
+ * Get the flags of a node.
+ * @param irn The node.
+ * @return The flags.
*/
-typedef struct _arch_register_req_t {
- arch_register_req_type_t type; /**< The type of the constraint. */
- const arch_register_class_t *cls; /**< The register class this constraint belongs to. */
-
- void (*limited)(void *limited_env, bitset_t *bs);
- /**< In case of the 'limited'
- constraint, this function
- must put all allowable
- registers in the bitset and
- return the number of registers
- in the bitset. */
-
- void *limited_env; /**< This must passed to limited. */
+static inline arch_irn_flags_t arch_get_irn_flags(const ir_node *node)
+{
+ backend_info_t const *const info = be_get_info(node);
+ return info->flags;
+}
- ir_node *other_same; /**< The other which shall have the same reg
- as this one. (for case should_be_same). */
+void arch_set_irn_flags(ir_node *node, arch_irn_flags_t flags);
+void arch_add_irn_flags(ir_node *node, arch_irn_flags_t flags);
- ir_node *other_different; /**< The other node from which this one's register
- must be different (case must_be_different). */
-} arch_register_req_t;
+#define arch_irn_is(irn, flag) ((arch_get_irn_flags(irn) & arch_irn_flags_ ## flag) != 0)
-/**
- * Format a register requirements information into a string.
- * @param buf The string where to put it to.
- * @param len The size of @p buf.
- * @param req The requirements structure to format.
- * @return A pointer to buf.
- */
-extern char *arch_register_req_format(char *buf, size_t len, const arch_register_req_t *req);
+static inline unsigned arch_get_irn_n_outs(const ir_node *node)
+{
+ backend_info_t *info = be_get_info(node);
+ if (info->out_infos == NULL)
+ return 0;
+ return (unsigned)ARR_LEN(info->out_infos);
+}
/**
- * Certain node classes which are relevant for the register allocator.
+ * Start codegeneration
*/
-typedef enum _arch_irn_class_t {
- arch_irn_class_normal,
- arch_irn_class_spill,
- arch_irn_class_reload,
- arch_irn_class_copy,
- arch_irn_class_perm,
- arch_irn_class_branch,
- arch_irn_class_call
-} arch_irn_class_t;
+arch_env_t *arch_env_begin_codegeneration(const arch_isa_if_t *isa,
+ be_main_env_t *main_env);
/**
- * Some flags describing a node in more detail.
+ * Register an instruction set architecture
*/
-typedef enum _arch_irn_flags_t {
- arch_irn_flags_none = 0, /**< Node flags. */
- arch_irn_flags_dont_spill = 1, /**< This must not be spilled. */
- arch_irn_flags_rematerializable = 2, /**< This should be replicated instead of spilled/reloaded. */
- arch_irn_flags_ignore = 4, /**< Ignore node during register allocation. */
- arch_irn_flags_last = arch_irn_flags_ignore
-} arch_irn_flags_t;
+void be_register_isa_if(const char *name, const arch_isa_if_t *isa);
/**
- * Get the string representation of a flag.
- * This functions does not handle or'ed bitmasks of flags.
- * @param flag The flag.
- * @return The flag as a string.
+ * A register.
*/
-extern const char *arch_irn_flag_str(arch_irn_flags_t flag);
-
-struct _arch_irn_ops_if_t {
-
- /**
- * Get the register requirements for a given operand.
- * @param self The self pointer.
- * @param irn The node.
- * @param pos The operand's position
- * (-1 for the result of the node, 0..n for the input
- * operands).
- * @return The register requirements for the selected operand.
- * The pointer returned is never NULL.
- */
- const arch_register_req_t *(*get_irn_reg_req)(const void *self,
- arch_register_req_t *req, const ir_node *irn, int pos);
-
- /**
- * Set the register for an output operand.
- * @param irn The node.
- * @param reg The register allocated to that operand.
- * @note If the operand is not a register operand,
- * the call is ignored.
- */
- void (*set_irn_reg)(const void *self, ir_node *irn, const arch_register_t *reg);
-
- /**
- * Get the register allocated for an output operand.
- * @param irn The node.
- * @return The register allocated at that operand. NULL, if
- * the operand was no register operand or
- * @c arch_register_invalid, if no register has yet been
- * allocated for this node.
- */
- const arch_register_t *(*get_irn_reg)(const void *self, const ir_node *irn);
-
- /**
- * Classify the node.
- * @param irn The node.
- * @return A classification.
- */
- arch_irn_class_t (*classify)(const void *self, const ir_node *irn);
-
- /**
- * Get the flags of a node.
- * @param self The irn ops themselves.
- * @param irn The node.
- * @return A set of flags.
- */
- arch_irn_flags_t (*get_flags)(const void *self, const ir_node *irn);
-
- /**
- * Set a bias for the stack pointer.
- * If the node in question uses the stack pointer for indexing, it must
- * consider the value of <code>bias</code> additionally.
- * @param self The this pointer.
- * @param irn The node in question.
- * @param bias The bias.
- */
- void (*set_stack_bias)(const void *self, ir_node *irn, int bias);
+struct arch_register_t {
+ const char *name; /**< The name of the register. */
+ const arch_register_class_t *reg_class; /**< The class of the register */
+ unsigned short index; /**< The index of the register in
+ the class. */
+ unsigned short global_index; /**< The global index this
+ register in the architecture. */
+ arch_register_type_t type; /**< The type of the register. */
+ /** register constraint allowing just this register */
+ const arch_register_req_t *single_req;
+ /** register number in dwarf debugging format */
+ unsigned short dwarf_number;
};
/**
- * irn_ops base class.
+ * A class of registers.
+ * Like general purpose or floating point.
*/
-struct _arch_irn_ops_t {
- const arch_irn_ops_if_t *impl;
+struct arch_register_class_t {
+ unsigned index; /**< index of this register class */
+ const char *name; /**< The name of the register class.*/
+ unsigned n_regs; /**< Number of registers in this
+ class. */
+ ir_mode *mode; /**< The mode of the register class.*/
+ const arch_register_t *regs; /**< The array of registers. */
+ arch_register_class_flags_t flags; /**< register class flags. */
+ const arch_register_req_t *class_req;
};
-extern void
-arch_set_stack_bias(const arch_env_t *env, ir_node *irn, int bias);
-
-/**
- * Get the register requirements for a node.
- * @param env The architecture environment.
- * @param req A pointer to a requirements structure, where the data can
- * be put into.
- * @param irn The node.
- * @param pos The position of the operand you're interested in.
- * @return A pointer to the register requirements which may <b>not</b>
- * neccessarily be equal to @p req. If NULL is returned, the
- * operand was no register operand.
- */
-extern const arch_register_req_t *
-arch_get_register_req(const arch_env_t *env, arch_register_req_t *req,
- const ir_node *irn, int pos);
+/** return the number of registers in this register class */
+#define arch_register_class_n_regs(cls) ((cls)->n_regs)
-/**
- * Check if an operand is a register operand.
- * @param env The environment.
- * @param irn The node.
- * @param pos The position of the operand.
- * @return 1, if the operand is significant for register allocation, 0
- * if not.
- */
-extern int arch_is_register_operand(const arch_env_t *env,
- const ir_node *irn, int pos);
+/** return the largest mode of this register class */
+#define arch_register_class_mode(cls) ((cls)->mode)
-/**
- * Get the number of allocatable registers concerning
- * a register class for an operand of a node.
- * @param env The environment.
- * @param irn The node.
- * @param pos The postition of the node's operand.
- * @param bs The bitset all allocatable registers shall be put into.
- * Note, that you can also pass NULL here. If you don't,
- * make sure, the bitset is as large as the register class
- * has registers.
- * @return The amount of registers allocatable for that operand.
- */
-extern int arch_get_allocatable_regs(const arch_env_t *env, const ir_node *irn, int pos, bitset_t *bs);
+/** return the name of this register class */
+#define arch_register_class_name(cls) ((cls)->name)
-/**
- * Put all registers which shall not be ignored by the register
- * allocator in a bit set.
- * @param env The arch env.
- * @param cls The register class to consider.
- * @param bs The bit set to put the registers to.
- */
-extern void arch_put_non_ignore_regs(const arch_env_t *env, const arch_register_class_t *cls, bitset_t *bs);
+/** return the index of this register class */
+#define arch_register_class_index(cls) ((cls)->index)
-/**
- * Check, if a register is assignable to an operand of a node.
- * @param env The architecture environment.
- * @param irn The node.
- * @param pos The position of the operand.
- * @param reg The register.
- * @return 1, if the register might be allocated to the operand 0 if not.
- */
-extern int arch_reg_is_allocatable(const arch_env_t *env,
- const ir_node *irn, int pos, const arch_register_t *reg);
+/** return the register class flags */
+#define arch_register_class_flags(cls) ((cls)->flags)
-/**
- * Get the register class of an operand of a node.
- * @param env The architecture environment.
- * @param irn The node.
- * @param pos The position of the operand.
- * @return The register class of the operand or NULL, if
- * operand is a non-register operand.
- */
-extern const arch_register_class_t *
-arch_get_irn_reg_class(const arch_env_t *env, const ir_node *irn, int pos);
+static inline const arch_register_t *arch_register_for_index(
+ const arch_register_class_t *cls, unsigned idx)
+{
+ assert(idx < cls->n_regs);
+ return &cls->regs[idx];
+}
/**
- * Get the register allocated at a certain output operand of a node.
- * @param env The arch environment.
- * @param irn The node.
- * @return The register allocated for this operand
+ * Convenience macro to check for set constraints.
+ * @param req A pointer to register requirements.
+ * @param kind The kind of constraint to check for
+ * (see arch_register_req_type_t).
+ * @return 1, If the kind of constraint is present, 0 if not.
*/
-extern const arch_register_t *
-arch_get_irn_register(const arch_env_t *env, const ir_node *irn);
+#define arch_register_req_is(req, kind) \
+ (((req)->type & (arch_register_req_type_ ## kind)) != 0)
/**
- * Set the register for a certain output operand.
- * @param env The architecture environment.
- * @param irn The node.
- * @param idx The index of the output operand.
- * @param reg The register.
+ * Expresses requirements to register allocation for an operand.
*/
-extern void arch_set_irn_register(const arch_env_t *env, ir_node *irn,
- const arch_register_t *reg);
+struct arch_register_req_t {
+ arch_register_req_type_t type; /**< The type of the constraint. */
+ const arch_register_class_t *cls; /**< The register class this constraint
+ belongs to. */
+ const unsigned *limited; /**< allowed register bitset
+ (in case of wide-values this is
+ only about the first register) */
+ unsigned other_same; /**< Bitmask of ins which should use the
+ same register (should_be_same). */
+ unsigned other_different; /**< Bitmask of ins which shall use a
+ different register
+ (must_be_different) */
+ unsigned char width; /**< specifies how many sequential
+ registers are required */
+};
-/**
- * Classify a node.
- * @param env The architecture environment.
- * @param irn The node.
- * @return A classification of the node.
- */
-extern arch_irn_class_t arch_irn_classify(const arch_env_t *env, const ir_node *irn);
+static inline bool reg_reqs_equal(const arch_register_req_t *req1,
+ const arch_register_req_t *req2)
+{
+ if (req1 == req2)
+ return true;
+
+ if (req1->type != req2->type ||
+ req1->cls != req2->cls ||
+ req1->other_same != req2->other_same ||
+ req1->other_different != req2->other_different ||
+ (req1->limited != NULL) != (req2->limited != NULL))
+ return false;
+
+ if (req1->limited != NULL) {
+ size_t const n_regs = arch_register_class_n_regs(req1->cls);
+ if (!rbitsets_equal(req1->limited, req2->limited, n_regs))
+ return false;
+ }
+
+ return true;
+}
-/**
- * Get the flags of a node.
- * @param env The architecture environment.
- * @param irn The node.
- * @return The flags.
- */
-extern arch_irn_flags_t arch_irn_get_flags(const arch_env_t *env, const ir_node *irn);
+struct arch_irn_ops_t {
-#define arch_irn_is_ignore(env, irn) ((arch_irn_get_flags(env, irn) & arch_irn_flags_ignore) != 0)
+ /**
+ * Get the entity on the stack frame this node depends on.
+ * @param irn The node in question.
+ * @return The entity on the stack frame or NULL, if the node does not have
+ * a stack frame entity.
+ */
+ ir_entity *(*get_frame_entity)(const ir_node *irn);
-#define arch_irn_has_reg_class(env, irn, pos, cls) \
- ((cls) == arch_get_irn_reg_class(env, irn, pos))
+ /**
+ * Set the offset of a node carrying an entity on the stack frame.
+ * @param irn The node.
+ * @param offset The offset of the node's stack frame entity.
+ */
+ void (*set_frame_offset)(ir_node *irn, int offset);
-#define arch_irn_consider_in_reg_alloc(env, cls, irn) \
- (arch_irn_has_reg_class(env, irn, -1, cls) && !arch_irn_is_ignore(env, irn))
+ /**
+ * Returns the delta of the stackpointer for nodes that increment or
+ * decrement the stackpointer with a constant value. (push, pop
+ * nodes on most architectures).
+ * A positive value stands for an expanding stack area, a negative value for
+ * a shrinking one.
+ *
+ * @param irn The node
+ * @return 0 if the stackpointer is not modified with a constant
+ * value, otherwise the increment/decrement value
+ */
+ int (*get_sp_bias)(const ir_node *irn);
-/**
- * Somebody who can be asked about nodes.
- */
-struct _arch_irn_handler_t {
+ /**
+ * Get the estimated cycle count for @p irn.
+ *
+ * @param irn The node.
+ * @return The estimated cycle count for this operation
+ */
+ int (*get_op_estimated_cost)(const ir_node *irn);
- /**
- * Get the operations of an irn.
- * @param self The handler from which the method is invoked.
- * @param irn Some node.
- * @return Operations for that irn.
- */
- const void *(*get_irn_ops)(const arch_irn_handler_t *handler,
- const ir_node *irn);
+ /**
+ * Asks the backend whether operand @p i of @p irn can be loaded form memory
+ * internally
+ *
+ * @param irn The node.
+ * @param i Index of the argument we would like to know whether @p irn
+ * can load it form memory internally
+ * @return nonzero if argument can be loaded or zero otherwise
+ */
+ int (*possible_memory_operand)(const ir_node *irn, unsigned int i);
+ /**
+ * Ask the backend to assimilate @p reload of operand @p i into @p irn.
+ *
+ * @param irn The node.
+ * @param spill The spill.
+ * @param i The position of the reload.
+ */
+ void (*perform_memory_operand)(ir_node *irn, ir_node *spill,
+ unsigned int i);
};
/**
- * The code generator.
+ * Architecture interface.
*/
-struct _arch_code_generator_if_t {
+struct arch_isa_if_t {
+ /**
+ * Initializes the isa interface. This is necessary before calling any
+ * other functions from this interface.
+ */
+ void (*init)(void);
+ /**
+ * Fress resources allocated by this isa interface.
+ */
+ void (*finish)(void);
/**
- * Initialize the code generator.
- * @param file The file to dump to.
- * @param birg A backend IRG session.
- * @return A newly created code generator.
+ * Returns the frontend settings needed for this backend.
*/
- void *(*init)(FILE *file, const be_irg_t *birg);
+ const backend_params *(*get_params)(void);
/**
- * Called, when the graph is being normalized.
+ * lowers current program for target. See the documentation for
+ * be_lower_for_target() for details.
*/
- void (*prepare_graph)(void *self);
+ void (*lower_for_target)(void);
/**
- * Called before scheduling.
+ * parse an assembler constraint part and set flags according to its nature
+ * advances the *c pointer to point to the last parsed character (so if you
+ * parse a single character don't advance c)
*/
- void (*before_sched)(void *self);
+ asm_constraint_flags_t (*parse_asm_constraint)(const char **c);
/**
- * Called before register allocation.
+ * returns true if the string is a valid clobbered (register) in this
+ * backend
*/
- void (*before_ra)(void *self);
+ int (*is_valid_clobber)(const char *clobber);
/**
- * Called after register allocation to lower Spills to Stores
- * @param self The code generator
- * @param spill The spill node to lower
- * @return The new backend node which substitutes the spill
+ * Start codegeneration
+ * @return a new isa instance
*/
- ir_node *(*lower_spill)(void *self, ir_node *spill);
+ arch_env_t *(*begin_codegeneration)(const be_main_env_t *env);
/**
- * Called after register allocation to lower Reloads to Loads
- * @param self The code generator
- * @param reload The reload node to lower
- * @return The new backend node which substitutes the reload
+ * Free the isa instance.
*/
- ir_node *(*lower_reload)(void *self, ir_node *reload);
+ void (*end_codegeneration)(void *self);
/**
- * Called after everything happened.
- * The code generator must also be de-allocated here.
+ * Initialize the code generator for a graph
+ * @param irg A graph
*/
- void (*done)(void *self);
+ void (*init_graph)(ir_graph *irg);
-};
+ /**
+ * Get the ABI restrictions for procedure calls.
+ * @param call_type The call type of the method (procedure) in question.
+ * @param p The array of parameter locations to be filled.
+ */
+ void (*get_call_abi)(ir_type *call_type, be_abi_call_t *abi);
-#define _arch_cg_call(cg, func) \
-do { \
- if((cg)->impl->func) \
- (cg)->impl->func(cg); \
-} while(0)
+ /**
+ * mark node as rematerialized
+ */
+ void (*mark_remat)(ir_node *node);
-#define arch_code_generator_prepare_graph(cg) _arch_cg_call(cg, prepare_graph)
-#define arch_code_generator_before_sched(cg) _arch_cg_call(cg, before_sched)
-#define arch_code_generator_before_ra(cg) _arch_cg_call(cg, before_ra)
-#define arch_code_generator_done(cg) _arch_cg_call(cg, done)
+ /**
+ * return node used as base in pic code addresses
+ */
+ ir_node* (*get_pic_base)(ir_graph *irg);
-/**
- * Code generator base class.
- */
-struct _arch_code_generator_t {
- const arch_code_generator_if_t *impl;
-};
+ /**
+ * Create a spill instruction. We assume that spill instructions
+ * do not need any additional registers and do not affect cpu-flags in any
+ * way.
+ * Construct a sequence of instructions after @p after (the resulting nodes
+ * are already scheduled).
+ * Returns a mode_M value which is used as input for a reload instruction.
+ */
+ ir_node *(*new_spill)(ir_node *value, ir_node *after);
-/**
- * ISA base class.
- */
-struct _arch_isa_t {
- const arch_isa_if_t *impl;
- const arch_register_t *sp; /** The stack pointer register. */
- const arch_register_t *bp; /** The base pointer register. */
- const int stack_dir; /** -1 for decreasing, 1 for increasing. */
-};
+ /**
+ * Create a reload instruction. We assume that reload instructions do not
+ * need any additional registers and do not affect cpu-flags in any way.
+ * Constructs a sequence of instruction before @p before (the resulting
+ * nodes are already scheduled). A rewiring of users is not performed in
+ * this function.
+ * Returns a value representing the restored value.
+ */
+ ir_node *(*new_reload)(ir_node *value, ir_node *spilled_value,
+ ir_node *before);
-#define arch_isa_stack_dir(isa) ((isa)->stack_dir)
-#define arch_isa_sp(isa) ((isa)->sp)
-#define arch_isa_bp(isa) ((isa)->bp)
+ /**
+ * Checks if the given register is callee/caller saved.
+ * @deprecated, only necessary if backend still uses beabi functions
+ */
+ int (*register_saved_by)(const arch_register_t *reg, int callee);
-/**
- * Architecture interface.
- */
-struct _arch_isa_if_t {
+ /**
+ * Called directly after initialization. Backend should handle all
+ * intrinsics here.
+ */
+ void (*handle_intrinsics)(void);
-#ifdef WITH_LIBCORE
- void (*register_options)(lc_opt_entry_t *grp);
-#endif
+ /**
+ * Called before abi introduce.
+ */
+ void (*before_abi)(ir_graph *irg);
- /**
- * Initialize the isa interface.
- */
- void *(*init)(void);
-
- /**
- * Free the isa instance.
- */
- void (*done)(void *self);
-
- /**
- * Get the the number of register classes in the isa.
- * @return The number of register classes.
- */
- int (*get_n_reg_class)(const void *self);
-
- /**
- * Get the i-th register class.
- * @param i The number of the register class.
- * @return The register class.
- */
- const arch_register_class_t *(*get_reg_class)(const void *self, int i);
-
- /**
- * Get the register class which shall be used to store a value of a given mode.
- * @param self The this pointer.
- * @param mode The mode in question.
- * @return A register class which can hold values of the given mode.
- */
- const arch_register_class_t *(*get_reg_class_for_mode)(const void *self, const ir_mode *mode);
-
- /**
- * Get the ABI restrictions for procedure calls.
- * @param self The this pointer.
- * @param method_type The type of the method (procedure) in question.
- * @param p The array of parameter locations to be filled.
- */
- void (*get_call_abi)(const void *self, ir_type *method_type, be_abi_call_t *abi);
-
- /**
- * The irn handler for this architecture.
- * The irn handler is registered by the Firm back end
- * when the architecture is initialized.
- * (May be NULL).
- */
- const arch_irn_handler_t *(*get_irn_handler)(const void *self);
-
- /**
- * Get the code generator interface.
- * @param self The this pointer.
- * @return Some code generator interface.
- */
- const arch_code_generator_if_t *(*get_code_generator_if)(void *self);
-
- /**
- * Get the list scheduler to use.
- * @param self The isa object.
- * @return The list scheduler selector.
- */
- const list_sched_selector_t *(*get_list_sched_selector)(const void *self);
-
- /**
- * Take a proj from a call, set the correct register and projnum for this proj
- * @param self The isa object.
- * @param proj The proj
- * @param is_keep Non-zero if proj is a Keep argument
- * @return The backend proj number assigned to this proj
- */
- long (*handle_call_proj)(const void *self, ir_node *proj, int is_keep);
-};
+ /**
+ * Called, when the graph is being normalized.
+ */
+ void (*prepare_graph)(ir_graph *irg);
-#define arch_isa_get_n_reg_class(isa) ((isa)->impl->get_n_reg_class(isa))
-#define arch_isa_get_reg_class(isa,i) ((isa)->impl->get_reg_class(isa, i))
-#define arch_isa_get_irn_handler(isa) ((isa)->impl->get_irn_handler(isa))
-#define arch_isa_get_call_abi(isa,tp,abi) ((isa)->impl->get_call_abi((isa), (tp), (abi)))
-#define arch_isa_get_reg_class_for_mode(isa,mode) ((isa)->impl->get_reg_class_for_mode((isa), (mode)))
-#define arch_isa_make_code_generator(isa,irg) ((isa)->impl->make_code_generator(isa, irg))
+ /**
+ * Called before register allocation.
+ */
+ void (*before_ra)(ir_graph *irg);
-#define ARCH_MAX_HANDLERS 8
+ /**
+ * Called directly before done is called. This should be the last place
+ * where the irg is modified.
+ */
+ void (*finish_graph)(ir_graph *irg);
-/**
- * Environment for the architecture infrastructure.
- * Keep this everywhere you're going.
- */
-struct _arch_env_t {
- const struct _be_node_factory_t *node_factory; /**< The node factory for be nodes. */
- arch_isa_t *isa; /**< The isa about which everything is. */
+ /**
+ * Called after everything happened. This call should emit the final
+ * assembly code but avoid changing the irg.
+ */
+ void (*emit)(ir_graph *irg);
+};
- arch_irn_handler_t const *handlers[ARCH_MAX_HANDLERS]; /**< The handlers are organized as
- a stack. */
+#define arch_env_end_codegeneration(env) ((env)->impl->end_codegeneration(env))
+#define arch_env_handle_intrinsics(env) \
+ do { if((env)->impl->handle_intrinsics != NULL) (env)->impl->handle_intrinsics(); } while(0)
+#define arch_env_get_call_abi(env,tp,abi) ((env)->impl->get_call_abi((tp), (abi)))
+#define arch_env_get_params(env) ((env)->impl->get_params())
+#define arch_env_parse_asm_constraint(env,c) ((env)->impl->parse_asm_constraint((c))
+#define arch_env_is_valid_clobber(env,clobber) ((env)->impl->is_valid_clobber((clobber))
+#define arch_env_mark_remat(env,node) \
+ do { if ((env)->impl->mark_remat != NULL) (env)->impl->mark_remat((node)); } while(0)
- int handlers_tos; /**< The stack pointer of the handler
- stack. */
-};
+#define arch_env_new_spill(env,value,after) ((env)->impl->new_spill(value, after))
+#define arch_env_new_reload(env,value,spilled,before) ((env)->impl->new_reload(value, spilled, before))
/**
- * Get the isa of an arch environment.
- * @param env The environment.
- * @return The isa with which the env was initialized with.
+ * ISA base class.
*/
-#define arch_env_get_isa(env) ((env)->isa)
+struct arch_env_t {
+ const arch_isa_if_t *impl;
+ unsigned n_registers; /**< number of registers */
+ const arch_register_t *registers; /**< register array */
+ unsigned n_register_classes; /**< number of register classes*/
+ const arch_register_class_t *register_classes; /**< register classes */
+ const arch_register_t *sp; /**< The stack pointer register. */
+ const arch_register_t *bp; /**< The base pointer register. */
+ int stack_alignment; /**< power of 2 stack alignment */
+ const be_main_env_t *main_env; /**< the be main environment */
+ int spill_cost; /**< cost for a be_Spill node */
+ int reload_cost; /**< cost for a be_Reload node */
+ bool custom_abi : 1; /**< backend does all abi handling
+ and does not need the generic
+ stuff from beabi.h/.c */
+};
-/**
- * Initialize the architecture environment struct.
- * @param isa The isa which shall be put into the environment.
- * @return The environment.
- */
-extern arch_env_t *arch_env_init(arch_env_t *env, const arch_isa_if_t *isa);
+static inline bool arch_irn_is_ignore(const ir_node *irn)
+{
+ const arch_register_req_t *req = arch_get_irn_register_req(irn);
+ return arch_register_req_is(req, ignore);
+}
+
+static inline bool arch_irn_consider_in_reg_alloc(
+ const arch_register_class_t *cls, const ir_node *node)
+{
+ const arch_register_req_t *req = arch_get_irn_register_req(node);
+ return req->cls == cls && !arch_register_req_is(req, ignore);
+}
/**
- * Add a node handler to the environment.
- * @param env The environment.
- * @param handler A node handler.
- * @return The environment itself.
+ * Iterate over all values defined by an instruction.
+ * Only looks at values in a certain register class where the requirements
+ * are not marked as ignore.
+ * Executes @p code for each definition.
*/
-extern arch_env_t *arch_env_add_irn_handler(arch_env_t *env, const arch_irn_handler_t *handler);
+#define be_foreach_definition_(node, ccls, value, code) \
+ do { \
+ if (get_irn_mode(node) == mode_T) { \
+ foreach_out_edge(node, edge_) { \
+ ir_node *const value = get_edge_src_irn(edge_); \
+ arch_register_req_t const *const req_ = arch_get_irn_register_req(value); \
+ if (req_->cls != ccls) \
+ continue; \
+ code \
+ } \
+ } else { \
+ arch_register_req_t const *const req_ = arch_get_irn_register_req(node); \
+ ir_node *const value = node; \
+ if (req_->cls == ccls) { \
+ code \
+ } \
+ } \
+ } while (0)
+
+#define be_foreach_definition(node, ccls, value, code) \
+ be_foreach_definition_(node, ccls, value, \
+ if (arch_register_req_is(req_, ignore)) \
+ continue; \
+ code \
+ )
+
+static inline const arch_register_class_t *arch_get_irn_reg_class(
+ const ir_node *node)
+{
+ const arch_register_req_t *req = arch_get_irn_register_req(node);
+ return req->cls;
+}
-#endif /* _FIRM_BEARCH_H */
+bool arch_reg_is_allocatable(const arch_register_req_t *req,
+ const arch_register_t *reg);
+
+#endif
projects / libfirm / blobdiff