/*
- * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
+ * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
*
* This file is part of libFirm.
*
#include "beinfo.h"
#include "be.h"
#include "beirg.h"
+#include "error.h"
+
+/**
+ * this constant is returned by the get_sp_bias functions if the stack
+ * is reset (usually because the frame pointer is copied to the stack
+ * pointer
+ */
+#define SP_BIAS_RESET INT_MIN
typedef enum arch_register_class_flags_t {
arch_register_class_flag_none = 0,
- arch_register_class_flag_manual_ra = 1, /**< don't do automatic register allocation for this class */
- arch_register_class_flag_state = 2
+ /** don't do automatic register allocation for this class */
+ arch_register_class_flag_manual_ra = 1U << 0,
+ /** the register models an abstract state (example: fpu rounding mode) */
+ arch_register_class_flag_state = 1U << 1
} arch_register_class_flags_t;
+ENUM_BITSET(arch_register_class_flags_t)
typedef enum arch_register_type_t {
arch_register_type_none = 0,
- arch_register_type_caller_save = 1, /**< The register must be saved by the caller
- upon a function call. It thus can be overwritten
- in the called function. */
- arch_register_type_callee_save = 2, /**< The register must be saved by the caller
- upon a function call. It thus can be overwritten
- in the called function. */
- arch_register_type_ignore = 4, /**< Do not consider this register when allocating. */
- arch_register_type_joker = 8, /**< The emitter can choose an arbitrary register */
- arch_register_type_virtual = 16, /**< This is just a virtual register.Virtual registers have
- nearly no constraints, it is a allowed to have multiple
- definition for the same register at a point) */
- arch_register_type_state = 32, /**< The register represents a state that should be handled by
- bestate code */
+ /** The register must be saved by the caller upon a function call. It thus
+ * can be overwritten in the called function. */
+ arch_register_type_caller_save = 1U << 0,
+ /** The register must be saved by the caller upon a function call. It thus
+ * can be overwritten in the called function. */
+ arch_register_type_callee_save = 1U << 1,
+ /** Do not consider this register when allocating. */
+ arch_register_type_ignore = 1U << 2,
+ /** The emitter can choose an arbitrary register. The register fulfills any
+ * register constraints as long as the register class matches */
+ arch_register_type_joker = 1U << 3,
+ /** This is just a virtual register. Virtual registers fulfill any register
+ * constraints as long as the register class matches. It is a allowed to
+ * have multiple definitions for the same virtual register at a point */
+ arch_register_type_virtual = 1U << 4,
+ /** The register represents a state that should be handled by bestate
+ * code */
+ arch_register_type_state = 1U << 5,
} arch_register_type_t;
+ENUM_BITSET(arch_register_type_t)
/**
* Different types of register allocation requirements.
*/
typedef enum arch_register_req_type_t {
- arch_register_req_type_none = 0, /**< No register requirement. */
- arch_register_req_type_normal = 1U << 0, /**< All registers in the class are allowed. */
- arch_register_req_type_limited = 1U << 1, /**< Only a real subset of the class is allowed. */
- arch_register_req_type_should_be_same = 1U << 2, /**< The register should be equal to another one at the node. */
- arch_register_req_type_must_be_different = 1U << 3, /**< The register must be unequal from some other at the node. */
- arch_register_req_type_ignore = 1U << 4, /**< ignore while allocating registers */
- arch_register_req_type_produces_sp = 1U << 5, /**< the output produces a new value for the stack pointer */
+ /** No register requirement. */
+ arch_register_req_type_none = 0,
+ /** All registers in the class are allowed. */
+ arch_register_req_type_normal = 1U << 0,
+ /** Only a real subset of the class is allowed. */
+ arch_register_req_type_limited = 1U << 1,
+ /** The register should be equal to another one at the node. */
+ arch_register_req_type_should_be_same = 1U << 2,
+ /** The register must be unequal from some other at the node. */
+ arch_register_req_type_must_be_different = 1U << 3,
+ /** The registernumber should be aligned (in case of multiregister values)*/
+ arch_register_req_type_aligned = 1U << 4,
+ /** ignore while allocating registers */
+ arch_register_req_type_ignore = 1U << 5,
+ /** the output produces a new value for the stack pointer
+ * (this is not really a constraint but a marker to guide the stackpointer
+ * rewiring logic) */
+ arch_register_req_type_produces_sp = 1U << 6,
} arch_register_req_type_t;
+ENUM_BITSET(arch_register_req_type_t)
extern const arch_register_req_t *arch_no_register_req;
void arch_dump_reqs_and_registers(FILE *F, const ir_node *node);
/**
- * Node classification. Mainly used for statistics.
+ * Node classification. Used for statistics and for detecting reload nodes.
*/
typedef enum arch_irn_class_t {
+ arch_irn_class_none = 0,
arch_irn_class_spill = 1 << 0,
arch_irn_class_reload = 1 << 1,
arch_irn_class_remat = 1 << 2,
arch_irn_class_copy = 1 << 3,
arch_irn_class_perm = 1 << 4
} arch_irn_class_t;
+ENUM_BITSET(arch_irn_class_t)
void arch_set_frame_offset(ir_node *irn, int bias);
ir_entity *arch_get_frame_entity(const ir_node *irn);
-void arch_set_frame_entity(ir_node *irn, ir_entity *ent);
int arch_get_sp_bias(ir_node *irn);
int arch_get_op_estimated_cost(const ir_node *irn);
-arch_inverse_t *arch_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obstack);
-int arch_possible_memory_operand(const ir_node *irn, unsigned int i);
-void arch_perform_memory_operand(ir_node *irn, ir_node *spill, unsigned int i);
+arch_inverse_t *arch_get_inverse(const ir_node *irn, int i,
+ arch_inverse_t *inverse,
+ struct obstack *obstack);
+int arch_possible_memory_operand(const ir_node *irn,
+ unsigned int i);
+void arch_perform_memory_operand(ir_node *irn, ir_node *spill,
+ unsigned int i);
/**
* Get the register requirements for a node.
*/
const arch_register_req_t *arch_get_register_req(const ir_node *irn, int pos);
-/**
- * Put all registers which shall not be ignored by the register
- * allocator in a bit set.
- * @param cls The register class to consider.
- * @param bs The bit set to put the registers to.
- */
-extern void arch_put_non_ignore_regs(const arch_register_class_t *cls, bitset_t *bs);
-
/**
* Check, if a register is assignable to an operand of a node.
* @param irn The node.
* @param reg The register.
* @return 1, if the register might be allocated to the operand 0 if not.
*/
-int arch_reg_is_allocatable(const ir_node *irn, int pos, const arch_register_t *reg);
+int arch_reg_is_allocatable(const ir_node *irn, int pos,
+ const arch_register_t *reg);
#define arch_reg_out_is_allocatable(irn, reg) arch_reg_is_allocatable(irn, -1, reg)
* @return The register class of the operand or NULL, if
* operand is a non-register operand.
*/
-const arch_register_class_t *arch_get_irn_reg_class(const ir_node *irn, int pos);
+const arch_register_class_t *arch_get_irn_reg_class(const ir_node *irn,
+ int pos);
#define arch_get_irn_reg_class_out(irn) arch_get_irn_reg_class(irn, -1)
*/
arch_irn_class_t arch_irn_classify(const ir_node *irn);
-#define arch_irn_class_is(irn, irn_class) ((arch_irn_classify(irn) & arch_irn_class_ ## irn_class) != 0)
-
/**
* Get the flags of a node.
* @param irn The node.
* A register.
*/
struct arch_register_t {
- const char *name; /**< The name of the register. */
- const arch_register_class_t *reg_class; /**< The class the register belongs to. */
- unsigned index; /**< The index of the register in the class. */
- arch_register_type_t type; /**< The type of the register. */
+ const char *name; /**< The name of the register. */
+ const arch_register_class_t *reg_class; /**< The class of the register */
+ unsigned short index; /**< The index of the register in
+ the class. */
+ unsigned short global_index; /** The global index this register
+ in the architecture. */
+ arch_register_type_t type; /**< The type of the register. */
+ /** register constraint allowing just this register */
const arch_register_req_t *single_req;
};
-static inline const arch_register_class_t *_arch_register_get_class(const arch_register_t *reg)
+static inline const arch_register_class_t *arch_register_get_class(
+ const arch_register_t *reg)
{
return reg->reg_class;
}
-static inline unsigned _arch_register_get_index(const arch_register_t *reg)
+static inline unsigned arch_register_get_index(const arch_register_t *reg)
{
return reg->index;
}
-static inline const char *_arch_register_get_name(const arch_register_t *reg)
+static inline const char *arch_register_get_name(const arch_register_t *reg)
{
return reg->name;
}
-#define arch_register_get_class(reg) _arch_register_get_class(reg)
-#define arch_register_get_index(reg) _arch_register_get_index(reg)
-#define arch_register_get_name(reg) _arch_register_get_name(reg)
-
-/**
- * Convenience macro to check for register type.
- * @param req A pointer to register.
- * @param kind The kind of type to check for (see arch_register_type_t).
- * @return 1, If register is of given kind, 0 if not.
- */
-#define arch_register_type_is(reg, kind) \
- (((reg)->type & arch_register_type_ ## kind) != 0)
-
/**
* A class of registers.
* Like general purpose or floating point.
/** return the register class flags */
#define arch_register_class_flags(cls) ((cls)->flags)
-static inline const arch_register_t *_arch_register_for_index(const arch_register_class_t *cls, unsigned idx)
+static inline const arch_register_t *arch_register_for_index(
+ const arch_register_class_t *cls, unsigned idx)
{
assert(idx < cls->n_regs);
return &cls->regs[idx];
}
-#define arch_register_for_index(cls, idx) _arch_register_for_index(cls, idx)
-
/**
* Convenience macro to check for set constraints.
* @param req A pointer to register requirements.
- * @param kind The kind of constraint to check for (see arch_register_req_type_t).
+ * @param kind The kind of constraint to check for
+ * (see arch_register_req_type_t).
* @return 1, If the kind of constraint is present, 0 if not.
*/
#define arch_register_req_is(req, kind) \
* Expresses requirements to register allocation for an operand.
*/
struct arch_register_req_t {
- arch_register_req_type_t type; /**< The type of the constraint. */
- const arch_register_class_t *cls; /**< The register class this constraint belongs to. */
-
+ arch_register_req_type_t type; /**< The type of the constraint. */
+ const arch_register_class_t *cls; /**< The register class this constraint
+ belongs to. */
const unsigned *limited; /**< allowed register bitset */
-
unsigned other_same; /**< Bitmask of ins which should use the
same register (should_be_same). */
unsigned other_different; /**< Bitmask of ins which shall use a
different register
(must_be_different) */
+ unsigned char width; /**< specifies how many sequential
+ registers are required */
};
static inline int reg_reqs_equal(const arch_register_req_t *req1,
return 0;
n_regs = arch_register_class_n_regs(req1->cls);
- if (!rbitset_equal(req1->limited, req2->limited, n_regs))
+ if (!rbitsets_equal(req1->limited, req2->limited, n_regs))
return 0;
}
int n; /**< count of nodes returned in nodes array */
int costs; /**< costs of this remat */
- /**< nodes for this inverse operation. shall be in
- * schedule order. last element is the target value
- */
+ /** nodes for this inverse operation. shall be in schedule order.
+ * last element is the target value */
ir_node **nodes;
};
struct arch_irn_ops_t {
- /**
- * Get the register requirements for a given operand.
- * @param irn The node.
- * @param pos The operand's position
- * @return The register requirements for the selected operand.
- * The pointer returned is never NULL.
- */
- const arch_register_req_t *(*get_irn_reg_req_in)(const ir_node *irn, int pos);
-
/**
* Classify the node.
* @param irn The node.
/**
* Get the entity on the stack frame this node depends on.
* @param irn The node in question.
- * @return The entity on the stack frame or NULL, if the node does not have a
- * stack frame entity.
+ * @return The entity on the stack frame or NULL, if the node does not have
+ * a stack frame entity.
*/
ir_entity *(*get_frame_entity)(const ir_node *irn);
- /**
- * Set the entity on the stack frame this node depends on.
- * @param irn The node in question.
- * @param ent The entity to set
- */
- void (*set_frame_entity)(ir_node *irn, ir_entity *ent);
-
/**
* Set the offset of a node carrying an entity on the stack frame.
* @param irn The node.
* of the given node as result.
*
* @param irn The original operation
- * @param i Index of the argument we want the inverse operation to yield
+ * @param i Index of the argument we want the inverse operation to
+ * yield
* @param inverse struct to be filled with the resulting inverse op
- * @param obstack The obstack to use for allocation of the returned nodes array
+ * @param obstack The obstack to use for allocation of the returned nodes
+ * array
* @return The inverse operation or NULL if operation invertible
*/
- arch_inverse_t *(*get_inverse)(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obstack);
+ arch_inverse_t *(*get_inverse)(const ir_node *irn, int i,
+ arch_inverse_t *inverse,
+ struct obstack *obstack);
/**
* Get the estimated cycle count for @p irn.
*
* @param irn The node.
- *
* @return The estimated cycle count for this operation
*/
int (*get_op_estimated_cost)(const ir_node *irn);
/**
- * Asks the backend whether operand @p i of @p irn can be loaded form memory internally
+ * Asks the backend whether operand @p i of @p irn can be loaded form memory
+ * internally
*
* @param irn The node.
- * @param i Index of the argument we would like to know whether @p irn can load it form memory internally
- *
+ * @param i Index of the argument we would like to know whether @p irn
+ * can load it form memory internally
* @return nonzero if argument can be loaded or zero otherwise
*/
int (*possible_memory_operand)(const ir_node *irn, unsigned int i);
* @param spill The spill.
* @param i The position of the reload.
*/
- void (*perform_memory_operand)(ir_node *irn, ir_node *spill, unsigned int i);
-};
-
-/**
- * The code generator interface.
- */
-struct arch_code_generator_if_t {
- /**
- * Initialize the code generator.
- * @param birg A backend IRG session.
- * @return A newly created code generator.
- */
- void *(*init)(be_irg_t *birg);
-
- /**
- * return node used as base in pic code addresses
- */
- ir_node* (*get_pic_base)(void *self);
-
- /**
- * Called before abi introduce.
- */
- void (*before_abi)(void *self);
-
- /**
- * Called, when the graph is being normalized.
- */
- void (*prepare_graph)(void *self);
-
- /**
- * Backend may provide an own spiller.
- * This spiller needs to spill all register classes.
- */
- void (*spill)(void *self, be_irg_t *birg);
-
- /**
- * Called before register allocation.
- */
- void (*before_ra)(void *self);
-
- /**
- * Called after register allocation.
- */
- void (*after_ra)(void *self);
-
- /**
- * Called directly before done is called. This should be the last place
- * where the irg is modified.
- */
- void (*finish)(void *self);
-
- /**
- * Called after everything happened. This call should emit the final
- * assembly code but avoid changing the irg.
- * The code generator must also be de-allocated here.
- */
- void (*done)(void *self);
-};
-
-/**
- * helper macro: call function func from the code generator
- * if it's implemented.
- */
-#define _arch_cg_call(cg, func) \
-do { \
- if((cg)->impl->func) \
- (cg)->impl->func(cg); \
-} while(0)
-
-#define _arch_cg_call_env(cg, env, func) \
-do { \
- if((cg)->impl->func) \
- (cg)->impl->func(cg, env); \
-} while(0)
-
-#define arch_code_generator_before_abi(cg) _arch_cg_call(cg, before_abi)
-#define arch_code_generator_prepare_graph(cg) _arch_cg_call(cg, prepare_graph)
-#define arch_code_generator_before_ra(cg) _arch_cg_call(cg, before_ra)
-#define arch_code_generator_after_ra(cg) _arch_cg_call(cg, after_ra)
-#define arch_code_generator_finish(cg) _arch_cg_call(cg, finish)
-#define arch_code_generator_done(cg) _arch_cg_call(cg, done)
-#define arch_code_generator_spill(cg, birg) _arch_cg_call_env(cg, birg, spill)
-#define arch_code_generator_has_spiller(cg) ((cg)->impl->spill != NULL)
-#define arch_code_generator_get_pic_base(cg) \
- ((cg)->impl->get_pic_base != NULL ? (cg)->impl->get_pic_base(cg) : NULL)
-
-/**
- * Code generator base class.
- */
-struct arch_code_generator_t {
- const arch_code_generator_if_t *impl;
+ void (*perform_memory_operand)(ir_node *irn, ir_node *spill,
+ unsigned int i);
};
/**
*/
arch_env_t *(*init)(FILE *file_handle);
+ /**
+ * lowers current program for target. See the documentation for
+ * be_lower_for_target() for details.
+ */
+ void (*lower_for_target)(void);
+
/**
* Free the isa instance.
*/
void (*handle_intrinsics)(void);
/**
- * Get the the number of register classes in the isa.
- * @return The number of register classes.
- */
- unsigned (*get_n_reg_class)(void);
-
- /**
- * Get the i-th register class.
- * @param i The number of the register class.
- * @return The register class.
- */
- const arch_register_class_t *(*get_reg_class)(unsigned i);
-
- /**
- * Get the register class which shall be used to store a value of a given mode.
+ * Get the register class which shall be used to store a value of a given
+ * mode.
* @param self The this pointer.
* @param mode The mode in question.
* @return A register class which can hold values of the given mode.
* @param call_type The call type of the method (procedure) in question.
* @param p The array of parameter locations to be filled.
*/
- void (*get_call_abi)(const void *self, ir_type *call_type, be_abi_call_t *abi);
-
- /**
- * Get the code generator interface.
- * @param self The this pointer.
- * @return Some code generator interface.
- */
- const arch_code_generator_if_t *(*get_code_generator_if)(void *self);
-
- /**
- * Get the list scheduler to use. There is already a selector given, the
- * backend is free to modify and/or ignore it.
- *
- * @param self The isa object.
- * @param selector The selector given by options.
- * @return The list scheduler selector.
- */
- const list_sched_selector_t *(*get_list_sched_selector)(const void *self, list_sched_selector_t *selector);
-
- /**
- * Get the ILP scheduler to use.
- * @param self The isa object.
- * @return The ILP scheduler selector
- */
- const ilp_sched_selector_t *(*get_ilp_sched_selector)(const void *self);
+ void (*get_call_abi)(const void *self, ir_type *call_type,
+ be_abi_call_t *abi);
/**
* Get the necessary alignment for storing a register of given class.
*/
const backend_params *(*get_params)(void);
- /**
- * Returns an 2-dim array of execution units, @p irn can be executed on.
- * The first dimension is the type, the second the allowed units of this
- * type.
- * Each dimension is a NULL terminated list.
- * @param self The isa object.
- * @param irn The node.
- * @return An array of allowed execution units.
- * exec_unit = {
- * { unit1_of_tp1, ..., unitX1_of_tp1, NULL },
- * ...,
- * { unit1_of_tpY, ..., unitXn_of_tpY, NULL },
- * NULL
- * };
- */
- const be_execution_unit_t ***(*get_allowed_execution_units)(const ir_node *irn);
-
- /**
- * Return the abstract machine for this isa.
- * @param self The isa object.
- */
- const be_machine_t *(*get_machine)(const void *self);
-
/**
* Return an ordered list of irgs where code should be generated for.
* If NULL is returned, all irg will be taken into account and they will be
* generated in an arbitrary order.
* @param self The isa object.
- * @param irgs A flexible array ARR_F of length 0 where the backend can append the desired irgs.
- * @return A flexible array ARR_F containing all desired irgs in the desired order.
+ * @param irgs A flexible array ARR_F of length 0 where the backend can
+ * append the desired irgs.
+ * @return A flexible array ARR_F containing all desired irgs in the
+ * desired order.
*/
ir_graph **(*get_backend_irg_list)(const void *self, ir_graph ***irgs);
* backend
*/
int (*is_valid_clobber)(const char *clobber);
+
+ /**
+ * Initialize the code generator.
+ * @param irg A graph
+ * @return A newly created code generator.
+ */
+ void (*init_graph)(ir_graph *irg);
+
+ /**
+ * return node used as base in pic code addresses
+ */
+ ir_node* (*get_pic_base)(ir_graph *irg);
+
+ /**
+ * Called before abi introduce.
+ */
+ void (*before_abi)(ir_graph *irg);
+
+ /**
+ * Called, when the graph is being normalized.
+ */
+ void (*prepare_graph)(ir_graph *irg);
+
+ /**
+ * Called before register allocation.
+ */
+ void (*before_ra)(ir_graph *irg);
+
+ /**
+ * Called after register allocation.
+ */
+ void (*after_ra)(ir_graph *irg);
+
+ /**
+ * Called directly before done is called. This should be the last place
+ * where the irg is modified.
+ */
+ void (*finish)(ir_graph *irg);
+
+ /**
+ * Called after everything happened. This call should emit the final
+ * assembly code but avoid changing the irg.
+ * The code generator must also be de-allocated here.
+ */
+ void (*emit)(ir_graph *irg);
};
#define arch_env_done(env) ((env)->impl->done(env))
#define arch_env_handle_intrinsics(env) \
do { if((env)->impl->handle_intrinsics != NULL) (env)->impl->handle_intrinsics(); } while(0)
-#define arch_env_get_n_reg_class(env) ((env)->impl->get_n_reg_class())
-#define arch_env_get_reg_class(env,i) ((env)->impl->get_reg_class(i))
#define arch_env_get_reg_class_for_mode(env,mode) ((env)->impl->get_reg_class_for_mode((mode)))
#define arch_env_get_call_abi(env,tp,abi) ((env)->impl->get_call_abi((env), (tp), (abi)))
-#define arch_env_get_code_generator_if(env) ((env)->impl->get_code_generator_if((env)))
-#define arch_env_get_list_sched_selector(env,selector) ((env)->impl->get_list_sched_selector((env), (selector)))
-#define arch_env_get_ilp_sched_selector(env) ((env)->impl->get_ilp_sched_selector(env))
#define arch_env_get_reg_class_alignment(env,cls) ((env)->impl->get_reg_class_alignment((cls)))
#define arch_env_get_params(env) ((env)->impl->get_params())
#define arch_env_get_allowed_execution_units(env,irn) ((env)->impl->get_allowed_execution_units((irn)))
*/
struct arch_env_t {
const arch_isa_if_t *impl;
- const arch_register_t *sp; /** The stack pointer register. */
- const arch_register_t *bp; /** The base pointer register. */
- const arch_register_class_t *link_class; /** The static link pointer register class. */
- int stack_dir; /** -1 for decreasing, 1 for increasing. */
- int stack_alignment; /** power of 2 stack alignment */
- const be_main_env_t *main_env; /** the be main environment */
- int spill_cost; /** cost for a be_Spill node */
- int reload_cost; /** cost for a be_Reload node */
+ unsigned n_registers; /**< number of registers */
+ const arch_register_t *registers; /**< register array */
+ unsigned n_register_classes; /**< number of register classes*/
+ const arch_register_class_t *register_classes; /**< register classes */
+ const arch_register_t *sp; /**< The stack pointer register. */
+ const arch_register_t *bp; /**< The base pointer register. */
+ const arch_register_class_t *link_class; /**< The static link pointer
+ register class. */
+ int stack_dir; /**< -1 for decreasing, 1 for
+ increasing. */
+ int stack_alignment; /**< power of 2 stack alignment */
+ const be_main_env_t *main_env; /**< the be main environment */
+ int spill_cost; /**< cost for a be_Spill node */
+ int reload_cost; /**< cost for a be_Reload node */
+ bool custom_abi : 1; /**< backend does all abi handling
+ and does not need the generic
+ stuff from beabi.h/.c */
};
static inline unsigned arch_irn_get_n_outs(const ir_node *node)
if (info->out_infos == NULL)
return 0;
- return ARR_LEN(info->out_infos);
+ return (unsigned)ARR_LEN(info->out_infos);
}
static inline const arch_irn_ops_t *get_irn_ops_simple(const ir_node *node)
int pos = 0;
backend_info_t *info;
+ /* you have to query the Proj nodes for the constraints (or use
+ * arch_get_out_register_req. Querying a mode_T node and expecting
+ * arch_no_register_req is a bug in your code! */
+ assert(get_irn_mode(irn) != mode_T);
+
if (is_Proj(irn)) {
pos = get_Proj_proj(irn);
irn = get_Proj_pred(irn);
- } else if (get_irn_mode(irn) == mode_T) {
- /* TODO: find out who does this and fix the caller! */
- return arch_no_register_req;
}
+
info = be_get_info(irn);
if (info->out_infos == NULL)
return arch_no_register_req;
static inline const arch_register_req_t *arch_get_in_register_req(
const ir_node *node, int pos)
{
- const arch_irn_ops_t *ops = get_irn_ops_simple(node);
- return ops->get_irn_reg_req_in(node, pos);
+ const backend_info_t *info = be_get_info(node);
+ if (info->in_reqs == NULL)
+ return arch_no_register_req;
+ return info->in_reqs[pos];
}
/**
info->out_infos[pos].req = req;
}
+static inline void arch_set_in_register_reqs(ir_node *node,
+ const arch_register_req_t **in_reqs)
+{
+ backend_info_t *info = be_get_info(node);
+ info->in_reqs = in_reqs;
+}
+
+static inline const arch_register_req_t **arch_get_in_register_reqs(
+ const ir_node *node)
+{
+ backend_info_t *info = be_get_info(node);
+ return info->in_reqs;
+}
+
+/**
+ * Iterate over all values defined by an instruction.
+ * Only looks at values in a certain register class where the requirements
+ * are not marked as ignore.
+ * Executes @p code for each definition.
+ */
+#define be_foreach_definition_(node, cls, value, code) \
+ do { \
+ if (get_irn_mode(node) == mode_T) { \
+ const ir_edge_t *edge_; \
+ foreach_out_edge(node, edge_) { \
+ const arch_register_req_t *req_; \
+ value = get_edge_src_irn(edge_); \
+ req_ = arch_get_register_req_out(value); \
+ if (req_->cls != cls) \
+ continue; \
+ code \
+ } \
+ } else { \
+ const arch_register_req_t *req_ = arch_get_register_req_out(node); \
+ value = node; \
+ if (req_->cls == cls) { \
+ code \
+ } \
+ } \
+ } while (0)
+
+#define be_foreach_definition(node, cls, value, code) \
+ be_foreach_definition_(node, cls, value, \
+ if (req_->type & arch_register_req_type_ignore) \
+ continue; \
+ code \
+ )
+
#endif
projects / libfirm / blobdiff