#include "firm_config.h"
-#ifdef WITH_LIBCORE
-#include <libcore/lc_opts.h>
-#endif
-
#include "firm_types.h"
#include "bitset.h"
#include "bearch_t.h"
#include "be_t.h"
#include "bemachine.h"
+#include "beirg.h"
struct _be_node_factory_t;
* Different types of register allocation requirements.
*/
typedef enum _arch_register_req_type_t {
- arch_register_req_type_none = 0, /**< No register requirement. */
-
- arch_register_req_type_normal = 1, /**< All registers in the class
- are allowed. */
-
- arch_register_req_type_limited = 2, /**< Only a real subset of
- the class is allowed. */
-
- arch_register_req_type_should_be_same = 4, /**< The register should be equal
- another one at the node. */
-
- arch_register_req_type_should_be_different = 8, /**< The register must be unequal
- to some other at the node. */
-
- arch_register_req_type_should_be_different_from_all = 16, /**< The register must be different from
- all in's at the node */
+ arch_register_req_type_none = 0, /**< No register requirement. */
+ arch_register_req_type_normal = 1, /**< All registers in the class are allowed. */
+ arch_register_req_type_limited = 2, /**< Only a real subset of the class is allowed. */
+ arch_register_req_type_should_be_same = 4, /**< The register should be equal another one at the node. */
+ arch_register_req_type_should_be_different = 8, /**< The register must be unequal to some other at the node. */
+ arch_register_req_type_should_be_different_from_all = 16, /**< The register must be different from all in's at the node */
} arch_register_req_type_t;
/**
* Certain node classes which are relevant for the register allocator.
*/
typedef enum _arch_irn_class_t {
- arch_irn_class_normal = 1 << 0,
- arch_irn_class_spill = 1 << 1,
- arch_irn_class_reload = 1 << 2,
- arch_irn_class_copy = 1 << 3,
- arch_irn_class_perm = 1 << 4,
- arch_irn_class_branch = 1 << 5,
- arch_irn_class_call = 1 << 6,
- arch_irn_class_const = 1 << 7,
- arch_irn_class_load = 1 << 8,
- arch_irn_class_store = 1 << 9,
- arch_irn_class_stackparam = 1 << 10,
+ arch_irn_class_normal = 1 << 0,
+ arch_irn_class_spill = 1 << 1,
+ arch_irn_class_reload = 1 << 2,
+ arch_irn_class_copy = 1 << 3,
+ arch_irn_class_perm = 1 << 4,
+ arch_irn_class_branch = 1 << 5,
+ arch_irn_class_call = 1 << 6,
+ arch_irn_class_const = 1 << 7,
+ arch_irn_class_load = 1 << 8,
+ arch_irn_class_store = 1 << 9,
+ arch_irn_class_stackparam = 1 << 10,
} arch_irn_class_t;
/**
* @param self The self pointer.
* @param irn The node.
* @param pos The operand's position
- * (-1 for the result of the node, 0..n for the input
- * operands).
+ * (-1 for the result of the node, 0..n for the input operands).
* @return The register requirements for the selected operand.
* The pointer returned is never NULL.
*/
#define arch_irn_is(env, irn, flag) ((arch_irn_get_flags(env, irn) & arch_irn_flags_ ## flag) != 0)
#define arch_irn_has_reg_class(env, irn, pos, cls) \
- ((cls) == arch_get_irn_reg_class(env, irn, pos))
+ ((cls) == arch_get_irn_reg_class(env, irn, pos))
#define arch_irn_consider_in_reg_alloc(env, cls, irn) \
(arch_irn_has_reg_class(env, irn, -1, cls) && !arch_irn_is(env, irn, ignore))
* Backend may provide an own spiller.
* This spiller needs to spill all register classes.
*/
- void (*spill)(void *self, void *env);
+ void (*spill)(void *self, be_irg_t *birg);
/**
* Called before scheduling.
#define arch_code_generator_after_ra(cg) _arch_cg_call(cg, after_ra)
#define arch_code_generator_finish(cg) _arch_cg_call(cg, finish)
#define arch_code_generator_done(cg) _arch_cg_call(cg, done)
-#define arch_code_generator_spill(cg, env) _arch_cg_call_env(cg, env, spill)
+#define arch_code_generator_spill(cg, birg) _arch_cg_call_env(cg, birg, spill)
#define arch_code_generator_has_spiller(cg) ((cg)->impl->spill != NULL)
/**
*/
const be_machine_t *(*get_machine)(const void *self);
-#ifdef WITH_LIBCORE
/**
- * Register command line options for this backend.
- * @param grp The root group.
+ * Return an ordered list of irgs where code should be generated for.
+ * If NULL is returned, all irg will be taken into account and they will be
+ * generated in an arbitrary order.
+ * @param self The isa object.
+ * @param irgs A flexible array ARR_F of length 0 where the backend cann append the desired irgs.
+ * @return A flexible array ARR_F containing all desired irgs in the desired order.
*/
- void (*register_options)(lc_opt_entry_t *grp);
-#endif
+ ir_graph **(*get_backend_irg_list)(const void *self, ir_graph ***irgs);
};
#define arch_isa_get_n_reg_class(isa) ((isa)->impl->get_n_reg_class(isa))
#define arch_isa_get_reg_class_alignment(isa, cls) ((isa)->impl->get_reg_class_alignment((isa), (cls)))
#define arch_isa_get_allowed_execution_units(isa, irn) ((isa)->impl->get_allowed_execution_units((isa), (irn)))
#define arch_isa_get_machine(isa) ((isa)->impl->get_machine((isa)))
+#define arch_isa_get_backend_irg_list(isa, irgs) ((isa)->impl->get_backend_irg_list((isa), (irgs)))
#define ARCH_MAX_HANDLERS 8
*/
extern const arch_irn_handler_t *arch_env_pop_irn_handler(arch_env_t *env);
+/**
+ * Register an instruction set architecture
+ */
+void be_register_isa_if(const char *name, const arch_isa_if_t *isa);
+
#endif /* _FIRM_BEARCH_H */
projects / libfirm / blobdiff