#include "beinfo.h"
#include "be.h"
#include "beirg.h"
+#include "error.h"
typedef enum arch_register_class_flags_t {
arch_register_class_flag_none = 0,
- arch_register_class_flag_manual_ra = 1, /**< don't do automatic register allocation for this class */
- arch_register_class_flag_state = 2
+ /** don't do automatic register allocation for this class */
+ arch_register_class_flag_manual_ra = 1U << 0,
+ /** the register models an abstract state (example: fpu rounding mode) */
+ arch_register_class_flag_state = 1U << 1
} arch_register_class_flags_t;
typedef enum arch_register_type_t {
arch_register_type_none = 0,
- arch_register_type_caller_save = 1, /**< The register must be saved by the caller
- upon a function call. It thus can be overwritten
- in the called function. */
- arch_register_type_callee_save = 2, /**< The register must be saved by the caller
- upon a function call. It thus can be overwritten
- in the called function. */
- arch_register_type_ignore = 4, /**< Do not consider this register when allocating. */
- arch_register_type_joker = 8, /**< The emitter can choose an arbitrary register */
- arch_register_type_virtual = 16, /**< This is just a virtual register.Virtual registers have
- nearly no constraints, it is a allowed to have multiple
- definition for the same register at a point) */
- arch_register_type_state = 32, /**< The register represents a state that should be handled by
- bestate code */
+ /** The register must be saved by the caller upon a function call. It thus
+ * can be overwritten in the called function. */
+ arch_register_type_caller_save = 1U << 0,
+ /** The register must be saved by the caller upon a function call. It thus
+ * can be overwritten in the called function. */
+ arch_register_type_callee_save = 1U << 1,
+ /** Do not consider this register when allocating. */
+ arch_register_type_ignore = 1U << 2,
+ /** The emitter can choose an arbitrary register. The register fulfills any
+ * register constraints as long as the register class matches */
+ arch_register_type_joker = 1U << 3,
+ /** This is just a virtual register. Virtual registers fulfill any register
+ * constraints as long as the register class matches. It is a allowed to
+ * have multiple definitions for the same virtual register at a point */
+ arch_register_type_virtual = 1U << 4,
+ /** The register represents a state that should be handled by bestate
+ * code */
+ arch_register_type_state = 1U << 5,
} arch_register_type_t;
/**
* Different types of register allocation requirements.
*/
typedef enum arch_register_req_type_t {
- arch_register_req_type_none = 0, /**< No register requirement. */
- arch_register_req_type_normal = 1U << 0, /**< All registers in the class are allowed. */
- arch_register_req_type_limited = 1U << 1, /**< Only a real subset of the class is allowed. */
- arch_register_req_type_should_be_same = 1U << 2, /**< The register should be equal to another one at the node. */
- arch_register_req_type_must_be_different = 1U << 3, /**< The register must be unequal from some other at the node. */
- arch_register_req_type_ignore = 1U << 4, /**< ignore while allocating registers */
- arch_register_req_type_produces_sp = 1U << 5, /**< the output produces a new value for the stack pointer */
+ /** No register requirement. */
+ arch_register_req_type_none = 0,
+ /** All registers in the class are allowed. */
+ arch_register_req_type_normal = 1U << 0,
+ /** Only a real subset of the class is allowed. */
+ arch_register_req_type_limited = 1U << 1,
+ /** The register should be equal to another one at the node. */
+ arch_register_req_type_should_be_same = 1U << 2,
+ /** The register must be unequal from some other at the node. */
+ arch_register_req_type_must_be_different = 1U << 3,
+ /** The registernumber should be aligned (in case of multiregister values)*/
+ arch_register_req_type_aligned = 1U << 4,
+ /** ignore while allocating registers */
+ arch_register_req_type_ignore = 1U << 5,
+ /** the output produces a new value for the stack pointer
+ * (this is not really a constraint but a marker to guide the stackpointer
+ * rewiring logic) */
+ arch_register_req_type_produces_sp = 1U << 6,
} arch_register_req_type_t;
extern const arch_register_req_t *arch_no_register_req;
void arch_dump_reqs_and_registers(FILE *F, const ir_node *node);
/**
- * Node classification. Mainly used for statistics.
+ * Node classification. Used for statistics and for detecting reload nodes.
*/
typedef enum arch_irn_class_t {
arch_irn_class_spill = 1 << 0,
void arch_set_frame_offset(ir_node *irn, int bias);
ir_entity *arch_get_frame_entity(const ir_node *irn);
-void arch_set_frame_entity(ir_node *irn, ir_entity *ent);
int arch_get_sp_bias(ir_node *irn);
int arch_get_op_estimated_cost(const ir_node *irn);
-arch_inverse_t *arch_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obstack);
-int arch_possible_memory_operand(const ir_node *irn, unsigned int i);
-void arch_perform_memory_operand(ir_node *irn, ir_node *spill, unsigned int i);
+arch_inverse_t *arch_get_inverse(const ir_node *irn, int i,
+ arch_inverse_t *inverse,
+ struct obstack *obstack);
+int arch_possible_memory_operand(const ir_node *irn,
+ unsigned int i);
+void arch_perform_memory_operand(ir_node *irn, ir_node *spill,
+ unsigned int i);
/**
* Get the register requirements for a node.
* @param cls The register class to consider.
* @param bs The bit set to put the registers to.
*/
-extern void arch_put_non_ignore_regs(const arch_register_class_t *cls, bitset_t *bs);
+extern void arch_put_non_ignore_regs(const arch_register_class_t *cls,
+ bitset_t *bs);
/**
* Check, if a register is assignable to an operand of a node.
* @param reg The register.
* @return 1, if the register might be allocated to the operand 0 if not.
*/
-int arch_reg_is_allocatable(const ir_node *irn, int pos, const arch_register_t *reg);
+int arch_reg_is_allocatable(const ir_node *irn, int pos,
+ const arch_register_t *reg);
#define arch_reg_out_is_allocatable(irn, reg) arch_reg_is_allocatable(irn, -1, reg)
* @return The register class of the operand or NULL, if
* operand is a non-register operand.
*/
-const arch_register_class_t *arch_get_irn_reg_class(const ir_node *irn, int pos);
+const arch_register_class_t *arch_get_irn_reg_class(const ir_node *irn,
+ int pos);
#define arch_get_irn_reg_class_out(irn) arch_get_irn_reg_class(irn, -1)
*/
arch_irn_class_t arch_irn_classify(const ir_node *irn);
-#define arch_irn_class_is(irn, irn_class) ((arch_irn_classify(irn) & arch_irn_class_ ## irn_class) != 0)
-
/**
* Get the flags of a node.
* @param irn The node.
* A register.
*/
struct arch_register_t {
- const char *name; /**< The name of the register. */
- const arch_register_class_t *reg_class; /**< The class the register belongs to. */
- unsigned index; /**< The index of the register in the class. */
- arch_register_type_t type; /**< The type of the register. */
+ const char *name; /**< The name of the register. */
+ const arch_register_class_t *reg_class; /**< The class of the register */
+ unsigned index; /**< The index of the register in
+ the class. */
+ arch_register_type_t type; /**< The type of the register. */
+ /** register constraint allowing just this register */
const arch_register_req_t *single_req;
};
-static inline const arch_register_class_t *
-_arch_register_get_class(const arch_register_t *reg)
+static inline const arch_register_class_t *_arch_register_get_class(
+ const arch_register_t *reg)
{
return reg->reg_class;
}
-static inline
-unsigned _arch_register_get_index(const arch_register_t *reg)
+static inline unsigned _arch_register_get_index(const arch_register_t *reg)
{
return reg->index;
}
-static inline
-const char *_arch_register_get_name(const arch_register_t *reg)
+static inline const char *_arch_register_get_name(const arch_register_t *reg)
{
return reg->name;
}
/** return the register class flags */
#define arch_register_class_flags(cls) ((cls)->flags)
-static inline const arch_register_t *
-_arch_register_for_index(const arch_register_class_t *cls, unsigned idx)
+static inline const arch_register_t *_arch_register_for_index(
+ const arch_register_class_t *cls, unsigned idx)
{
assert(idx < cls->n_regs);
return &cls->regs[idx];
/**
* Convenience macro to check for set constraints.
* @param req A pointer to register requirements.
- * @param kind The kind of constraint to check for (see arch_register_req_type_t).
+ * @param kind The kind of constraint to check for
+ * (see arch_register_req_type_t).
* @return 1, If the kind of constraint is present, 0 if not.
*/
#define arch_register_req_is(req, kind) \
* Expresses requirements to register allocation for an operand.
*/
struct arch_register_req_t {
- arch_register_req_type_t type; /**< The type of the constraint. */
- const arch_register_class_t *cls; /**< The register class this constraint belongs to. */
-
+ arch_register_req_type_t type; /**< The type of the constraint. */
+ const arch_register_class_t *cls; /**< The register class this constraint
+ belongs to. */
const unsigned *limited; /**< allowed register bitset */
-
unsigned other_same; /**< Bitmask of ins which should use the
same register (should_be_same). */
unsigned other_different; /**< Bitmask of ins which shall use a
different register
(must_be_different) */
+ unsigned char width; /**< specifies how many sequential
+ registers are required */
};
static inline int reg_reqs_equal(const arch_register_req_t *req1,
return 0;
n_regs = arch_register_class_n_regs(req1->cls);
- if (!rbitset_equal(req1->limited, req2->limited, n_regs))
+ if (!rbitsets_equal(req1->limited, req2->limited, n_regs))
return 0;
}
int n; /**< count of nodes returned in nodes array */
int costs; /**< costs of this remat */
- /**< nodes for this inverse operation. shall be in
- * schedule order. last element is the target value
- */
+ /** nodes for this inverse operation. shall be in schedule order.
+ * last element is the target value */
ir_node **nodes;
};
struct arch_irn_ops_t {
/**
- * Get the register requirements for a given operand.
+ * Get the register requirements for a given operand.
* @param irn The node.
* @param pos The operand's position
* @return The register requirements for the selected operand.
* The pointer returned is never NULL.
*/
- const arch_register_req_t *(*get_irn_reg_req_in)(const ir_node *irn, int pos);
-
- /**
- * Get the register requirements for values produced by a node
- * @param irn The node.
- * @param pos The operand's position (0 for most nodes,
- * 0..n for mode_T nodes)
- * @return The register requirements for the selected operand.
- * The pointer returned is never NULL.
- */
- const arch_register_req_t *(*get_irn_reg_req_out)(const ir_node *irn, int pos);
+ const arch_register_req_t *(*get_irn_reg_req_in)(const ir_node *irn,
+ int pos);
/**
* Classify the node.
/**
* Get the entity on the stack frame this node depends on.
* @param irn The node in question.
- * @return The entity on the stack frame or NULL, if the node does not have a
- * stack frame entity.
+ * @return The entity on the stack frame or NULL, if the node does not have
+ * a stack frame entity.
*/
ir_entity *(*get_frame_entity)(const ir_node *irn);
- /**
- * Set the entity on the stack frame this node depends on.
- * @param irn The node in question.
- * @param ent The entity to set
- */
- void (*set_frame_entity)(ir_node *irn, ir_entity *ent);
-
/**
* Set the offset of a node carrying an entity on the stack frame.
* @param irn The node.
* of the given node as result.
*
* @param irn The original operation
- * @param i Index of the argument we want the inverse operation to yield
+ * @param i Index of the argument we want the inverse operation to
+ * yield
* @param inverse struct to be filled with the resulting inverse op
- * @param obstack The obstack to use for allocation of the returned nodes array
+ * @param obstack The obstack to use for allocation of the returned nodes
+ * array
* @return The inverse operation or NULL if operation invertible
*/
- arch_inverse_t *(*get_inverse)(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obstack);
+ arch_inverse_t *(*get_inverse)(const ir_node *irn, int i,
+ arch_inverse_t *inverse,
+ struct obstack *obstack);
/**
* Get the estimated cycle count for @p irn.
*
* @param irn The node.
- *
* @return The estimated cycle count for this operation
*/
int (*get_op_estimated_cost)(const ir_node *irn);
/**
- * Asks the backend whether operand @p i of @p irn can be loaded form memory internally
+ * Asks the backend whether operand @p i of @p irn can be loaded form memory
+ * internally
*
* @param irn The node.
- * @param i Index of the argument we would like to know whether @p irn can load it form memory internally
- *
+ * @param i Index of the argument we would like to know whether @p irn
+ * can load it form memory internally
* @return nonzero if argument can be loaded or zero otherwise
*/
int (*possible_memory_operand)(const ir_node *irn, unsigned int i);
* @param spill The spill.
* @param i The position of the reload.
*/
- void (*perform_memory_operand)(ir_node *irn, ir_node *spill, unsigned int i);
+ void (*perform_memory_operand)(ir_node *irn, ir_node *spill,
+ unsigned int i);
};
/**
struct arch_code_generator_if_t {
/**
* Initialize the code generator.
- * @param birg A backend IRG session.
+ * @param irg A graph
* @return A newly created code generator.
*/
- void *(*init)(be_irg_t *birg);
+ void *(*init)(ir_graph *irg);
/**
* return node used as base in pic code addresses
* Backend may provide an own spiller.
* This spiller needs to spill all register classes.
*/
- void (*spill)(void *self, be_irg_t *birg);
+ void (*spill)(void *self, ir_graph *irg);
/**
* Called before register allocation.
#define arch_code_generator_after_ra(cg) _arch_cg_call(cg, after_ra)
#define arch_code_generator_finish(cg) _arch_cg_call(cg, finish)
#define arch_code_generator_done(cg) _arch_cg_call(cg, done)
-#define arch_code_generator_spill(cg, birg) _arch_cg_call_env(cg, birg, spill)
+#define arch_code_generator_spill(cg, irg) _arch_cg_call_env(cg, irg, spill)
#define arch_code_generator_has_spiller(cg) ((cg)->impl->spill != NULL)
#define arch_code_generator_get_pic_base(cg) \
((cg)->impl->get_pic_base != NULL ? (cg)->impl->get_pic_base(cg) : NULL)
const arch_register_class_t *(*get_reg_class)(unsigned i);
/**
- * Get the register class which shall be used to store a value of a given mode.
+ * Get the register class which shall be used to store a value of a given
+ * mode.
* @param self The this pointer.
* @param mode The mode in question.
* @return A register class which can hold values of the given mode.
* @param call_type The call type of the method (procedure) in question.
* @param p The array of parameter locations to be filled.
*/
- void (*get_call_abi)(const void *self, ir_type *call_type, be_abi_call_t *abi);
+ void (*get_call_abi)(const void *self, ir_type *call_type,
+ be_abi_call_t *abi);
/**
* Get the code generator interface.
* @param selector The selector given by options.
* @return The list scheduler selector.
*/
- const list_sched_selector_t *(*get_list_sched_selector)(const void *self, list_sched_selector_t *selector);
+ const list_sched_selector_t *(*get_list_sched_selector)(const void *self,
+ list_sched_selector_t *selector);
/**
* Get the ILP scheduler to use.
* NULL
* };
*/
- const be_execution_unit_t ***(*get_allowed_execution_units)(const ir_node *irn);
+ const be_execution_unit_t ***(*get_allowed_execution_units)(
+ const ir_node *irn);
/**
* Return the abstract machine for this isa.
* If NULL is returned, all irg will be taken into account and they will be
* generated in an arbitrary order.
* @param self The isa object.
- * @param irgs A flexible array ARR_F of length 0 where the backend can append the desired irgs.
- * @return A flexible array ARR_F containing all desired irgs in the desired order.
+ * @param irgs A flexible array ARR_F of length 0 where the backend can
+ * append the desired irgs.
+ * @return A flexible array ARR_F containing all desired irgs in the
+ * desired order.
*/
ir_graph **(*get_backend_irg_list)(const void *self, ir_graph ***irgs);
*/
struct arch_env_t {
const arch_isa_if_t *impl;
- const arch_register_t *sp; /** The stack pointer register. */
- const arch_register_t *bp; /** The base pointer register. */
- const arch_register_class_t *link_class; /** The static link pointer register class. */
- int stack_dir; /** -1 for decreasing, 1 for increasing. */
- int stack_alignment; /** power of 2 stack alignment */
- const be_main_env_t *main_env; /** the be main environment */
- int spill_cost; /** cost for a be_Spill node */
- int reload_cost; /** cost for a be_Reload node */
+ const arch_register_t *sp; /**< The stack pointer register. */
+ const arch_register_t *bp; /**< The base pointer register. */
+ const arch_register_class_t *link_class; /**< The static link pointer
+ register class. */
+ int stack_dir; /**< -1 for decreasing, 1 for
+ increasing. */
+ int stack_alignment; /**< power of 2 stack alignment */
+ const be_main_env_t *main_env; /**< the be main environment */
+ int spill_cost; /**< cost for a be_Spill node */
+ int reload_cost; /**< cost for a be_Reload node */
+ bool custom_abi : 1; /**< backend does all abi handling
+ and does not need the generic stuff
+ from beabi.h/.c */
};
static inline unsigned arch_irn_get_n_outs(const ir_node *node)
static inline const arch_register_req_t *arch_get_register_req_out(
const ir_node *irn)
{
- int pos = 0;
- const arch_irn_ops_t *ops;
+ int pos = 0;
+ backend_info_t *info;
+
+ /* you have to query the Proj nodes for the constraints (or use
+ * arch_get_out_register_req. Querying a mode_T node and expecting
+ * arch_no_register_req is a bug in your code! */
+ assert(get_irn_mode(irn) != mode_T);
if (is_Proj(irn)) {
pos = get_Proj_proj(irn);
irn = get_Proj_pred(irn);
- } else if (get_irn_mode(irn) == mode_T) {
- return arch_no_register_req;
}
- ops = get_irn_ops_simple(irn);
- return ops->get_irn_reg_req_out(irn, pos);
+
+ info = be_get_info(irn);
+ if (info->out_infos == NULL)
+ return arch_no_register_req;
+
+ return info->out_infos[pos].req;
}
static inline bool arch_irn_is_ignore(const ir_node *irn)
static inline const arch_register_req_t *arch_get_out_register_req(
const ir_node *node, int pos)
{
- const arch_irn_ops_t *ops = get_irn_ops_simple(node);
- return ops->get_irn_reg_req_out(node, pos);
+ const backend_info_t *info = be_get_info(node);
+ if (info->out_infos == NULL)
+ return arch_no_register_req;
+ return info->out_infos[pos].req;
}
-#endif /* FIRM_BE_BEARCH_H */
+static inline void arch_set_out_register_req(ir_node *node, int pos,
+ const arch_register_req_t *req)
+{
+ backend_info_t *info = be_get_info(node);
+ assert(pos < (int) arch_irn_get_n_outs(node));
+ info->out_infos[pos].req = req;
+}
+
+/**
+ * Iterate over all values defined by an instruction.
+ * Only looks at values in a certain register class where the requirements
+ * are not marked as ignore.
+ * Executes @p code for each definition.
+ */
+#define be_foreach_definition(node, cls, value, code) \
+ do { \
+ if (get_irn_mode(node) == mode_T) { \
+ const ir_edge_t *edge_; \
+ foreach_out_edge(node, edge_) { \
+ const arch_register_req_t *req_; \
+ value = get_edge_src_irn(edge_); \
+ req_ = arch_get_register_req_out(value); \
+ if (req_->cls != cls) \
+ continue; \
+ if (req_->type & arch_register_req_type_ignore) \
+ continue; \
+ code \
+ } \
+ } else { \
+ const arch_register_req_t *req_ = arch_get_register_req_out(node); \
+ value = node; \
+ if (req_->cls == cls \
+ && !(req_->type & arch_register_req_type_ignore)) { \
+ code \
+ } \
+ } \
+ } while (0)
+
+#endif
projects / libfirm / blobdiff