#include "bitset.h"
#include "debug.h"
+#include "array_t.h"
#include "irtools.h"
#include "../bearch_t.h" /* the general register allocator interface */
static ir_entity *arm_get_frame_entity(const ir_node *irn) {
/* we do NOT transform be_Spill or be_Reload nodes, so we never
have frame access using ARM nodes. */
+ (void) irn;
return NULL;
}
static void arm_set_frame_entity(ir_node *irn, ir_entity *ent) {
+ (void) irn;
+ (void) ent;
panic("arm_set_frame_entity() called. This should not happen.");
}
v = (v << 8) | get_tarval_sub_bits(tv, 1);
v = (v << 8) | get_tarval_sub_bits(tv, 0);
*resL = new_Const_long(mode_Is, v);
- }
- else if (get_irn_op(skip_Proj(arg)) == op_Load) {
+ } else if (is_Load(skip_Proj(arg))) {
/* FIXME: handling of low/high depends on LE/BE here */
- assert(0);
+ panic("Unimplemented convert_dbl_to_int() case");
}
else {
ir_graph *irg = current_ir_graph;
v = (v << 8) | get_tarval_sub_bits(tv, 1);
v = (v << 8) | get_tarval_sub_bits(tv, 0);
return new_Const_long(mode_Is, v);
- }
- else if (get_irn_op(skip_Proj(arg)) == op_Load) {
+ } else if (is_Load(skip_Proj(arg))) {
ir_node *load;
load = skip_Proj(arg);
}
- assert(0);
- return NULL;
+ panic("Unimplemented convert_sng_to_int() case");
}
/**
&arm_gp_regs[REG_SP], /* stack pointer */
&arm_gp_regs[REG_R11], /* base pointer */
-1, /* stack direction */
- 1, /* stack alignment for calls */
+ 2, /* power of two stack alignment for calls, 2^2 == 4 */
NULL, /* main environment */
7, /* spill costs */
5, /* reload costs */
static int inited = 0;
arm_isa_t *isa;
- if(inited)
+ if (inited)
return NULL;
isa = xmalloc(sizeof(*isa));
arm_create_opcodes(&arm_irn_ops);
arm_handle_intrinsics();
+ /* needed for the debug support */
+ be_gas_emit_switch_section(GAS_SECTION_TEXT);
+ be_emit_cstring(".Ltext0:\n");
+ be_emit_write_line();
+
/* we mark referenced global entities, so we can only emit those which
* are actually referenced. (Note: you mustn't use the type visited flag
* elsewhere in the backend)
return env;
}
+/**
+ * Put all registers which are saved by the prologue/epilogue in a set.
+ *
+ * @param self The callback object.
+ * @param s The result set.
+ */
static void arm_abi_dont_save_regs(void *self, pset *s)
{
arm_abi_env_t *env = self;
pset_insert_ptr(s, env->arch_env->bp);
}
-
-
/**
- * Build the ARM prolog
+ * Generate the routine prologue.
+ *
+ * @param self The callback object.
+ * @param mem A pointer to the mem node. Update this if you define new memory.
+ * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param stack_bias Points to the current stack bias, can be modified if needed.
+ *
+ * @return The register which shall be used as a stack frame base.
+ *
+ * All nodes which define registers in @p reg_map must keep @p reg_map current.
*/
-static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
- ir_node *keep, *store;
- arm_abi_env_t *env = self;
- ir_graph *irg = env->irg;
- ir_node *block = get_irg_start_block(irg);
- arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
+static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias) {
+ arm_abi_env_t *env = self;
+ ir_node *keep, *store;
+ ir_graph *irg;
+ ir_node *block;
+ arch_register_class_t *gp;
- ir_node *fp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
- ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
- ir_node *sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
- ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
- ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
+ ir_node *fp, *ip, *lr, *pc;
+ ir_node *sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
+
+ (void) stack_bias;
if (env->flags.try_omit_fp)
return env->arch_env->sp;
+ fp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
+ ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
+ lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
+ pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
+
+ gp = &arm_reg_classes[CLASS_arm_gp];
+ irg = env->irg;
+ block = get_irg_start_block(irg);
+
ip = be_new_Copy(gp, irg, block, sp);
arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), 4);
arch_set_irn_register(env->arch_env, fp, env->arch_env->bp);
+ fp = be_new_Copy(gp, irg, block, fp); // XXX Gammelfix: only be_ nodes can have the ignore flag set
+ arch_set_irn_register(env->arch_env, fp, env->arch_env->bp);
+ be_node_set_flags(fp, BE_OUT_POS(0), arch_irn_flags_ignore);
be_abi_reg_map_set(reg_map, env->arch_env->bp, fp);
be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
(void) self;
(void) irn;
/* TODO */
- assert(0);
- return NULL;
+ panic("Unimplemented arm_get_allowed_execution_units()");
}
static const be_machine_t *arm_get_machine(const void *self) {
(void) self;
/* TODO */
- assert(0);
- return NULL;
+ panic("Unimplemented arm_get_machine()");
}
/**
return 1;
}
+static asm_constraint_flags_t arm_parse_asm_constraint(const void *self, const char **c)
+{
+ /* asm not supported */
+ (void) self;
+ (void) c;
+ return ASM_CONSTRAINT_FLAG_INVALID;
+}
+
+static int arm_is_valid_clobber(const void *self, const char *clobber)
+{
+ (void) self;
+ (void) clobber;
+ return 0;
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
static backend_params p = {
1, /* need dword lowering */
0, /* don't support inline assembler yet */
+ 0, /* no immediate floating point mode. */
NULL, /* no additional opcodes */
NULL, /* will be set later */
NULL, /* but yet no creator function */
NULL, /* context for create_intrinsic_fkt */
NULL, /* will be set below */
+ NULL /* no immediate fp mode */
};
p.dep_param = &ad;
arm_get_allowed_execution_units,
arm_get_machine,
arm_get_irg_list,
+ NULL, /* mark remat */
+ arm_parse_asm_constraint,
+ arm_is_valid_clobber
};
void be_init_arch_arm(void)
projects / libfirm / blobdiff