/**
* @file
* @brief The main arm backend driver file.
- * @author Oliver Richter, Tobias Gneist
+ * @author Matthias Braun, Oliver Richter, Tobias Gneist
* @version $Id$
*/
#include "config.h"
#include "array_t.h"
#include "irtools.h"
-#include "../bearch_t.h" /* the general register allocator interface */
-#include "../benode_t.h"
+#include "../bearch.h"
+#include "../benode.h"
#include "../belower.h"
-#include "../besched_t.h"
+#include "../besched.h"
#include "be.h"
#include "../beabi.h"
#include "../bemachine.h"
#include "../beilpsched.h"
#include "../bemodule.h"
-#include "../beirg_t.h"
+#include "../beirg.h"
#include "../bespillslots.h"
#include "../begnuas.h"
+#include "../belistsched.h"
+#include "../beflags.h"
#include "bearch_arm_t.h"
-#include "arm_new_nodes.h" /* arm nodes interface */
-#include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
+#include "arm_new_nodes.h"
+#include "gen_arm_regalloc_if.h"
#include "arm_transform.h"
#include "arm_optimize.h"
#include "arm_emitter.h"
#include "arm_map_regs.h"
-#define DEBUG_MODULE "firm.be.arm.isa"
-
-/* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
-static set *cur_reg_set = NULL;
-
-/**************************************************
- * _ _ _ __
- * | | | (_)/ _|
- * _ __ ___ __ _ __ _| | | ___ ___ _| |_
- * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
- * | | | __/ (_| | | (_| | | | (_) | (__ | | |
- * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
- * __/ |
- * |___/
- **************************************************/
-
-/**
- * Return register requirements for a arm node.
- * If the node returns a tuple (mode_T) then the proj's
- * will be asked for this information.
- */
-static const arch_register_req_t *arm_get_irn_reg_req(const ir_node *node,
- int pos)
+static arch_irn_class_t arm_classify(const ir_node *irn)
{
- long node_pos = pos == -1 ? 0 : pos;
- ir_mode *mode = get_irn_mode(node);
-
- if (is_Block(node) || mode == mode_X) {
- return arch_no_register_req;
- }
-
- if (mode == mode_T && pos < 0) {
- return arch_no_register_req;
- }
-
- if (is_Proj(node)) {
- if(mode == mode_M)
- return arch_no_register_req;
-
- if(pos >= 0) {
- return arch_no_register_req;
- }
-
- node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
- node = skip_Proj_const(node);
- }
-
- /* get requirements for our own nodes */
- if (is_arm_irn(node)) {
- const arch_register_req_t *req;
- if (pos >= 0) {
- req = get_arm_in_req(node, pos);
- } else {
- req = get_arm_out_req(node, node_pos);
- }
-
- return req;
- }
-
- /* unknown should be transformed by now */
- assert(!is_Unknown(node));
- return arch_no_register_req;
+ (void) irn;
+ return 0;
}
-static arch_irn_class_t arm_classify(const ir_node *irn)
+static ir_entity *arm_get_frame_entity(const ir_node *irn)
{
- irn = skip_Proj_const(irn);
+ const arm_attr_t *attr = get_arm_attr_const(irn);
- if (is_cfop(irn)) {
- return arch_irn_class_branch;
+ if (is_arm_FrameAddr(irn)) {
+ const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
+ return attr->entity;
+ }
+ if (attr->is_load_store) {
+ const arm_load_store_attr_t *load_store_attr
+ = get_arm_load_store_attr_const(irn);
+ if (load_store_attr->is_frame_entity) {
+ return load_store_attr->entity;
+ }
}
-
- return 0;
-}
-
-static ir_entity *arm_get_frame_entity(const ir_node *irn) {
- /* we do NOT transform be_Spill or be_Reload nodes, so we never
- have frame access using ARM nodes. */
- (void) irn;
return NULL;
}
-static void arm_set_frame_entity(ir_node *irn, ir_entity *ent) {
+static void arm_set_frame_entity(ir_node *irn, ir_entity *ent)
+{
(void) irn;
(void) ent;
panic("arm_set_frame_entity() called. This should not happen.");
*/
static void arm_set_stack_bias(ir_node *irn, int bias)
{
- (void) irn;
- (void) bias;
- /* TODO: correct offset if irn accesses the stack */
+ if (is_arm_FrameAddr(irn)) {
+ arm_SymConst_attr_t *attr = get_irn_generic_attr(irn);
+ attr->fp_offset += bias;
+ } else {
+ arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
+ assert(attr->base.is_load_store);
+ attr->offset += bias;
+ }
}
static int arm_get_sp_bias(const ir_node *irn)
{
+ /* We don't have any nodes changing the stack pointer.
+ TODO: we probably want to support post-/pre increment/decrement later */
(void) irn;
return 0;
}
/* fill register allocator interface */
static const arch_irn_ops_t arm_irn_ops = {
- arm_get_irn_reg_req,
+ get_arm_in_req,
arm_classify,
arm_get_frame_entity,
arm_set_frame_entity,
NULL, /* perform_memory_operand */
};
-/**************************************************
- * _ _ __
- * | | (_)/ _|
- * ___ ___ __| | ___ __ _ ___ _ __ _| |_
- * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
- * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
- * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
- * __/ |
- * |___/
- **************************************************/
-
/**
* Transforms the standard Firm graph into
* a ARM firm graph.
*/
-static void arm_prepare_graph(void *self) {
+static void arm_prepare_graph(void *self)
+{
arm_code_gen_t *cg = self;
/* transform nodes into assembler instructions */
arm_peephole_optimization(cg);
}
+static ir_node *arm_flags_remat(ir_node *node, ir_node *after)
+{
+ ir_node *block;
+ ir_node *copy;
+
+ if (is_Block(after)) {
+ block = after;
+ } else {
+ block = get_nodes_block(after);
+ }
+ copy = exact_copy(node);
+ set_nodes_block(copy, block);
+ sched_add_after(after, copy);
+ return copy;
+}
static void arm_before_ra(void *self)
{
- (void) self;
- /* Some stuff you need to do immediately after register allocation */
+ arm_code_gen_t *cg = self;
+
+ be_sched_fix_flags(cg->birg, &arm_reg_classes[CLASS_arm_flags],
+ &arm_flags_remat);
+}
+
+static void transform_Reload(ir_node *node)
+{
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *block = get_nodes_block(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *ptr = get_irg_frame(irg);
+ ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
+ ir_mode *mode = get_irn_mode(node);
+ ir_entity *entity = be_get_frame_entity(node);
+ const arch_register_t *reg;
+ ir_node *proj;
+ ir_node *load;
+
+ ir_node *sched_point = sched_prev(node);
+
+ load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
+ sched_add_after(sched_point, load);
+ sched_remove(node);
+
+ proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
+
+ reg = arch_get_irn_register(node);
+ arch_set_irn_register(proj, reg);
+
+ exchange(node, proj);
+}
+
+static void transform_Spill(ir_node *node)
+{
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *block = get_nodes_block(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *ptr = get_irg_frame(irg);
+ ir_node *mem = new_NoMem();
+ ir_node *val = get_irn_n(node, be_pos_Spill_val);
+ ir_mode *mode = get_irn_mode(val);
+ ir_entity *entity = be_get_frame_entity(node);
+ ir_node *sched_point;
+ ir_node *store;
+
+ sched_point = sched_prev(node);
+ store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
+ true);
+
+ sched_remove(node);
+ sched_add_after(sched_point, store);
+
+ exchange(node, store);
+}
+
+static void arm_after_ra_walker(ir_node *block, void *data)
+{
+ ir_node *node, *prev;
+ (void) data;
+
+ for (node = sched_last(block); !sched_is_begin(node); node = prev) {
+ prev = sched_prev(node);
+
+ if (be_is_Reload(node)) {
+ transform_Reload(node);
+ } else if (be_is_Spill(node)) {
+ transform_Spill(node);
+ }
+ }
}
-/**
- * We transform Spill and Reload here. This needs to be done before
- * stack biasing otherwise we would miss the corrected offset for these nodes.
- */
static void arm_after_ra(void *self)
{
arm_code_gen_t *cg = self;
be_coalesce_spillslots(cg->birg);
+
+ irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL);
}
/**
* Emits the code, closes the output file and frees
* the code generator interface.
*/
-static void arm_emit_and_done(void *self) {
+static void arm_emit_and_done(void *self)
+{
arm_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
arm_gen_routine(cg, irg);
- cur_reg_set = NULL;
-
/* de-allocate code generator */
del_set(cg->reg_set);
free(self);
* 2.) A load: simply split into two
*/
static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
- ir_node **resH, ir_node **resL) {
+ ir_node **resH, ir_node **resL)
+{
if (is_Const(arg)) {
tarval *tv = get_Const_tarval(arg);
unsigned v;
panic("Unimplemented convert_dbl_to_int() case");
}
else {
- ir_graph *irg = current_ir_graph;
ir_node *conv;
conv = new_bd_arm_fpaDbl2GP(NULL, bl, arg, mem);
/* move high/low */
- *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
- *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
- mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
+ *resL = new_r_Proj(conv, mode_Is, pn_arm_fpaDbl2GP_low);
+ *resH = new_r_Proj(conv, mode_Is, pn_arm_fpaDbl2GP_high);
+ mem = new_r_Proj(conv, mode_M, pn_arm_fpaDbl2GP_M);
}
return mem;
}
v = (v << 8) | get_tarval_sub_bits(tv, 1);
v = (v << 8) | get_tarval_sub_bits(tv, 0);
return new_Const_long(mode_Is, v);
- } else if (is_Load(skip_Proj(arg))) {
- ir_node *load;
-
- load = skip_Proj(arg);
}
panic("Unimplemented convert_sng_to_int() case");
}
n = i;
n_param = get_method_n_params(mtp) - n + idx;
n_res = get_method_n_ress(mtp);
- new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
+ new_mtd = new_d_type_method(n_param, n_res, get_type_dbg_info(mtp));
for (i = 0; i < idx; ++i)
set_method_param_type(new_mtd, i, new_tp[i]);
/**
* Handle graph transformations before the abi converter does its work.
*/
-static void arm_before_abi(void *self) {
+static void arm_before_abi(void *self)
+{
arm_code_gen_t *cg = self;
irg_walk_graph(cg->irg, NULL, handle_calls, cg);
/**
* Initializes the code generator.
*/
-static void *arm_cg_init(be_irg_t *birg) {
+static void *arm_cg_init(be_irg_t *birg)
+{
static ir_type *int_tp = NULL;
arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env;
arm_code_gen_t *cg;
if (! int_tp) {
/* create an integer type with machine size */
- int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
+ int_tp = new_type_primitive(mode_Is);
}
cg = XMALLOC(arm_code_gen_t);
cg->birg = birg;
cg->int_tp = int_tp;
cg->have_fp_insn = 0;
- cg->unknown_gp = NULL;
- cg->unknown_fpa = NULL;
cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
- cur_reg_set = cg->reg_set;
-
/* enter the current code generator */
isa->cg = cg;
* and map all instructions the backend did not support
* to runtime calls.
*/
-static void arm_handle_intrinsics(void) {
+static void arm_handle_intrinsics(void)
+{
ir_type *tp, *int_tp, *uint_tp;
i_record records[8];
int n_records = 0;
#define ID(x) new_id_from_chars(x, sizeof(x)-1)
- int_tp = new_type_primitive(ID("int"), mode_Is);
- uint_tp = new_type_primitive(ID("uint"), mode_Iu);
+ int_tp = new_type_primitive(mode_Is);
+ uint_tp = new_type_primitive(mode_Iu);
/* ARM has neither a signed div instruction ... */
{
i_instr_record *map_Div = &records[n_records++].i_instr;
- tp = new_type_method(ID("rt_iDiv"), 2, 1);
+ tp = new_type_method(2, 1);
set_method_param_type(tp, 0, int_tp);
set_method_param_type(tp, 1, int_tp);
set_method_res_type(tp, 0, int_tp);
rt_iDiv.exc_mem_proj_nr = pn_Div_M;
rt_iDiv.res_proj_nr = pn_Div_res;
- set_entity_visibility(rt_iDiv.ent, visibility_external_allocated);
+ add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT);
+ set_entity_visibility(rt_iDiv.ent, ir_visibility_external);
map_Div->kind = INTRINSIC_INSTR;
map_Div->op = op_Div;
{
i_instr_record *map_Div = &records[n_records++].i_instr;
- tp = new_type_method(ID("rt_uDiv"), 2, 1);
+ tp = new_type_method(2, 1);
set_method_param_type(tp, 0, uint_tp);
set_method_param_type(tp, 1, uint_tp);
set_method_res_type(tp, 0, uint_tp);
rt_uDiv.exc_mem_proj_nr = pn_Div_M;
rt_uDiv.res_proj_nr = pn_Div_res;
- set_entity_visibility(rt_uDiv.ent, visibility_external_allocated);
+ set_entity_visibility(rt_uDiv.ent, ir_visibility_external);
map_Div->kind = INTRINSIC_INSTR;
map_Div->op = op_Div;
{
i_instr_record *map_Mod = &records[n_records++].i_instr;
- tp = new_type_method(ID("rt_iMod"), 2, 1);
+ tp = new_type_method(2, 1);
set_method_param_type(tp, 0, int_tp);
set_method_param_type(tp, 1, int_tp);
set_method_res_type(tp, 0, int_tp);
rt_iMod.exc_mem_proj_nr = pn_Mod_M;
rt_iMod.res_proj_nr = pn_Mod_res;
- set_entity_visibility(rt_iMod.ent, visibility_external_allocated);
+ set_entity_visibility(rt_iMod.ent, ir_visibility_external);
map_Mod->kind = INTRINSIC_INSTR;
map_Mod->op = op_Mod;
{
i_instr_record *map_Mod = &records[n_records++].i_instr;
- tp = new_type_method(ID("rt_uMod"), 2, 1);
+ tp = new_type_method(2, 1);
set_method_param_type(tp, 0, uint_tp);
set_method_param_type(tp, 1, uint_tp);
set_method_res_type(tp, 0, uint_tp);
rt_uMod.exc_mem_proj_nr = pn_Mod_M;
rt_uMod.res_proj_nr = pn_Mod_res;
- set_entity_visibility(rt_uMod.ent, visibility_external_allocated);
+ set_entity_visibility(rt_uMod.ent, ir_visibility_external);
map_Mod->kind = INTRINSIC_INSTR;
map_Mod->op = op_Mod;
&arm_isa_if, /* isa interface */
&arm_gp_regs[REG_SP], /* stack pointer */
&arm_gp_regs[REG_R11], /* base pointer */
+ &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
-1, /* stack direction */
2, /* power of two stack alignment for calls, 2^2 == 4 */
NULL, /* main environment */
/**
* Initializes the backend ISA and opens the output file.
*/
-static arch_env_t *arm_init(FILE *file_handle) {
+static arch_env_t *arm_init(FILE *file_handle)
+{
static int inited = 0;
arm_isa_t *isa;
arm_create_opcodes(&arm_irn_ops);
arm_handle_intrinsics();
+ be_gas_emit_types = false;
+
/* needed for the debug support */
be_gas_emit_switch_section(GAS_SECTION_TEXT);
- be_emit_cstring(".Ltext0:\n");
+ be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
be_emit_write_line();
- /* we mark referenced global entities, so we can only emit those which
- * are actually referenced. (Note: you mustn't use the type visited flag
- * elsewhere in the backend)
- */
- inc_master_type_visited();
-
inited = 1;
return &isa->arch_env;
}
/**
* Closes the output file and frees the ISA structure.
*/
-static void arm_done(void *self) {
+static void arm_done(void *self)
+{
arm_isa_t *isa = self;
- be_gas_emit_decls(isa->arch_env.main_env, 1);
+ be_gas_emit_decls(isa->arch_env.main_env);
be_emit_exit();
free(self);
* here to speed up register allocation (and makes dumps
* smaller and more readable).
*/
-static unsigned arm_get_n_reg_class(const void *self) {
- (void) self;
+static unsigned arm_get_n_reg_class(void)
+{
return N_CLASSES;
}
/**
* Return the register class with requested index.
*/
-static const arch_register_class_t *arm_get_reg_class(const void *self,
- unsigned i) {
- (void) self;
+static const arch_register_class_t *arm_get_reg_class(unsigned i)
+{
assert(i < N_CLASSES);
return &arm_reg_classes[i];
}
* @param mode The mode in question.
* @return A register class which can hold values of the given mode.
*/
-const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
- (void) self;
+static const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode)
+{
if (mode_is_float(mode))
return &arm_reg_classes[CLASS_arm_fpa];
else
* it will contain the return address and space to store the old base pointer.
* @return The Firm type modeling the ABI between type.
*/
-static ir_type *arm_get_between_type(void *self) {
+static ir_type *arm_get_between_type(void *self)
+{
static ir_type *between_type = NULL;
- static ir_entity *old_bp_ent = NULL;
(void) self;
if (between_type == NULL) {
- ir_entity *ret_addr_ent;
- ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
- ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
-
- between_type = new_type_class(new_id_from_str("arm_between_type"));
- old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
- ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
-
- set_entity_offset(old_bp_ent, 0);
- set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
- set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
+ between_type = new_type_class(new_id_from_str("arm_between_type"));
+ set_type_size_bytes(between_type, 0);
}
return between_type;
*
* All nodes which define registers in @p reg_map must keep @p reg_map current.
*/
-static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias) {
+static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
+{
arm_abi_env_t *env = self;
- ir_node *keep, *store;
+ ir_node *store;
ir_graph *irg;
ir_node *block;
arch_register_class_t *gp;
irg = env->irg;
block = get_irg_start_block(irg);
- ip = be_new_Copy(gp, irg, block, sp);
- be_set_constr_single_reg_out(ip, 0, &arm_gp_regs[REG_R12], arch_register_req_type_produces_sp);
+ /* mark bp register as ignore */
+ be_set_constr_single_reg_out(get_Proj_pred(fp),
+ get_Proj_proj(fp), env->arch_env->bp,
+ arch_register_req_type_ignore);
+ /* copy SP to IP (so we can spill it */
+ ip = be_new_Copy(gp, block, sp);
+ be_set_constr_single_reg_out(ip, 0, &arm_gp_regs[REG_R12], 0);
+
+ /* spill stuff */
store = new_bd_arm_StoreStackM4Inc(NULL, block, sp, fp, ip, lr, pc, *mem);
- sp = new_r_Proj(irg, block, store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
+ sp = new_r_Proj(store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
arch_set_irn_register(sp, env->arch_env->sp);
- *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
+ *mem = new_r_Proj(store, mode_M, pn_arm_StoreStackM4Inc_M);
+
+ /* frame pointer is ip-4 (because ip is our old sp value) */
+ fp = new_bd_arm_Sub_imm(NULL, block, ip, 4, 0);
+ arch_set_irn_register(fp, env->arch_env->bp);
- keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
- be_node_set_reg_class_in(keep, 1, gp);
- be_set_constr_single_reg_out(keep, 0, &arm_gp_regs[REG_R12], arch_register_req_type_produces_sp);
+ /* beware: we change the fp but the StoreStackM4Inc above wants the old
+ * fp value. We are not allowed to spill or anything in the prolog, so we
+ * have to enforce some order here. (scheduler/regalloc are too stupid
+ * to extract this order from register requirements) */
+ add_irn_dep(fp, store);
- fp = new_bd_arm_Sub_i(NULL, block, keep, get_irn_mode(fp), 4);
+ fp = be_new_Copy(gp, block, fp); // XXX Gammelfix: only be_ have custom register requirements
+ be_set_constr_single_reg_out(fp, 0, env->arch_env->bp,
+ arch_register_req_type_ignore);
arch_set_irn_register(fp, env->arch_env->bp);
- fp = be_new_Copy(gp, irg, block, fp); // XXX Gammelfix: only be_ have custom register requirements
- be_set_constr_single_reg_out(fp, 0, env->arch_env->bp, 0);
be_abi_reg_map_set(reg_map, env->arch_env->bp, fp);
- be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
+ be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], ip);
be_abi_reg_map_set(reg_map, env->arch_env->sp, sp);
be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
/**
* Builds the ARM epilogue
*/
-static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
+static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
+{
arm_abi_env_t *env = self;
ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
// TODO: Activate Omit fp in epilogue
if (env->flags.try_omit_fp) {
- curr_sp = be_new_IncSP(env->arch_env->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
-
- curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
- be_set_constr_single_reg_out(curr_lr, 0, &arm_gp_regs[REG_LR], 0);
-
- curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
- be_set_constr_single_reg_out(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC], 0);
+ ir_node *incsp = be_new_IncSP(env->arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
+ curr_sp = incsp;
} else {
- ir_node *sub12_node;
ir_node *load_node;
- sub12_node = new_bd_arm_Sub_i(NULL, bl, curr_bp, mode_Iu, 12);
- // FIXME
- //set_arm_req_out_all(sub12_node, sub12_req);
- arch_set_irn_register(sub12_node, env->arch_env->sp);
- load_node = new_bd_arm_LoadStackM3(NULL, bl, sub12_node, *mem);
- // FIXME
- //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
- //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
- //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
- curr_bp = new_r_Proj(env->irg, bl, load_node, env->arch_env->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
- curr_sp = new_r_Proj(env->irg, bl, load_node, env->arch_env->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
- curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
- *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
+
+ load_node = new_bd_arm_LoadStackM3Epilogue(NULL, bl, curr_bp, *mem);
+
+ curr_bp = new_r_Proj(load_node, env->arch_env->bp->reg_class->mode, pn_arm_LoadStackM3Epilogue_res0);
+ curr_sp = new_r_Proj(load_node, env->arch_env->sp->reg_class->mode, pn_arm_LoadStackM3Epilogue_res1);
+ curr_pc = new_r_Proj(load_node, mode_Iu, pn_arm_LoadStackM3Epilogue_res2);
+ *mem = new_r_Proj(load_node, mode_M, pn_arm_LoadStackM3Epilogue_M);
arch_set_irn_register(curr_bp, env->arch_env->bp);
arch_set_irn_register(curr_sp, env->arch_env->sp);
arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
* @param method_type The type of the method (procedure) in question.
* @param abi The abi object to be modified
*/
-void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
+static void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi)
+{
ir_type *tp;
ir_mode *mode;
int i;
/* reg = get reg for param i; */
/* be_abi_call_param_reg(abi, i, reg); */
if (i < 4) {
- be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
+ be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i), ABI_CONTEXT_BOTH);
} else {
tp = get_method_param_type(method_type, i);
mode = get_type_mode(tp);
- be_abi_call_param_stack(abi, i, mode, 4, 0, 0);
+ be_abi_call_param_stack(abi, i, mode, 4, 0, 0, ABI_CONTEXT_BOTH);
}
}
assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
- be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]);
- be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]);
+ be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0], ABI_CONTEXT_BOTH);
+ be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1], ABI_CONTEXT_BOTH);
} else if (n == 1) {
const arch_register_t *reg;
mode = get_type_mode(tp);
reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0];
- be_abi_call_res_reg(abi, 0, reg);
+ be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
}
}
-int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
+static int arm_to_appear_in_schedule(void *block_env, const ir_node *irn)
+{
(void) block_env;
- if(!is_arm_irn(irn))
+ if (!is_arm_irn(irn))
return -1;
return 1;
/**
* Initializes the code generator interface.
*/
-static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
+static const arch_code_generator_if_t *arm_get_code_generator_if(void *self)
+{
(void) self;
return &arm_code_gen_if;
}
/**
* Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
*/
-static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
+static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector)
+{
(void) self;
memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
/* arm_sched_selector.exectime = arm_sched_exectime; */
}
-static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
+static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self)
+{
(void) self;
return NULL;
}
/**
* Returns the necessary byte alignment for storing a register of given class.
*/
-static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
- (void) self;
+static int arm_get_reg_class_alignment(const arch_register_class_t *cls)
+{
(void) cls;
/* ARM is a 32 bit CPU, no need for other alignment */
return 4;
}
-static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
- (void) self;
+static const be_execution_unit_t ***arm_get_allowed_execution_units(const ir_node *irn)
+{
(void) irn;
/* TODO */
panic("Unimplemented arm_get_allowed_execution_units()");
}
-static const be_machine_t *arm_get_machine(const void *self) {
+static const be_machine_t *arm_get_machine(const void *self)
+{
(void) self;
/* TODO */
panic("Unimplemented arm_get_machine()");
/**
* Return irp irgs in the desired order.
*/
-static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
+static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list)
+{
(void) self;
(void) irg_list;
return NULL;
* Allows or disallows the creation of Psi nodes for the given Phi nodes.
* @return 1 if allowed, 0 otherwise
*/
-static int arm_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) {
- ir_node *cmp, *cmp_a, *phi;
- ir_mode *mode;
-
+static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false,
+ ir_node *mux_true)
+{
+ (void) sel;
+ (void) mux_false;
+ (void) mux_true;
- /* currently Psi support is not implemented */
return 0;
-
-/* we don't want long long Psi */
-#define IS_BAD_PSI_MODE(mode) (!mode_is_float(mode) && get_mode_size_bits(mode) > 32)
-
- if (get_irn_mode(sel) != mode_b)
- return 0;
-
- cmp = get_Proj_pred(sel);
- cmp_a = get_Cmp_left(cmp);
- mode = get_irn_mode(cmp_a);
-
- if (IS_BAD_PSI_MODE(mode))
- return 0;
-
- /* check the Phi nodes */
- for (phi = phi_list; phi; phi = get_irn_link(phi)) {
- ir_node *pred_i = get_irn_n(phi, i);
- ir_node *pred_j = get_irn_n(phi, j);
- ir_mode *mode_i = get_irn_mode(pred_i);
- ir_mode *mode_j = get_irn_mode(pred_j);
-
- if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
- return 0;
- }
-
-#undef IS_BAD_PSI_MODE
-
- return 1;
}
-static asm_constraint_flags_t arm_parse_asm_constraint(const void *self, const char **c)
+static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
{
/* asm not supported */
- (void) self;
(void) c;
return ASM_CONSTRAINT_FLAG_INVALID;
}
-static int arm_is_valid_clobber(const void *self, const char *clobber)
+static int arm_is_valid_clobber(const char *clobber)
{
- (void) self;
(void) clobber;
return 0;
}
/**
* Returns the libFirm configuration parameter for this backend.
*/
-static const backend_params *arm_get_libfirm_params(void) {
+static const backend_params *arm_get_libfirm_params(void)
+{
static const ir_settings_if_conv_t ifconv = {
4, /* maxdepth, doesn't matter for Psi-conversion */
- arm_is_psi_allowed /* allows or disallows Psi creation for given selector */
+ arm_is_mux_allowed /* allows or disallows Mux creation for given selector */
};
static ir_settings_arch_dep_t ad = {
1, /* allow subs */
static backend_params p = {
1, /* need dword lowering */
0, /* don't support inline assembler yet */
- 0, /* no immediate floating point mode. */
- NULL, /* no additional opcodes */
NULL, /* will be set later */
NULL, /* but yet no creator function */
NULL, /* context for create_intrinsic_fkt */
- NULL, /* will be set below */
- NULL /* no immediate fp mode */
+ NULL, /* ifconv_info will be set below */
+ NULL, /* float arithmetic mode (TODO) */
+ 0, /* no trampoline support: size 0 */
+ 0, /* no trampoline support: align 0 */
+ NULL, /* no trampoline support: no trampoline builder */
+ 4 /* alignment of stack parameter */
};
p.dep_param = &ad;
arm_is_valid_clobber
};
+BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
void be_init_arch_arm(void)
{
lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
arm_init_transform();
arm_init_emitter();
}
-
-BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
projects / libfirm / blobdiff