/* fill register allocator interface */
static const arch_irn_ops_t arm_irn_ops = {
- get_arm_in_req,
arm_classify,
arm_get_frame_entity,
arm_set_stack_bias,
* Transforms the standard Firm graph into
* a ARM firm graph.
*/
-static void arm_prepare_graph(void *self)
+static void arm_prepare_graph(ir_graph *irg)
{
- arm_code_gen_t *cg = self;
-
/* transform nodes into assembler instructions */
- arm_transform_graph(cg);
+ arm_transform_graph(irg);
/* do local optimizations (mainly CSE) */
- local_optimize_graph(cg->irg);
-
- if (cg->dump)
- dump_ir_graph(cg->irg, "transformed");
+ local_optimize_graph(irg);
/* do code placement, to optimize the position of constants */
- place_code(cg->irg);
-
- if (cg->dump)
- dump_ir_graph(cg->irg, "place");
+ place_code(irg);
}
/**
* Called immediately before emit phase.
*/
-static void arm_finish_irg(void *self)
+static void arm_finish_irg(ir_graph *irg)
{
- arm_code_gen_t *cg = self;
-
/* do peephole optimizations and fix stack offsets */
- arm_peephole_optimization(cg);
+ arm_peephole_optimization(irg);
}
-static void arm_before_ra(void *self)
+static void arm_before_ra(ir_graph *irg)
{
- arm_code_gen_t *cg = self;
-
- be_sched_fix_flags(cg->irg, &arm_reg_classes[CLASS_arm_flags],
- NULL, NULL);
+ be_sched_fix_flags(irg, &arm_reg_classes[CLASS_arm_flags], NULL, NULL);
}
static void transform_Reload(ir_node *node)
}
}
-static void arm_after_ra(void *self)
+static void arm_after_ra(ir_graph *irg)
{
- arm_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
-
be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env);
be_assign_entities(fec_env, arm_set_frame_entity);
be_free_frame_entity_coalescer(fec_env);
- irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL);
-}
-
-/**
- * Emits the code, closes the output file and frees
- * the code generator interface.
- */
-static void arm_emit_and_done(void *self)
-{
- arm_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
-
- arm_gen_routine(cg, irg);
-
- /* de-allocate code generator */
- free(self);
+ irg_block_walk_graph(irg, NULL, arm_after_ra_walker, NULL);
}
-/* forward */
-static void *arm_cg_init(ir_graph *irg);
-
-static const arch_code_generator_if_t arm_code_gen_if = {
- arm_cg_init,
- NULL, /* get_pic_base */
- NULL, /* before abi introduce */
- arm_prepare_graph,
- NULL, /* spill */
- arm_before_ra, /* before register allocation hook */
- arm_after_ra,
- arm_finish_irg,
- arm_emit_and_done,
-};
-
/**
* Initializes the code generator.
*/
-static void *arm_cg_init(ir_graph *irg)
+static void arm_init_graph(ir_graph *irg)
{
- arm_isa_t *isa = (arm_isa_t*) be_get_irg_arch_env(irg);
- arm_code_gen_t *cg;
-
- cg = XMALLOCZ(arm_code_gen_t);
- cg->impl = &arm_code_gen_if;
- cg->irg = irg;
- cg->isa = isa;
- cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
-
- /* enter the current code generator */
- isa->cg = cg;
-
- return (arch_code_generator_t *)cg;
+ (void) irg;
}
true, /* we do have custom abi handling */
},
ARM_FPU_ARCH_FPE, /* FPU architecture */
- NULL, /* current code generator */
};
/**
arm_register_init();
- isa->cg = NULL;
be_emit_init(file_handle);
arm_create_opcodes(&arm_irn_ops);
return 1;
}
-/**
- * Initializes the code generator interface.
- */
-static const arch_code_generator_if_t *arm_get_code_generator_if(void *self)
-{
- (void) self;
- return &arm_code_gen_if;
-}
-
list_sched_selector_t arm_sched_selector;
/**
return 0;
}
+static void arm_lower_for_target(void)
+{
+ int i;
+ int n_irgs = get_irp_n_irgs();
+
+ for (i = 0; i < n_irgs; ++i) {
+ ir_graph *irg = get_irp_irg(i);
+ lower_switch(irg, 256, true);
+ }
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
static const backend_params *arm_get_libfirm_params(void)
{
- static const ir_settings_if_conv_t ifconv = {
- 4, /* maxdepth, doesn't matter for Psi-conversion */
- arm_is_mux_allowed /* allows or disallows Mux creation for given selector */
- };
static ir_settings_arch_dep_t ad = {
1, /* allow subs */
1, /* Muls are fast enough on ARM but ... */
32, /* SMUL & UMUL available for 32 bit */
};
static backend_params p = {
- 1, /* need dword lowering */
0, /* don't support inline assembler yet */
- NULL, /* will be set later */
- NULL, /* but yet no creator function */
- NULL, /* context for create_intrinsic_fkt */
- NULL, /* ifconv_info will be set below */
+ 1, /* support Rotl nodes */
+ 1, /* big endian */
+ arm_lower_for_target, /* lowering function */
+ &ad, /* will be set later */
+ arm_is_mux_allowed, /* allow_ifconv function */
NULL, /* float arithmetic mode (TODO) */
0, /* no trampoline support: size 0 */
0, /* no trampoline support: align 0 */
4 /* alignment of stack parameter */
};
- p.dep_param = &ad;
- p.if_conv_info = &ifconv;
return &p;
}
arm_get_reg_class,
arm_get_reg_class_for_mode,
NULL,
- arm_get_code_generator_if,
arm_get_list_sched_selector,
arm_get_ilp_sched_selector,
arm_get_reg_class_alignment,
arm_get_irg_list,
NULL, /* mark remat */
arm_parse_asm_constraint,
- arm_is_valid_clobber
+ arm_is_valid_clobber,
+
+ arm_init_graph,
+ NULL, /* get_pic_base */
+ NULL, /* before_abi */
+ arm_prepare_graph,
+ arm_before_ra,
+ arm_after_ra,
+ arm_finish_irg,
+ arm_gen_routine,
};
BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
projects / libfirm / blobdiff