-/* The main arm backend driver file. */
-/* $Id$ */
+/*
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
-#ifdef HAVE_CONFIG_H
+/**
+ * @file
+ * @brief The main arm backend driver file.
+ * @author Matthias Braun, Oliver Richter, Tobias Gneist
+ * @version $Id$
+ */
#include "config.h"
-#endif
-#include "pseudo_irg.h"
+#include "lc_opts.h"
+#include "lc_opts_enum.h"
+
#include "irgwalk.h"
#include "irprog.h"
#include "irprintf.h"
#include "ircons.h"
#include "irgmod.h"
-#include "lower_intrinsics.h"
+#include "irgopt.h"
+#include "iroptimize.h"
+#include "irdump.h"
+#include "lowering.h"
+#include "error.h"
#include "bitset.h"
#include "debug.h"
+#include "array_t.h"
+#include "irtools.h"
-#include "../bearch.h" /* the general register allocator interface */
-#include "../benode_t.h"
+#include "../bearch.h"
+#include "../benode.h"
#include "../belower.h"
-#include "../besched_t.h"
-#include "../be.h"
-#include "../beabi.h"
+#include "../besched.h"
+#include "be.h"
+#include "../bemachine.h"
+#include "../beilpsched.h"
+#include "../bemodule.h"
+#include "../beirg.h"
+#include "../bespillslots.h"
+#include "../begnuas.h"
+#include "../belistsched.h"
+#include "../beflags.h"
#include "bearch_arm_t.h"
-#include "arm_new_nodes.h" /* arm nodes interface */
-#include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
-#include "arm_gen_decls.h" /* interface declaration emitter */
+#include "arm_new_nodes.h"
+#include "gen_arm_regalloc_if.h"
#include "arm_transform.h"
+#include "arm_optimize.h"
#include "arm_emitter.h"
#include "arm_map_regs.h"
-#define DEBUG_MODULE "firm.be.arm.isa"
-
-/* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
-static set *cur_reg_set = NULL;
-
-/**************************************************
- * _ _ _ __
- * | | | (_)/ _|
- * _ __ ___ __ _ __ _| | | ___ ___ _| |_
- * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
- * | | | __/ (_| | | (_| | | | (_) | (__ | | |
- * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
- * __/ |
- * |___/
- **************************************************/
-
-static ir_node *my_skip_proj(const ir_node *n) {
- while (is_Proj(n))
- n = get_Proj_pred(n);
- return (ir_node *)n;
-}
-
-/**
- * Return register requirements for a arm node.
- * If the node returns a tuple (mode_T) then the proj's
- * will be asked for this information.
- */
-static const arch_register_req_t *arm_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
- const arm_register_req_t *irn_req;
- long node_pos = pos == -1 ? 0 : pos;
- ir_mode *mode = get_irn_mode(irn);
- FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
-
- if (is_Block(irn) || mode == mode_X || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
- return NULL;
- }
-
- if (mode == mode_T && pos < 0) {
- DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
- return NULL;
- }
-
- DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
-
- if (is_Proj(irn)) {
- /* in case of a proj, we need to get the correct OUT slot */
- /* of the node corresponding to the proj number */
- if (pos == -1) {
- node_pos = arm_translate_proj_pos(irn);
- }
- else {
- node_pos = pos;
- }
-
- irn = my_skip_proj(irn);
-
- DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
- }
-
- /* get requirements for our own nodes */
- if (is_arm_irn(irn)) {
- if (pos >= 0) {
- irn_req = get_arm_in_req(irn, pos);
- }
- else {
- irn_req = get_arm_out_req(irn, node_pos);
- }
-
- DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
-
- memcpy(req, &(irn_req->req), sizeof(*req));
-
- if (arch_register_req_is(&(irn_req->req), should_be_same)) {
- assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
- req->other_same = get_irn_n(irn, irn_req->same_pos);
- }
-
- if (arch_register_req_is(&(irn_req->req), should_be_different)) {
- assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
- req->other_different = get_irn_n(irn, irn_req->different_pos);
- }
- }
- /* get requirements for FIRM nodes */
- else {
- /* treat Phi like Const with default requirements */
- if (is_Phi(irn)) {
- DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
-
- if (mode_is_float(mode)) {
- memcpy(req, &(arm_default_req_arm_floating_point.req), sizeof(*req));
- }
- else if (mode_is_int(mode) || mode_is_reference(mode)) {
- memcpy(req, &(arm_default_req_arm_general_purpose.req), sizeof(*req));
- }
- else if (mode == mode_T || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
- return NULL;
- }
- else {
- assert(0 && "unsupported Phi-Mode");
- }
- }
- else {
- DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
- req = NULL;
- }
- }
-
- return req;
-}
-
-static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
- int pos = 0;
-
- if (is_Proj(irn)) {
-
- if (get_irn_mode(irn) == mode_X) {
- return;
- }
-
- pos = arm_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
- }
-
- if (is_arm_irn(irn)) {
- const arch_register_t **slots;
-
- slots = get_arm_slots(irn);
- slots[pos] = reg;
- }
- else {
- /* here we set the registers for the Phi nodes */
- arm_set_firm_reg(irn, reg, cur_reg_set);
- }
-}
-
-static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
- int pos = 0;
- const arch_register_t *reg = NULL;
-
- if (is_Proj(irn)) {
-
- if (get_irn_mode(irn) == mode_X) {
- return NULL;
- }
-
- pos = arm_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
- }
-
- if (is_arm_irn(irn)) {
- const arch_register_t **slots;
- slots = get_arm_slots(irn);
- reg = slots[pos];
- }
- else {
- reg = arm_get_firm_reg(irn, cur_reg_set);
- }
-
- return reg;
-}
-
-static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
- irn = my_skip_proj(irn);
-
- if (is_cfop(irn)) {
- return arch_irn_class_branch;
- }
- else if (is_arm_irn(irn)) {
- return arch_irn_class_normal;
- }
-
+static arch_irn_class_t arm_classify(const ir_node *irn)
+{
+ (void) irn;
+ /* TODO: we should mark reload/spill instructions and classify them here */
return 0;
}
-static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
- irn = my_skip_proj(irn);
+static ir_entity *arm_get_frame_entity(const ir_node *irn)
+{
+ const arm_attr_t *attr = get_arm_attr_const(irn);
- if (is_arm_irn(irn)) {
- return get_arm_flags(irn);
+ if (is_arm_FrameAddr(irn)) {
+ const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
+ return attr->entity;
}
- else if (is_Unknown(irn)) {
- return arch_irn_flags_ignore;
+ if (attr->is_load_store) {
+ const arm_load_store_attr_t *load_store_attr
+ = get_arm_load_store_attr_const(irn);
+ if (load_store_attr->is_frame_entity) {
+ return load_store_attr->entity;
+ }
}
-
- return 0;
-}
-
-static entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
- /* TODO: return the entity assigned to the frame */
return NULL;
}
* This function is called by the generic backend to correct offsets for
* nodes accessing the stack.
*/
-static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
- /* TODO: correct offset if irn accesses the stack */
+static void arm_set_stack_bias(ir_node *irn, int bias)
+{
+ if (is_arm_FrameAddr(irn)) {
+ arm_SymConst_attr_t *attr = get_irn_generic_attr(irn);
+ attr->fp_offset += bias;
+ } else {
+ arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
+ assert(attr->base.is_load_store);
+ attr->offset += bias;
+ }
+}
+
+static int arm_get_sp_bias(const ir_node *irn)
+{
+ /* We don't have any nodes changing the stack pointer.
+ We probably want to support post-/pre increment/decrement later */
+ (void) irn;
+ return 0;
}
/* fill register allocator interface */
-static const arch_irn_ops_if_t arm_irn_ops_if = {
- arm_get_irn_reg_req,
- arm_set_irn_reg,
- arm_get_irn_reg,
+static const arch_irn_ops_t arm_irn_ops = {
+ get_arm_in_req,
arm_classify,
- arm_get_flags,
arm_get_frame_entity,
- arm_set_stack_bias
+ arm_set_stack_bias,
+ arm_get_sp_bias,
+ NULL, /* get_inverse */
+ NULL, /* get_op_estimated_cost */
+ NULL, /* possible_memory_operand */
+ NULL, /* perform_memory_operand */
};
-arm_irn_ops_t arm_irn_ops = {
- &arm_irn_ops_if,
- NULL
-};
-
-
-
-/**************************************************
- * _ _ __
- * | | (_)/ _|
- * ___ ___ __| | ___ __ _ ___ _ __ _| |_
- * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
- * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
- * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
- * __/ |
- * |___/
- **************************************************/
-
/**
- * Transforms the standard firm graph into
- * a ARM firm graph
+ * Transforms the standard Firm graph into
+ * a ARM firm graph.
*/
-static void arm_prepare_graph(void *self) {
+static void arm_prepare_graph(void *self)
+{
arm_code_gen_t *cg = self;
- irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
-}
+ /* transform nodes into assembler instructions */
+ arm_transform_graph(cg);
+
+ /* do local optimizations (mainly CSE) */
+ local_optimize_graph(cg->irg);
+
+ if (cg->dump)
+ dump_ir_graph(cg->irg, "transformed");
+ /* do code placement, to optimize the position of constants */
+ place_code(cg->irg);
+ if (cg->dump)
+ dump_ir_graph(cg->irg, "place");
+}
/**
* Called immediately before emit phase.
*/
-static void arm_finish_irg(ir_graph *irg, arm_code_gen_t *cg) {
- /* TODO: - fix offsets for nodes accessing stack
- - ...
- */
+static void arm_finish_irg(void *self)
+{
+ arm_code_gen_t *cg = self;
+
+ /* do peephole optimizations and fix stack offsets */
+ arm_peephole_optimization(cg);
}
+static ir_node *arm_flags_remat(ir_node *node, ir_node *after)
+{
+ ir_node *block;
+ ir_node *copy;
-/**
- * These are some hooks which must be filled but are probably not needed.
- */
-static void arm_before_sched(void *self) {
- /* Some stuff you need to do after scheduling but before register allocation */
+ if (is_Block(after)) {
+ block = after;
+ } else {
+ block = get_nodes_block(after);
+ }
+ copy = exact_copy(node);
+ set_nodes_block(copy, block);
+ sched_add_after(after, copy);
+ return copy;
}
-static void arm_before_ra(void *self) {
- /* Some stuff you need to do immediately after register allocation */
+static void arm_before_ra(void *self)
+{
+ arm_code_gen_t *cg = self;
+
+ be_sched_fix_flags(cg->irg, &arm_reg_classes[CLASS_arm_flags],
+ &arm_flags_remat);
}
+static void transform_Reload(ir_node *node)
+{
+ ir_node *block = get_nodes_block(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *ptr = get_irn_n(node, be_pos_Reload_frame);
+ ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
+ ir_mode *mode = get_irn_mode(node);
+ ir_entity *entity = be_get_frame_entity(node);
+ const arch_register_t *reg;
+ ir_node *proj;
+ ir_node *load;
-/**
- * Emits the code, closes the output file and frees
- * the code generator interface.
- */
-static void arm_emit_and_done(void *self) {
- arm_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
- FILE *out = cg->out;
+ ir_node *sched_point = sched_prev(node);
- if (cg->emit_decls) {
- arm_gen_decls(cg->out);
- cg->emit_decls = 0;
- }
+ load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
+ sched_add_after(sched_point, load);
+ sched_remove(node);
- arm_finish_irg(irg, cg);
- dump_ir_block_graph_sched(irg, "-arm-finished");
- arm_gen_routine(out, irg, cg);
+ proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
- cur_reg_set = NULL;
+ reg = arch_get_irn_register(node);
+ arch_set_irn_register(proj, reg);
- /* de-allocate code generator */
- del_set(cg->reg_set);
- free(self);
+ exchange(node, proj);
}
-enum convert_which { low, high };
+static void transform_Spill(ir_node *node)
+{
+ ir_node *block = get_nodes_block(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *ptr = get_irn_n(node, be_pos_Spill_frame);
+ ir_node *mem = new_NoMem();
+ ir_node *val = get_irn_n(node, be_pos_Spill_val);
+ ir_mode *mode = get_irn_mode(val);
+ ir_entity *entity = be_get_frame_entity(node);
+ ir_node *sched_point;
+ ir_node *store;
-/**
- * Move an floating point value to a integer register.
- * Place the move operation into block bl.
- */
-static ir_node *convert_to_int(ir_node *bl, ir_node *arg, enum convert_which which) {
- return NULL;
+ sched_point = sched_prev(node);
+ store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
+ true);
+
+ sched_remove(node);
+ sched_add_after(sched_point, store);
+
+ exchange(node, store);
}
-/**
- * Convert the arguments of a call to support the
- * ARM calling convention of general purpose AND floating
- * point arguments
- */
-static void handle_calls(ir_node *call, void *env)
+static void arm_after_ra_walker(ir_node *block, void *data)
{
- arm_code_gen_t *cg = env;
- int i, j, n, size, idx, flag, n_param, n_res;
- ir_type *mtp, *new_mtd, *new_tp[5];
- ir_node *new_in[5], **in;
- ir_node *bl;
+ ir_node *node, *prev;
+ (void) data;
- if (! is_Call(call))
- return;
+ for (node = sched_last(block); !sched_is_begin(node); node = prev) {
+ prev = sched_prev(node);
- /* check, if we need conversions */
- n = get_Call_n_params(call);
- mtp = get_Call_type(call);
- assert(get_method_n_params(mtp) == n);
-
- /* it's always enough to handle the first 4 parameters */
- if (n > 4)
- n = 4;
- flag = size = idx = 0;
- bl = get_nodes_block(call);
- for (i = 0; i < n; ++i) {
- ir_type *param_tp = get_method_param_type(mtp, i);
-
- if (is_compound_type(param_tp)) {
- /* an aggregate parameter: bad case */
- assert(0);
- }
- else {
- /* a primitive parameter */
- ir_mode *mode = get_type_mode(param_tp);
-
- if (mode_is_float(mode)) {
- if (get_mode_size_bits(mode) > 32) {
- size += 2 * 4;
- new_tp[idx] = cg->int_tp;
- new_in[idx] = convert_to_int(bl, get_Call_param(call, i), low);
- ++idx;
- new_tp[idx] = cg->int_tp;
- new_in[idx] = convert_to_int(bl, get_Call_param(call, i), high);
- ++idx;
- }
- else {
- size += 4;
- new_tp[idx] = cg->int_tp;
- new_in[idx] = convert_to_int(bl, get_Call_param(call, i), low);
- ++idx;
- }
- flag = 1;
- }
- else {
- size += 4;
- new_tp[idx] = param_tp;
- new_in[idx] = get_Call_param(call, i);
- ++idx;
- }
+ if (be_is_Reload(node)) {
+ transform_Reload(node);
+ } else if (be_is_Spill(node)) {
+ transform_Spill(node);
}
-
- if (size >= 16)
- break;
}
+}
- /* if flag is NOT set, no need to translate the method type */
- if (! flag)
+static void arm_collect_frame_entity_nodes(ir_node *node, void *data)
+{
+ be_fec_env_t *env = data;
+ const ir_mode *mode;
+ int align;
+ ir_entity *entity;
+ const arm_load_store_attr_t *attr;
+
+ if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
+ mode = get_irn_mode(node);
+ align = get_mode_size_bytes(mode);
+ be_node_needs_frame_entity(env, node, mode, align);
return;
+ }
- /* construct a new method type */
- n = i;
- n_param = get_method_n_params(mtp) - n + idx;
- n_res = get_method_n_ress(mtp);
- new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp));
-
- for (i = 0; i < idx; ++i)
- set_method_param_type(new_mtd, i, new_tp[i]);
- for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
- set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i));
- for (i = 0; i < n_res; ++i)
- set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
+ switch (get_arm_irn_opcode(node)) {
+ case iro_arm_Ldf:
+ case iro_arm_Ldr:
+ break;
+ default:
+ return;
+ }
- set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
- set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
+ attr = get_arm_load_store_attr_const(node);
+ entity = attr->entity;
+ mode = attr->load_store_mode;
+ align = get_mode_size_bytes(mode);
+ if (entity != NULL)
+ return;
+ if (!attr->is_frame_entity)
+ return;
+ be_node_needs_frame_entity(env, node, mode, align);
+}
- if (is_lowered_type(mtp)) {
- mtp = get_associated_type(mtp);
+static void arm_set_frame_entity(ir_node *node, ir_entity *entity)
+{
+ if (is_be_node(node)) {
+ be_node_set_frame_entity(node, entity);
+ } else {
+ arm_load_store_attr_t *attr = get_arm_load_store_attr(node);
+ attr->entity = entity;
}
- set_lowered_type(mtp, new_mtd);
+}
- set_Call_type(call, new_mtd);
+static void arm_after_ra(void *self)
+{
+ arm_code_gen_t *cg = self;
+ ir_graph *irg = cg->irg;
- /* calculate new in array of the Call */
- NEW_ARR_A(ir_node *, in, n_param + 2);
- for (i = 0; i < idx; ++i)
- in[2 + i] = new_in[i];
- for (i = n, j = idx; i < get_method_n_params(mtp); ++i)
- in[2 + j++] = get_Call_param(call, i);
+ be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
- in[0] = get_Call_mem(call);
- in[1] = get_Call_ptr(call);
+ irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env);
+ be_assign_entities(fec_env, arm_set_frame_entity);
+ be_free_frame_entity_coalescer(fec_env);
- /* finally, change the call inputs */
- set_irn_in(call, n_param + 2, in);
+ irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL);
}
/**
- * Handle graph transformations before the abi converter does it's work
+ * Emits the code, closes the output file and frees
+ * the code generator interface.
*/
-static void arm_before_abi(void *self) {
+static void arm_emit_and_done(void *self)
+{
arm_code_gen_t *cg = self;
+ ir_graph *irg = cg->irg;
- irg_walk_graph(cg->irg, NULL, handle_calls, cg);
+ arm_gen_routine(cg, irg);
+
+ /* de-allocate code generator */
+ free(self);
}
-static void *arm_cg_init(FILE *F, const be_irg_t *birg);
+/* forward */
+static void *arm_cg_init(ir_graph *irg);
static const arch_code_generator_if_t arm_code_gen_if = {
arm_cg_init,
- arm_before_abi, /* before abi introduce */
+ NULL, /* get_pic_base */
+ NULL, /* before abi introduce */
arm_prepare_graph,
- arm_before_sched, /* before scheduling hook */
+ NULL, /* spill */
arm_before_ra, /* before register allocation hook */
- NULL, /* after register allocation */
+ arm_after_ra,
+ arm_finish_irg,
arm_emit_and_done,
};
/**
* Initializes the code generator.
*/
-static void *arm_cg_init(FILE *F, const be_irg_t *birg) {
- static ir_type *int_tp = NULL;
- arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
+static void *arm_cg_init(ir_graph *irg)
+{
+ arm_isa_t *isa = (arm_isa_t*) be_get_irg_arch_env(irg);
arm_code_gen_t *cg;
- if (! int_tp) {
- /* create an integer type with machine size */
- int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
- }
-
- cg = xmalloc(sizeof(*cg));
- cg->impl = &arm_code_gen_if;
- cg->irg = birg->irg;
- cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
- cg->out = F;
- cg->arch_env = birg->main_env->arch_env;
- cg->birg = birg;
- cg->int_tp = int_tp;
- FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
-
- isa->num_codegens++;
-
- if (isa->num_codegens > 1)
- cg->emit_decls = 0;
- else
- cg->emit_decls = 1;
-
- cur_reg_set = cg->reg_set;
+ cg = XMALLOCZ(arm_code_gen_t);
+ cg->impl = &arm_code_gen_if;
+ cg->irg = irg;
+ cg->isa = isa;
+ cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
- arm_irn_ops.cg = cg;
+ /* enter the current code generator */
+ isa->cg = cg;
return (arch_code_generator_t *)cg;
}
* and map all instructions the backend did not support
* to runtime calls.
*/
-void arm_global_init(void) {
- ir_type *tp, *int_tp, *uint_tp;
- i_record records[8];
- int n_records = 0;
+static void arm_handle_intrinsics(void)
+{
+ ir_type *tp, *int_tp, *uint_tp;
+ i_record records[8];
+ int n_records = 0;
+
+ runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
#define ID(x) new_id_from_chars(x, sizeof(x)-1)
- int_tp = new_type_primitive(ID("int"), mode_Is);
- uint_tp = new_type_primitive(ID("uint"), mode_Iu);
-
- {
- runtime_rt rt_Div;
- i_instr_record *map_Div = &records[n_records++].i_instr;
-
- tp = new_type_method(ID("rt_iDiv"), 2, 1);
- set_method_param_type(tp, 0, int_tp);
- set_method_param_type(tp, 1, int_tp);
- set_method_res_type(tp, 0, int_tp);
-
- rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
- rt_Div.mode = mode_T;
- rt_Div.mem_proj_nr = pn_Div_M;
- rt_Div.exc_proj_nr = pn_Div_X_except;
- rt_Div.exc_mem_proj_nr = pn_Div_M;
- rt_Div.res_proj_nr = pn_Div_res;
-
- set_entity_visibility(rt_Div.ent, visibility_external_allocated);
-
- map_Div->kind = INTRINSIC_INSTR;
- map_Div->op = op_Div;
- map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Div->ctx = &rt_Div;
- }
- {
- runtime_rt rt_Div;
- i_instr_record *map_Div = &records[n_records++].i_instr;
-
- tp = new_type_method(ID("rt_uDiv"), 2, 1);
- set_method_param_type(tp, 0, uint_tp);
- set_method_param_type(tp, 1, uint_tp);
- set_method_res_type(tp, 0, uint_tp);
-
- rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
- rt_Div.mode = mode_T;
- rt_Div.mem_proj_nr = pn_Div_M;
- rt_Div.exc_proj_nr = pn_Div_X_except;
- rt_Div.exc_mem_proj_nr = pn_Div_M;
- rt_Div.res_proj_nr = pn_Div_res;
-
- set_entity_visibility(rt_Div.ent, visibility_external_allocated);
-
- map_Div->kind = INTRINSIC_INSTR;
- map_Div->op = op_Div;
- map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Div->ctx = &rt_Div;
- }
- {
- runtime_rt rt_Mod;
- i_instr_record *map_Mod = &records[n_records++].i_instr;
-
- tp = new_type_method(ID("rt_iMod"), 2, 1);
- set_method_param_type(tp, 0, int_tp);
- set_method_param_type(tp, 1, int_tp);
- set_method_res_type(tp, 0, int_tp);
-
- rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
- rt_Mod.mode = mode_T;
- rt_Mod.mem_proj_nr = pn_Mod_M;
- rt_Mod.exc_proj_nr = pn_Mod_X_except;
- rt_Mod.exc_mem_proj_nr = pn_Mod_M;
- rt_Mod.res_proj_nr = pn_Mod_res;
-
- set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
-
- map_Mod->kind = INTRINSIC_INSTR;
- map_Mod->op = op_Mod;
- map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Mod->ctx = &rt_Mod;
- }
- {
- runtime_rt rt_Mod;
- i_instr_record *map_Mod = &records[n_records++].i_instr;
-
- tp = new_type_method(ID("rt_uMod"), 2, 1);
- set_method_param_type(tp, 0, uint_tp);
- set_method_param_type(tp, 1, uint_tp);
- set_method_res_type(tp, 0, uint_tp);
-
- rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
- rt_Mod.mode = mode_T;
- rt_Mod.mem_proj_nr = pn_Mod_M;
- rt_Mod.exc_proj_nr = pn_Mod_X_except;
- rt_Mod.exc_mem_proj_nr = pn_Mod_M;
- rt_Mod.res_proj_nr = pn_Mod_res;
-
- set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
-
- map_Mod->kind = INTRINSIC_INSTR;
- map_Mod->op = op_Mod;
- map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Mod->ctx = &rt_Mod;
- }
-
- if (n_records > 0)
- lower_intrinsics(records, n_records);
-}
-
-/*****************************************************************
- * ____ _ _ _____ _____
- * | _ \ | | | | |_ _|/ ____| /\
- * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
- * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
- * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
- * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
- *
- *****************************************************************/
+ int_tp = get_type_for_mode(mode_Is);
+ uint_tp = get_type_for_mode(mode_Iu);
+
+ /* ARM has neither a signed div instruction ... */
+ {
+ i_instr_record *map_Div = &records[n_records++].i_instr;
+
+ tp = new_type_method(2, 1);
+ set_method_param_type(tp, 0, int_tp);
+ set_method_param_type(tp, 1, int_tp);
+ set_method_res_type(tp, 0, int_tp);
+
+ rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
+ set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
+ rt_iDiv.mode = mode_T;
+ rt_iDiv.res_mode = mode_Is;
+ rt_iDiv.mem_proj_nr = pn_Div_M;
+ rt_iDiv.regular_proj_nr = pn_Div_X_regular;
+ rt_iDiv.exc_proj_nr = pn_Div_X_except;
+ rt_iDiv.exc_mem_proj_nr = pn_Div_M;
+ rt_iDiv.res_proj_nr = pn_Div_res;
+
+ add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT);
+ set_entity_visibility(rt_iDiv.ent, ir_visibility_external);
+
+ map_Div->kind = INTRINSIC_INSTR;
+ map_Div->op = op_Div;
+ map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+ map_Div->ctx = &rt_iDiv;
+ }
+ /* ... nor an unsigned div instruction ... */
+ {
+ i_instr_record *map_Div = &records[n_records++].i_instr;
+
+ tp = new_type_method(2, 1);
+ set_method_param_type(tp, 0, uint_tp);
+ set_method_param_type(tp, 1, uint_tp);
+ set_method_res_type(tp, 0, uint_tp);
+
+ rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
+ set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
+ rt_uDiv.mode = mode_T;
+ rt_uDiv.res_mode = mode_Iu;
+ rt_uDiv.mem_proj_nr = pn_Div_M;
+ rt_uDiv.regular_proj_nr = pn_Div_X_regular;
+ rt_uDiv.exc_proj_nr = pn_Div_X_except;
+ rt_uDiv.exc_mem_proj_nr = pn_Div_M;
+ rt_uDiv.res_proj_nr = pn_Div_res;
+
+ set_entity_visibility(rt_uDiv.ent, ir_visibility_external);
+
+ map_Div->kind = INTRINSIC_INSTR;
+ map_Div->op = op_Div;
+ map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+ map_Div->ctx = &rt_uDiv;
+ }
+ /* ... nor a signed mod instruction ... */
+ {
+ i_instr_record *map_Mod = &records[n_records++].i_instr;
+
+ tp = new_type_method(2, 1);
+ set_method_param_type(tp, 0, int_tp);
+ set_method_param_type(tp, 1, int_tp);
+ set_method_res_type(tp, 0, int_tp);
+
+ rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
+ set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
+ rt_iMod.mode = mode_T;
+ rt_iMod.res_mode = mode_Is;
+ rt_iMod.mem_proj_nr = pn_Mod_M;
+ rt_iMod.regular_proj_nr = pn_Mod_X_regular;
+ rt_iMod.exc_proj_nr = pn_Mod_X_except;
+ rt_iMod.exc_mem_proj_nr = pn_Mod_M;
+ rt_iMod.res_proj_nr = pn_Mod_res;
+
+ set_entity_visibility(rt_iMod.ent, ir_visibility_external);
+
+ map_Mod->kind = INTRINSIC_INSTR;
+ map_Mod->op = op_Mod;
+ map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+ map_Mod->ctx = &rt_iMod;
+ }
+ /* ... nor an unsigned mod. */
+ {
+ i_instr_record *map_Mod = &records[n_records++].i_instr;
+
+ tp = new_type_method(2, 1);
+ set_method_param_type(tp, 0, uint_tp);
+ set_method_param_type(tp, 1, uint_tp);
+ set_method_res_type(tp, 0, uint_tp);
+
+ rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
+ set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
+ rt_uMod.mode = mode_T;
+ rt_uMod.res_mode = mode_Iu;
+ rt_uMod.mem_proj_nr = pn_Mod_M;
+ rt_uMod.regular_proj_nr = pn_Mod_X_regular;
+ rt_uMod.exc_proj_nr = pn_Mod_X_except;
+ rt_uMod.exc_mem_proj_nr = pn_Mod_M;
+ rt_uMod.res_proj_nr = pn_Mod_res;
+
+ set_entity_visibility(rt_uMod.ent, ir_visibility_external);
+
+ map_Mod->kind = INTRINSIC_INSTR;
+ map_Mod->op = op_Mod;
+ map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+ map_Mod->ctx = &rt_uMod;
+ }
+
+ if (n_records > 0)
+ lower_intrinsics(records, n_records, /*part_block_used=*/0);
+}
+const arch_isa_if_t arm_isa_if;
static arm_isa_t arm_isa_template = {
- &arm_isa_if, /* isa interface */
- &arm_general_purpose_regs[REG_R13], /* stack pointer */
- &arm_general_purpose_regs[REG_R11], /* base pointer */
- -1, /* stack direction */
- 0 /* number of codegenerator objects */
+ {
+ &arm_isa_if, /* isa interface */
+ &arm_gp_regs[REG_SP], /* stack pointer */
+ &arm_gp_regs[REG_R11], /* base pointer */
+ &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
+ -1, /* stack direction */
+ 2, /* power of two stack alignment for calls, 2^2 == 4 */
+ NULL, /* main environment */
+ 7, /* spill costs */
+ 5, /* reload costs */
+ true, /* we do have custom abi handling */
+ },
+ ARM_FPU_ARCH_FPE, /* FPU architecture */
+ NULL, /* current code generator */
};
/**
* Initializes the backend ISA and opens the output file.
*/
-static void *arm_init(void) {
+static arch_env_t *arm_init(FILE *file_handle)
+{
static int inited = 0;
arm_isa_t *isa;
- if(inited)
+ if (inited)
return NULL;
- isa = xcalloc(1, sizeof(*isa));
+ isa = XMALLOC(arm_isa_t);
memcpy(isa, &arm_isa_template, sizeof(*isa));
- arm_register_init(isa);
- arm_create_opcodes();
+ arm_register_init();
- inited = 1;
+ isa->cg = NULL;
+ be_emit_init(file_handle);
+
+ arm_create_opcodes(&arm_irn_ops);
+ arm_handle_intrinsics();
+
+ be_gas_emit_types = false;
- return isa;
+ /* needed for the debug support */
+ be_gas_emit_switch_section(GAS_SECTION_TEXT);
+ be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
+ be_emit_write_line();
+
+ inited = 1;
+ return &isa->base;
}
/**
* Closes the output file and frees the ISA structure.
*/
-static void arm_done(void *self) {
+static void arm_done(void *self)
+{
+ arm_isa_t *isa = self;
+
+ be_gas_emit_decls(isa->base.main_env);
+
+ be_emit_exit();
free(self);
}
-
-static int arm_get_n_reg_class(const void *self) {
+/**
+ * Report the number of register classes.
+ * If we don't have fp instructions, report only GP
+ * here to speed up register allocation (and makes dumps
+ * smaller and more readable).
+ */
+static unsigned arm_get_n_reg_class(void)
+{
return N_CLASSES;
}
-static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
- assert(i >= 0 && i < N_CLASSES && "Invalid arm register class requested.");
+/**
+ * Return the register class with requested index.
+ */
+static const arch_register_class_t *arm_get_reg_class(unsigned i)
+{
+ assert(i < N_CLASSES);
return &arm_reg_classes[i];
}
-
-
/**
* Get the register class which shall be used to store a value of a given mode.
* @param self The this pointer.
* @param mode The mode in question.
* @return A register class which can hold values of the given mode.
*/
-const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
+static const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode)
+{
if (mode_is_float(mode))
- return &arm_reg_classes[CLASS_arm_floating_point];
+ return &arm_reg_classes[CLASS_arm_fpa];
else
- return &arm_reg_classes[CLASS_arm_general_purpose];
+ return &arm_reg_classes[CLASS_arm_gp];
}
+static int arm_to_appear_in_schedule(void *block_env, const ir_node *irn)
+{
+ (void) block_env;
+ if (!is_arm_irn(irn))
+ return -1;
+ return 1;
+}
/**
- * Produces the type which sits between the stack args and the locals on the stack.
- * it will contain the return address and space to store the old base pointer.
- * @return The Firm type modelling the ABI between type.
+ * Initializes the code generator interface.
*/
-static ir_type *arm_get_between_type(void *self) {
- static ir_type *between_type = NULL;
- static entity *old_bp_ent = NULL;
-
- if(!between_type) {
- entity *ret_addr_ent;
- ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
- ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
-
- between_type = new_type_class(new_id_from_str("arm_between_type"));
- old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
- ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
-
- set_entity_offset_bytes(old_bp_ent, 0);
- set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
- set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
- }
-
- return between_type;
+static const arch_code_generator_if_t *arm_get_code_generator_if(void *self)
+{
+ (void) self;
+ return &arm_code_gen_if;
}
+list_sched_selector_t arm_sched_selector;
+/**
+ * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
+ */
+static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector)
+{
+ (void) self;
+ memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
+ /* arm_sched_selector.exectime = arm_sched_exectime; */
+ arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
+ return &arm_sched_selector;
+}
-
-
-
-
-typedef struct {
- be_abi_call_flags_bits_t flags;
- const arch_env_t *arch_env;
- const arch_isa_t *isa;
- ir_graph *irg;
-} arm_abi_env_t;
-
-static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
+static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self)
{
- arm_abi_env_t *env = xmalloc(sizeof(env[0]));
- be_abi_call_flags_t fl = be_abi_call_get_flags(call);
- env->flags = fl.bits;
- env->irg = irg;
- env->arch_env = arch_env;
- env->isa = arch_env->isa;
- return env;
+ (void) self;
+ return NULL;
}
-static void arm_abi_dont_save_regs(void *self, pset *s)
+/**
+ * Returns the necessary byte alignment for storing a register of given class.
+ */
+static int arm_get_reg_class_alignment(const arch_register_class_t *cls)
{
- arm_abi_env_t *env = self;
- if(env->flags.try_omit_fp)
- pset_insert_ptr(s, env->isa->bp);
+ (void) cls;
+ /* ARM is a 32 bit CPU, no need for other alignment */
+ return 4;
}
+static const be_execution_unit_t ***arm_get_allowed_execution_units(const ir_node *irn)
+{
+ (void) irn;
+ /* TODO */
+ panic("Unimplemented arm_get_allowed_execution_units()");
+}
+static const be_machine_t *arm_get_machine(const void *self)
+{
+ (void) self;
+ /* TODO */
+ panic("Unimplemented arm_get_machine()");
+}
/**
- * Build the ARM prolog
+ * Return irp irgs in the desired order.
*/
-static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
- ir_node *keep, *store;
- arm_abi_env_t *env = self;
- ir_graph *irg = env->irg;
- ir_node *block = get_irg_start_block(irg);
-// ir_node *regs[16];
-// int n_regs = 0;
- arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_general_purpose];
- static const arm_register_req_t *fp_req[] = {
- &arm_default_req_arm_general_purpose_r11
- };
-
- ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
- ir_node *ip = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R12]);
- ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
- ir_node *lr = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R14]);
- ir_node *pc = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R15]);
-// ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R0]);
-// ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R1]);
-// ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R2]);
-// ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R3]);
-
- if(env->flags.try_omit_fp)
- return env->isa->sp;
-
- ip = be_new_Copy(gp, irg, block, sp );
- arch_set_irn_register(env->arch_env, ip, &arm_general_purpose_regs[REG_R12]);
- be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_general_purpose_regs[REG_R12] );
-
-// if (r0) regs[n_regs++] = r0;
-// if (r1) regs[n_regs++] = r1;
-// if (r2) regs[n_regs++] = r2;
-// if (r3) regs[n_regs++] = r3;
-// sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
-// set_arm_req_out(sp, &arm_default_req_arm_general_purpose_r13, 0);
-// arch_set_irn_register(env->arch_env, sp, env->isa->sp);
- store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem, mode_T);
- set_arm_req_out(store, &arm_default_req_arm_general_purpose_r13, 0);
-// arch_set_irn_register(env->arch_env, store, env->isa->sp);
-
- sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, 0);
- arch_set_irn_register(env->arch_env, sp, env->isa->sp);
- *mem = new_r_Proj(irg, block, store, mode_M, 1);
-
- keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
- be_node_set_reg_class(keep, 1, gp);
- arch_set_irn_register(env->arch_env, keep, &arm_general_purpose_regs[REG_R12]);
- be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_general_purpose_regs[REG_R12] );
-
- fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp) );
- set_arm_value(fp, new_tarval_from_long(4, mode_Iu));
- set_arm_req_out_all(fp, fp_req);
- //set_arm_req_out(fp, &arm_default_req_arm_general_purpose_r11, 0);
- arch_set_irn_register(env->arch_env, fp, env->isa->bp);
-
-// be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R0], r0);
-// be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R1], r1);
-// be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R2], r2);
-// be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R3], r3);
- be_abi_reg_map_set(reg_map, env->isa->bp, fp);
- be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R12], keep);
- be_abi_reg_map_set(reg_map, env->isa->sp, sp);
- be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R14], lr);
- be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R15], pc);
-
- return env->isa->bp;
-}
-
-static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
- arm_abi_env_t *env = self;
- ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
- ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
- ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R15]);
- ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R14]);
- static const arm_register_req_t *sub12_req[] = {
- &arm_default_req_arm_general_purpose_r13
- };
-
-// TODO: Activate Omit fp in epilogue
- if(env->flags.try_omit_fp) {
- curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
-
- curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_general_purpose], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
- be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_general_purpose]);
- arch_set_irn_register(env->arch_env, curr_lr, &arm_general_purpose_regs[REG_R14]);
- be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_general_purpose_regs[REG_R14] );
-
- curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_general_purpose], env->irg, bl, curr_lr );
- arch_set_irn_register(env->arch_env, curr_pc, &arm_general_purpose_regs[REG_R15]);
- be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_general_purpose_regs[REG_R15] );
- } else {
- ir_node *sub12_node;
- ir_node *load_node;
- sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu );
- set_arm_value(sub12_node, new_tarval_from_long(12,mode_Iu));
- set_arm_req_out_all(sub12_node, sub12_req);
- arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
- load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem, mode_T );
- set_arm_req_out(load_node, &arm_default_req_arm_general_purpose_r11, 0);
- set_arm_req_out(load_node, &arm_default_req_arm_general_purpose_r13, 1);
- set_arm_req_out(load_node, &arm_default_req_arm_general_purpose_r15, 2);
- curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, 0);
- curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, 1);
- curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, 2);
- *mem = new_r_Proj(env->irg, bl, load_node, mode_M, 3);
- arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
- arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
- arch_set_irn_register(env->arch_env, curr_pc, &arm_general_purpose_regs[REG_R15]);
- }
- be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
- be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
- be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R14], curr_lr);
- be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R15], curr_pc);
-}
-
-static const be_abi_callbacks_t arm_abi_callbacks = {
- arm_abi_init,
- free,
- arm_get_between_type,
- arm_abi_dont_save_regs,
- arm_abi_prologue,
- arm_abi_epilogue,
-};
-
+static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list)
+{
+ (void) self;
+ (void) irg_list;
+ return NULL;
+}
/**
- * Get the ABI restrictions for procedure calls.
- * @param self The this pointer.
- * @param method_type The type of the method (procedure) in question.
- * @param abi The abi object to be modified
+ * Allows or disallows the creation of Psi nodes for the given Phi nodes.
+ * @return 1 if allowed, 0 otherwise
*/
-void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
- ir_type *tp;
- ir_mode *mode;
- int i;
- int n = get_method_n_params(method_type);
- be_abi_call_flags_t flags = {
- {
- 0, /* store from left to right */
- 0, /* store arguments sequential */
- 1, /* try to omit the frame pointer */
- 1, /* the function can use any register as frame pointer */
- 1 /* a call can take the callee's address as an immediate */
- }
- };
-
- /* set stack parameter passing style */
- be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
-
- for (i = 0; i < n; i++) {
- /* reg = get reg for param i; */
- /* be_abi_call_param_reg(abi, i, reg); */
- if (i < 4)
-
- be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
- else
- be_abi_call_param_stack(abi, i, 4, 0, 0);
- }
-
- /* default: return value is in R0 resp. F0 */
- assert(get_method_n_ress(method_type) < 2);
- if (get_method_n_ress(method_type) > 0) {
- tp = get_method_res_type(method_type, 0);
- mode = get_type_mode(tp);
-
- be_abi_call_res_reg(abi, 0,
- mode_is_float(mode) ? &arm_floating_point_regs[REG_F0] : &arm_general_purpose_regs[REG_R0]);
- }
-}
+static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false,
+ ir_node *mux_true)
+{
+ (void) sel;
+ (void) mux_false;
+ (void) mux_true;
-static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
- return &arm_irn_ops;
+ return 0;
}
-const arch_irn_handler_t arm_irn_handler = {
- arm_get_irn_ops
-};
-
-const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
- return &arm_irn_handler;
+static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
+{
+ /* asm not supported */
+ (void) c;
+ return ASM_CONSTRAINT_FLAG_INVALID;
}
-int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
- return is_arm_irn(irn);
+static int arm_is_valid_clobber(const char *clobber)
+{
+ (void) clobber;
+ return 0;
}
/**
- * Initializes the code generator interface.
+ * Returns the libFirm configuration parameter for this backend.
*/
-static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
- return &arm_code_gen_if;
-}
-
-list_sched_selector_t arm_sched_selector;
+static const backend_params *arm_get_libfirm_params(void)
+{
+ static const ir_settings_if_conv_t ifconv = {
+ 4, /* maxdepth, doesn't matter for Psi-conversion */
+ arm_is_mux_allowed /* allows or disallows Mux creation for given selector */
+ };
+ static ir_settings_arch_dep_t ad = {
+ 1, /* allow subs */
+ 1, /* Muls are fast enough on ARM but ... */
+ 31, /* ... one shift would be possible better */
+ NULL, /* no evaluator function */
+ 0, /* SMUL is needed, only in Arch M */
+ 0, /* UMUL is needed, only in Arch M */
+ 32, /* SMUL & UMUL available for 32 bit */
+ };
+ static backend_params p = {
+ 1, /* need dword lowering */
+ 0, /* don't support inline assembler yet */
+ NULL, /* will be set later */
+ NULL, /* but yet no creator function */
+ NULL, /* context for create_intrinsic_fkt */
+ NULL, /* ifconv_info will be set below */
+ NULL, /* float arithmetic mode (TODO) */
+ 0, /* no trampoline support: size 0 */
+ 0, /* no trampoline support: align 0 */
+ NULL, /* no trampoline support: no trampoline builder */
+ 4 /* alignment of stack parameter */
+ };
-/**
- * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
- */
-static const list_sched_selector_t *arm_get_list_sched_selector(const void *self) {
- memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
- arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
- return &arm_sched_selector;
+ p.dep_param = &ad;
+ p.if_conv_info = &ifconv;
+ return &p;
}
-/**
- * Returns the necessary byte alignment for storing a register of given class.
- */
-static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
- ir_mode *mode = arch_register_class_mode(cls);
- return get_mode_size_bytes(mode);
-}
+/* fpu set architectures. */
+static const lc_opt_enum_int_items_t arm_fpu_items[] = {
+ { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
+ { "fpe", ARM_FPU_ARCH_FPE },
+ { "fpa", ARM_FPU_ARCH_FPA },
+ { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
+ { "vfp1", ARM_FPU_ARCH_VFP_V1 },
+ { "vfp2", ARM_FPU_ARCH_VFP_V2 },
+ { NULL, 0 }
+};
-#ifdef WITH_LIBCORE
-static void arm_register_options(lc_opt_entry_t *ent)
-{
-}
-#endif /* WITH_LIBCORE */
+static lc_opt_enum_int_var_t arch_fpu_var = {
+ &arm_isa_template.fpu_arch, arm_fpu_items
+};
+
+static const lc_opt_table_entry_t arm_options[] = {
+ LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
+ LC_OPT_LAST
+};
const arch_isa_if_t arm_isa_if = {
-#ifdef WITH_LIBCORE
- arm_register_options,
-#endif
arm_init,
arm_done,
+ NULL, /* handle_intrinsics */
arm_get_n_reg_class,
arm_get_reg_class,
arm_get_reg_class_for_mode,
- arm_get_call_abi,
- arm_get_irn_handler,
+ NULL,
arm_get_code_generator_if,
arm_get_list_sched_selector,
- arm_get_reg_class_alignment
+ arm_get_ilp_sched_selector,
+ arm_get_reg_class_alignment,
+ arm_get_libfirm_params,
+ arm_get_allowed_execution_units,
+ arm_get_machine,
+ arm_get_irg_list,
+ NULL, /* mark remat */
+ arm_parse_asm_constraint,
+ arm_is_valid_clobber
};
+
+BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
+void be_init_arch_arm(void)
+{
+ lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
+ lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
+
+ lc_opt_add_table(arm_grp, arm_options);
+
+ be_register_isa_if("arm", &arm_isa_if);
+
+ arm_init_transform();
+ arm_init_emitter();
+}
projects / libfirm / blobdiff