/*
- * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
*
* This file is part of libFirm.
*
#include "config.h"
#endif
-#include <libcore/lc_opts.h>
-#include <libcore/lc_opts_enum.h>
+#include "lc_opts.h"
+#include "lc_opts_enum.h"
#include "pseudo_irg.h"
#include "irgwalk.h"
#include "ircons.h"
#include "irgmod.h"
#include "irgopt.h"
+#include "iroptimize.h"
#include "lowering.h"
#include "bitset.h"
#include "debug.h"
+#include "irtools.h"
#include "../bearch_t.h" /* the general register allocator interface */
#include "../benode_t.h"
static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn)
{
+ arch_irn_flags_t flags = arch_irn_flags_none;
(void) self;
- irn = skip_Proj_const(irn);
- if (is_arm_irn(irn)) {
- return get_arm_flags(irn);
- }
- else if (is_Unknown(irn)) {
+ if(is_Unknown(irn)) {
return arch_irn_flags_ignore;
}
- return 0;
+ if (is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
+ ir_node *pred = get_Proj_pred(irn);
+ if (is_arm_irn(pred)) {
+ flags = get_arm_out_flags(pred, get_Proj_proj(irn));
+ }
+ irn = pred;
+ }
+
+ if (is_arm_irn(irn)) {
+ flags |= get_arm_flags(irn);
+ }
+
+ return flags;
}
static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn)
i_record records[8];
int n_records = 0;
+ runtime_rt rt_iDiv, rt_uDiv, rt_iMod, rt_uMod;
+
#define ID(x) new_id_from_chars(x, sizeof(x)-1)
int_tp = new_type_primitive(ID("int"), mode_Is);
/* ARM has neither a signed div instruction ... */
{
- runtime_rt rt_Div;
i_instr_record *map_Div = &records[n_records++].i_instr;
tp = new_type_method(ID("rt_iDiv"), 2, 1);
set_method_param_type(tp, 1, int_tp);
set_method_res_type(tp, 0, int_tp);
- rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
- rt_Div.mode = mode_T;
- rt_Div.res_mode = mode_Is;
- rt_Div.mem_proj_nr = pn_Div_M;
- rt_Div.regular_proj_nr = pn_Div_X_regular;
- rt_Div.exc_proj_nr = pn_Div_X_except;
- rt_Div.exc_mem_proj_nr = pn_Div_M;
- rt_Div.res_proj_nr = pn_Div_res;
+ rt_iDiv.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
+ set_entity_ld_ident(rt_iDiv.ent, ID("__divsi3"));
+ rt_iDiv.mode = mode_T;
+ rt_iDiv.res_mode = mode_Is;
+ rt_iDiv.mem_proj_nr = pn_Div_M;
+ rt_iDiv.regular_proj_nr = pn_Div_X_regular;
+ rt_iDiv.exc_proj_nr = pn_Div_X_except;
+ rt_iDiv.exc_mem_proj_nr = pn_Div_M;
+ rt_iDiv.res_proj_nr = pn_Div_res;
- set_entity_visibility(rt_Div.ent, visibility_external_allocated);
+ set_entity_visibility(rt_iDiv.ent, visibility_external_allocated);
map_Div->kind = INTRINSIC_INSTR;
map_Div->op = op_Div;
map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Div->ctx = &rt_Div;
+ map_Div->ctx = &rt_iDiv;
}
/* ... nor an unsigned div instruction ... */
{
- runtime_rt rt_Div;
i_instr_record *map_Div = &records[n_records++].i_instr;
tp = new_type_method(ID("rt_uDiv"), 2, 1);
set_method_param_type(tp, 1, uint_tp);
set_method_res_type(tp, 0, uint_tp);
- rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
- rt_Div.mode = mode_T;
- rt_Div.res_mode = mode_Iu;
- rt_Div.mem_proj_nr = pn_Div_M;
- rt_Div.regular_proj_nr = pn_Div_X_regular;
- rt_Div.exc_proj_nr = pn_Div_X_except;
- rt_Div.exc_mem_proj_nr = pn_Div_M;
- rt_Div.res_proj_nr = pn_Div_res;
+ rt_uDiv.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
+ set_entity_ld_ident(rt_uDiv.ent, ID("__udivsi3"));
+ rt_uDiv.mode = mode_T;
+ rt_uDiv.res_mode = mode_Iu;
+ rt_uDiv.mem_proj_nr = pn_Div_M;
+ rt_uDiv.regular_proj_nr = pn_Div_X_regular;
+ rt_uDiv.exc_proj_nr = pn_Div_X_except;
+ rt_uDiv.exc_mem_proj_nr = pn_Div_M;
+ rt_uDiv.res_proj_nr = pn_Div_res;
- set_entity_visibility(rt_Div.ent, visibility_external_allocated);
+ set_entity_visibility(rt_uDiv.ent, visibility_external_allocated);
map_Div->kind = INTRINSIC_INSTR;
map_Div->op = op_Div;
map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Div->ctx = &rt_Div;
+ map_Div->ctx = &rt_uDiv;
}
/* ... nor a signed mod instruction ... */
{
- runtime_rt rt_Mod;
i_instr_record *map_Mod = &records[n_records++].i_instr;
tp = new_type_method(ID("rt_iMod"), 2, 1);
set_method_param_type(tp, 1, int_tp);
set_method_res_type(tp, 0, int_tp);
- rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
- rt_Mod.mode = mode_T;
- rt_Mod.res_mode = mode_Is;
- rt_Mod.mem_proj_nr = pn_Mod_M;
- rt_Mod.regular_proj_nr = pn_Mod_X_regular;
- rt_Mod.exc_proj_nr = pn_Mod_X_except;
- rt_Mod.exc_mem_proj_nr = pn_Mod_M;
- rt_Mod.res_proj_nr = pn_Mod_res;
+ rt_iMod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
+ set_entity_ld_ident(rt_iMod.ent, ID("__modsi3"));
+ rt_iMod.mode = mode_T;
+ rt_iMod.res_mode = mode_Is;
+ rt_iMod.mem_proj_nr = pn_Mod_M;
+ rt_iMod.regular_proj_nr = pn_Mod_X_regular;
+ rt_iMod.exc_proj_nr = pn_Mod_X_except;
+ rt_iMod.exc_mem_proj_nr = pn_Mod_M;
+ rt_iMod.res_proj_nr = pn_Mod_res;
- set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
+ set_entity_visibility(rt_iMod.ent, visibility_external_allocated);
map_Mod->kind = INTRINSIC_INSTR;
map_Mod->op = op_Mod;
map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Mod->ctx = &rt_Mod;
+ map_Mod->ctx = &rt_iMod;
}
/* ... nor an unsigned mod. */
{
- runtime_rt rt_Mod;
i_instr_record *map_Mod = &records[n_records++].i_instr;
tp = new_type_method(ID("rt_uMod"), 2, 1);
set_method_param_type(tp, 1, uint_tp);
set_method_res_type(tp, 0, uint_tp);
- rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
- rt_Mod.mode = mode_T;
- rt_Mod.res_mode = mode_Iu;
- rt_Mod.mem_proj_nr = pn_Mod_M;
- rt_Mod.regular_proj_nr = pn_Mod_X_regular;
- rt_Mod.exc_proj_nr = pn_Mod_X_except;
- rt_Mod.exc_mem_proj_nr = pn_Mod_M;
- rt_Mod.res_proj_nr = pn_Mod_res;
+ rt_uMod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
+ set_entity_ld_ident(rt_uMod.ent, ID("__umodsi3"));
+ rt_uMod.mode = mode_T;
+ rt_uMod.res_mode = mode_Iu;
+ rt_uMod.mem_proj_nr = pn_Mod_M;
+ rt_uMod.regular_proj_nr = pn_Mod_X_regular;
+ rt_uMod.exc_proj_nr = pn_Mod_X_except;
+ rt_uMod.exc_mem_proj_nr = pn_Mod_M;
+ rt_uMod.res_proj_nr = pn_Mod_res;
- set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
+ set_entity_visibility(rt_uMod.ent, visibility_external_allocated);
map_Mod->kind = INTRINSIC_INSTR;
map_Mod->op = op_Mod;
map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Mod->ctx = &rt_Mod;
+ map_Mod->ctx = &rt_uMod;
}
if (n_records > 0)
- lower_intrinsics(records, n_records);
+ lower_intrinsics(records, n_records, /*part_block_used=*/0);
}
/*****************************************************************
0, /* use generic register names instead of SP, LR, PC */
ARM_FPU_ARCH_FPE, /* FPU architecture */
NULL, /* current code generator */
- NULL_EMITTER, /* emitter environment */
};
/**
arm_register_init();
isa->cg = NULL;
- be_emit_init_env(&isa->emit, file_handle);
+ be_emit_init(file_handle);
arm_create_opcodes();
- arm_register_copy_attr_func();
arm_handle_intrinsics();
/* we mark referenced global entities, so we can only emit those which
static void arm_done(void *self) {
arm_isa_t *isa = self;
- be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
+ be_gas_emit_decls(isa->arch_isa.main_env, 1);
- be_emit_destroy_env(&isa->emit);
+ be_emit_exit();
free(self);
}
* here to speed up register allocation (and makes dumps
* smaller and more readable).
*/
-static int arm_get_n_reg_class(const void *self) {
- const arm_isa_t *isa = self;
-
- /* ARGH! is called BEFORE transform */
- return 2;
- return isa->cg->have_fp_insn ? 2 : 1;
+static unsigned arm_get_n_reg_class(const void *self) {
+ (void) self;
+ return N_CLASSES;
}
/**
* Return the register class with requested index.
*/
-static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
+static const arch_register_class_t *arm_get_reg_class(const void *self,
+ unsigned i) {
(void) self;
- return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
+ assert(i < N_CLASSES);
+ return &arm_reg_classes[i];
}
/**
* @return A register class which can hold values of the given mode.
*/
const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
+ (void) self;
if (mode_is_float(mode))
return &arm_reg_classes[CLASS_arm_fpa];
else
/**
* Produces the type which sits between the stack args and the locals on the stack.
* it will contain the return address and space to store the old base pointer.
- * @return The Firm type modelling the ABI between type.
+ * @return The Firm type modeling the ABI between type.
*/
static ir_type *arm_get_between_type(void *self) {
static ir_type *between_type = NULL;
static ir_entity *old_bp_ent = NULL;
+ (void) self;
- if(!between_type) {
+ if (between_type == NULL) {
ir_entity *ret_addr_ent;
ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
arm_abi_env_t *env = self;
ir_graph *irg = env->irg;
ir_node *block = get_irg_start_block(irg);
-// ir_node *regs[16];
-// int n_regs = 0;
arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
-// ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
-// ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
-// ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
-// ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
- if(env->flags.try_omit_fp)
+ if (env->flags.try_omit_fp)
return env->isa->sp;
- ip = be_new_Copy(gp, irg, block, sp );
+ ip = be_new_Copy(gp, irg, block, sp);
arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
-// if (r0) regs[n_regs++] = r0;
-// if (r1) regs[n_regs++] = r1;
-// if (r2) regs[n_regs++] = r2;
-// if (r3) regs[n_regs++] = r3;
-// sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
-// set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
-// arch_set_irn_register(env->arch_env, sp, env->isa->sp);
store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
- // TODO
- // set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
- // arch_set_irn_register(env->arch_env, store, env->isa->sp);
sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
arch_set_irn_register(env->arch_env, sp, env->isa->sp);
fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
new_tarval_from_long(4, get_irn_mode(fp)));
- // TODO...
- //set_arm_req_out_all(fp, fp_req);
- //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
arch_set_irn_register(env->arch_env, fp, env->isa->bp);
-// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
-// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
-// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
-// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
be_abi_reg_map_set(reg_map, env->isa->bp, fp);
be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
be_abi_reg_map_set(reg_map, env->isa->sp, sp);
return env->isa->bp;
}
+/**
+ * Builds the ARM epilogue
+ */
static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
arm_abi_env_t *env = self;
ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
// TODO: Activate Omit fp in epilogue
- if(env->flags.try_omit_fp) {
+ if (env->flags.try_omit_fp) {
curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
add_irn_dep(curr_sp, *mem);
0, /* store arguments sequential */
1, /* try to omit the frame pointer */
1, /* the function can use any register as frame pointer */
- 1 /* a call can take the callee's address as an immediate */
+ 1, /* a call can take the callee's address as an immediate */
+ 0, /* IRG is a leaf function */
+ 0 /* Set to one, if there is already enough room on the stack for call args. */
}
};
+ (void) self;
/* set stack parameter passing style */
be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
for (i = 0; i < n; i++) {
/* reg = get reg for param i; */
/* be_abi_call_param_reg(abi, i, reg); */
- if (i < 4)
-
+ if (i < 4) {
be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
- else
- be_abi_call_param_stack(abi, i, 4, 0, 0);
+ } else {
+ tp = get_method_param_type(method_type, i);
+ mode = get_type_mode(tp);
+ be_abi_call_param_stack(abi, i, mode, 4, 0, 0);
+ }
}
/* set return registers */
}
static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
+ (void) self;
+ (void) irn;
return &arm_irn_ops;
}
};
const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
+ (void) self;
return &arm_irn_handler;
}
int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
+ (void) block_env;
if(!is_arm_irn(irn))
return -1;
* Initializes the code generator interface.
*/
static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) {
+ (void) self;
return &arm_code_gen_if;
}
* Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
*/
static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
- memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
+ (void) self;
+ memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
+ /* arm_sched_selector.exectime = arm_sched_exectime; */
arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
return &arm_sched_selector;
+
}
static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
+ (void) self;
return NULL;
}
* Returns the necessary byte alignment for storing a register of given class.
*/
static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
+ (void) self;
+ (void) cls;
/* ARM is a 32 bit CPU, no need for other alignment */
return 4;
}
static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
+ (void) self;
+ (void) irn;
/* TODO */
assert(0);
return NULL;
}
static const be_machine_t *arm_get_machine(const void *self) {
+ (void) self;
/* TODO */
assert(0);
return NULL;
* Return irp irgs in the desired order.
*/
static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
+ (void) self;
+ (void) irg_list;
return NULL;
}
+/**
+ * Allows or disallows the creation of Psi nodes for the given Phi nodes.
+ * @return 1 if allowed, 0 otherwise
+ */
+static int arm_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) {
+ ir_node *cmp, *cmp_a, *phi;
+ ir_mode *mode;
+
+
+ /* currently Psi support is not implemented */
+ return 0;
+
+/* we don't want long long Psi */
+#define IS_BAD_PSI_MODE(mode) (!mode_is_float(mode) && get_mode_size_bits(mode) > 32)
+
+ if (get_irn_mode(sel) != mode_b)
+ return 0;
+
+ cmp = get_Proj_pred(sel);
+ cmp_a = get_Cmp_left(cmp);
+ mode = get_irn_mode(cmp_a);
+
+ if (IS_BAD_PSI_MODE(mode))
+ return 0;
+
+ /* check the Phi nodes */
+ for (phi = phi_list; phi; phi = get_irn_link(phi)) {
+ ir_node *pred_i = get_irn_n(phi, i);
+ ir_node *pred_j = get_irn_n(phi, j);
+ ir_mode *mode_i = get_irn_mode(pred_i);
+ ir_mode *mode_j = get_irn_mode(pred_j);
+
+ if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
+ return 0;
+ }
+
+#undef IS_BAD_PSI_MODE
+
+ return 1;
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
static const backend_params *arm_get_libfirm_params(void) {
- static arch_dep_params_t ad = {
- 1, /* allow subs */
- 1, /* Muls are fast enough on ARM but ... */
- 1, /* ... one shift would be possible better */
- 0, /* SMUL is needed, only in Arch M*/
- 0, /* UMUL is needed, only in Arch M */
- 32, /* SMUL & UMUL available for 32 bit */
+ static const ir_settings_if_conv_t ifconv = {
+ 4, /* maxdepth, doesn't matter for Psi-conversion */
+ arm_is_psi_allowed /* allows or disallows Psi creation for given selector */
+ };
+ static ir_settings_arch_dep_t ad = {
+ 1, /* allow subs */
+ 1, /* Muls are fast enough on ARM but ... */
+ 31, /* ... one shift would be possible better */
+ NULL, /* no evaluator function */
+ 0, /* SMUL is needed, only in Arch M */
+ 0, /* UMUL is needed, only in Arch M */
+ 32, /* SMUL & UMUL available for 32 bit */
};
static backend_params p = {
1, /* need dword lowering */
NULL, /* will be set later */
NULL, /* but yet no creator function */
NULL, /* context for create_intrinsic_fkt */
- NULL, /* no if conversion settings */
+ NULL, /* will be set below */
};
- p.dep_param = &ad;
+ p.dep_param = &ad;
+ p.if_conv_info = &ifconv;
return &p;
}
static const lc_opt_table_entry_t arm_options[] = {
LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
- { NULL }
+ LC_OPT_LAST
};
const arch_isa_if_t arm_isa_if = {
be_register_isa_if("arm", &arm_isa_if);
arm_init_transform();
+ arm_init_emitter();
}
BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
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