#include "config.h"
#endif
+#include <libcore/lc_opts.h>
+#include <libcore/lc_opts_enum.h>
+
#include "pseudo_irg.h"
#include "irgwalk.h"
#include "irprog.h"
#include "../besched_t.h"
#include "../be.h"
#include "../beabi.h"
+#include "../bemachine.h"
+#include "../beilpsched.h"
+#include "../bemodule.h"
#include "bearch_arm_t.h"
* |___/
**************************************************/
-static ir_node *my_skip_proj(const ir_node *n) {
- while (is_Proj(n))
- n = get_Proj_pred(n);
- return (ir_node *)n;
-}
-
/**
* Return register requirements for a arm node.
* If the node returns a tuple (mode_T) then the proj's
* will be asked for this information.
*/
-static const arch_register_req_t *arm_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
- const arm_register_req_t *irn_req;
+static const
+arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
+ int pos) {
long node_pos = pos == -1 ? 0 : pos;
- ir_mode *mode = get_irn_mode(irn);
- firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
+ ir_mode *mode = get_irn_mode(node);
+ FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
- if (is_Block(irn) || mode == mode_X || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
- return NULL;
+ if (is_Block(node) || mode == mode_X || mode == mode_M) {
+ DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", node));
+ return arch_no_register_req;
}
if (mode == mode_T && pos < 0) {
- DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
- return NULL;
+ DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", node));
+ return arch_no_register_req;
}
- DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
+ DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, node));
- if (is_Proj(irn)) {
+ if (is_Proj(node)) {
/* in case of a proj, we need to get the correct OUT slot */
/* of the node corresponding to the proj number */
if (pos == -1) {
- node_pos = arm_translate_proj_pos(irn);
+ node_pos = arm_translate_proj_pos(node);
}
else {
node_pos = pos;
}
- irn = my_skip_proj(irn);
+ node = skip_Proj_const(node);
- DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
+ DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", node, node_pos));
}
/* get requirements for our own nodes */
- if (is_arm_irn(irn)) {
+ if (is_arm_irn(node)) {
+ const arch_register_req_t *req;
if (pos >= 0) {
- irn_req = get_arm_in_req(irn, pos);
+ req = get_arm_in_req(node, pos);
+ } else {
+ req = get_arm_out_req(node, node_pos);
}
- else {
- irn_req = get_arm_out_req(irn, node_pos);
- }
-
- DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
-
- memcpy(req, &(irn_req->req), sizeof(*req));
- if (arch_register_req_is(&(irn_req->req), should_be_same)) {
- assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
- req->other_same = get_irn_n(irn, irn_req->same_pos);
- }
-
- if (arch_register_req_is(&(irn_req->req), should_be_different)) {
- assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
- req->other_different = get_irn_n(irn, irn_req->different_pos);
- }
+ DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", node, pos));
+ return req;
}
- /* get requirements for FIRM nodes */
- else {
- /* treat Phi like Const with default requirements */
- if (is_Phi(irn)) {
- DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
- if (mode_is_float(mode)) {
- memcpy(req, &(arm_default_req_arm_floating_point.req), sizeof(*req));
- }
- else if (mode_is_int(mode) || mode_is_reference(mode)) {
- memcpy(req, &(arm_default_req_arm_general_purpose.req), sizeof(*req));
- }
- else if (mode == mode_T || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
- return NULL;
- }
- else {
- assert(0 && "unsupported Phi-Mode");
- }
- }
- else {
- DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
- req = NULL;
- }
- }
+ /* unknown should be tranformed by now */
+ assert(!is_Unknown(node));
+ DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", node));
- return req;
+ return arch_no_register_req;
}
static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
}
pos = arm_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
+ irn = skip_Proj(irn);
}
if (is_arm_irn(irn)) {
}
pos = arm_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
+ irn = skip_Proj_const(irn);
}
if (is_arm_irn(irn)) {
}
static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
- irn = my_skip_proj(irn);
+ irn = skip_Proj_const(irn);
if (is_cfop(irn)) {
return arch_irn_class_branch;
}
static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
- irn = my_skip_proj(irn);
+ irn = skip_Proj_const(irn);
if (is_arm_irn(irn)) {
return get_arm_flags(irn);
return 0;
}
-static entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
+static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
/* TODO: return the entity assigned to the frame */
return NULL;
}
+static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
+ /* TODO: set the entity assigned to the frame */
+}
+
/**
* This function is called by the generic backend to correct offsets for
* nodes accessing the stack.
/* TODO: correct offset if irn accesses the stack */
}
+static int arm_get_sp_bias(const void *self, const ir_node *irn) {
+ return 0;
+}
+
/* fill register allocator interface */
static const arch_irn_ops_if_t arm_irn_ops_if = {
arm_classify,
arm_get_flags,
arm_get_frame_entity,
- arm_set_stack_bias
+ arm_set_frame_entity,
+ arm_set_stack_bias,
+ arm_get_sp_bias,
+ NULL, /* get_inverse */
+ NULL, /* get_op_estimated_cost */
+ NULL, /* possible_memory_operand */
+ NULL, /* perform_memory_operand */
};
arm_irn_ops_t arm_irn_ops = {
**************************************************/
/**
- * Transforms the standard firm graph into
- * a ARM firm graph
+ * Transforms the standard Firm graph into
+ * a ARM firm graph.
*/
static void arm_prepare_graph(void *self) {
arm_code_gen_t *cg = self;
+ arm_register_transformers();
irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
}
/**
* Called immediately before emit phase.
*/
-static void arm_finish_irg(ir_graph *irg, arm_code_gen_t *cg) {
+static void arm_finish_irg(void *self) {
/* TODO: - fix offsets for nodes accessing stack
- ...
*/
static void arm_emit_and_done(void *self) {
arm_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
- FILE *out = cg->out;
+ FILE *out = cg->isa->out;
if (cg->emit_decls) {
- arm_gen_decls(cg->out);
+ arm_gen_decls(out);
cg->emit_decls = 0;
}
- arm_finish_irg(irg, cg);
dump_ir_block_graph_sched(irg, "-arm-finished");
arm_gen_routine(out, irg, cg);
free(self);
}
-enum convert_which { low, high };
+/**
+ * Move a double floating point value into an integer register.
+ * Place the move operation into block bl.
+ *
+ * Handle some special cases here:
+ * 1.) A constant: simply split into two
+ * 2.) A load: siply split into two
+ */
+static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
+ ir_node **resH, ir_node **resL) {
+ if (is_Const(arg)) {
+ tarval *tv = get_Const_tarval(arg);
+ unsigned v;
+
+ /* get the upper 32 bits */
+ v = get_tarval_sub_bits(tv, 7);
+ v = (v << 8) | get_tarval_sub_bits(tv, 6);
+ v = (v << 8) | get_tarval_sub_bits(tv, 5);
+ v = (v << 8) | get_tarval_sub_bits(tv, 4);
+ *resH = new_Const_long(mode_Is, v);
+
+ /* get the lower 32 bits */
+ v = get_tarval_sub_bits(tv, 3);
+ v = (v << 8) | get_tarval_sub_bits(tv, 2);
+ v = (v << 8) | get_tarval_sub_bits(tv, 1);
+ v = (v << 8) | get_tarval_sub_bits(tv, 0);
+ *resL = new_Const_long(mode_Is, v);
+ }
+ else if (get_irn_op(skip_Proj(arg)) == op_Load) {
+ /* FIXME: handling of low/high depends on LE/BE here */
+ assert(0);
+ }
+ else {
+ ir_graph *irg = current_ir_graph;
+ ir_node *conv;
+
+ conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
+ /* move high/low */
+ *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
+ *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
+ mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
+ }
+ return mem;
+}
/**
- * Move an floating point value to a integer register.
+ * Move a single floating point value into an integer register.
* Place the move operation into block bl.
+ *
+ * Handle some special cases here:
+ * 1.) A constant: simply move
+ * 2.) A load: siply load
*/
-static ir_node *convert_to_int(ir_node *bl, ir_node *arg, enum convert_which which) {
+static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
+ if (is_Const(arg)) {
+ tarval *tv = get_Const_tarval(arg);
+ unsigned v;
+
+ /* get the lower 32 bits */
+ v = get_tarval_sub_bits(tv, 3);
+ v = (v << 8) | get_tarval_sub_bits(tv, 2);
+ v = (v << 8) | get_tarval_sub_bits(tv, 1);
+ v = (v << 8) | get_tarval_sub_bits(tv, 0);
+ return new_Const_long(mode_Is, v);
+ }
+ else if (get_irn_op(skip_Proj(arg)) == op_Load) {
+ ir_node *load;
+
+ load = skip_Proj(arg);
+ }
+ assert(0);
return NULL;
}
/**
* Convert the arguments of a call to support the
* ARM calling convention of general purpose AND floating
- * point arguments
+ * point arguments.
*/
static void handle_calls(ir_node *call, void *env)
{
if (mode_is_float(mode)) {
if (get_mode_size_bits(mode) > 32) {
+ ir_node *mem = get_Call_mem(call);
+
+ /* Beware: ARM wants the high part first */
size += 2 * 4;
- new_tp[idx] = cg->int_tp;
- new_in[idx] = convert_to_int(bl, get_Call_param(call, i), low);
- ++idx;
- new_tp[idx] = cg->int_tp;
- new_in[idx] = convert_to_int(bl, get_Call_param(call, i), high);
- ++idx;
+ new_tp[idx] = cg->int_tp;
+ new_tp[idx+1] = cg->int_tp;
+ mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]);
+ idx += 2;
+ set_Call_mem(call, mem);
}
else {
size += 4;
new_tp[idx] = cg->int_tp;
- new_in[idx] = convert_to_int(bl, get_Call_param(call, i), low);
+ new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i));
++idx;
}
flag = 1;
}
/**
- * Handle graph transformations before the abi converter does it's work
+ * Handle graph transformations before the abi converter does its work.
*/
static void arm_before_abi(void *self) {
arm_code_gen_t *cg = self;
irg_walk_graph(cg->irg, NULL, handle_calls, cg);
}
-static void *arm_cg_init(FILE *F, const be_irg_t *birg);
+static void *arm_cg_init(be_irg_t *birg);
static const arch_code_generator_if_t arm_code_gen_if = {
arm_cg_init,
- arm_before_abi, /* before abi introduce */
+ arm_before_abi, /* before abi introduce */
arm_prepare_graph,
+ NULL, /* spill */
arm_before_sched, /* before scheduling hook */
arm_before_ra, /* before register allocation hook */
- NULL, /* after register allocation */
+ NULL, /* after register allocation */
+ arm_finish_irg,
arm_emit_and_done,
};
/**
* Initializes the code generator.
*/
-static void *arm_cg_init(FILE *F, const be_irg_t *birg) {
+static void *arm_cg_init(be_irg_t *birg) {
static ir_type *int_tp = NULL;
arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
arm_code_gen_t *cg;
- if (! int_tp) {
+ if (! int_tp) {
/* create an integer type with machine size */
int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
}
cg->impl = &arm_code_gen_if;
cg->irg = birg->irg;
cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
- cg->mod = firm_dbg_register("firm.be.arm.cg");
- cg->out = F;
cg->arch_env = birg->main_env->arch_env;
+ cg->isa = isa;
cg->birg = birg;
cg->int_tp = int_tp;
+ cg->have_fp = 0;
+
+ FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
isa->num_codegens++;
arm_irn_ops.cg = cg;
+ /* enter the current code generator */
+ isa->cg = cg;
+
return (arch_code_generator_t *)cg;
}
* and map all instructions the backend did not support
* to runtime calls.
*/
-void arm_global_init(void) {
+static void arm_handle_intrinsics(void) {
ir_type *tp, *int_tp, *uint_tp;
i_record records[8];
int n_records = 0;
int_tp = new_type_primitive(ID("int"), mode_Is);
uint_tp = new_type_primitive(ID("uint"), mode_Iu);
+ /* ARM has neither a signed div instruction ... */
{
runtime_rt rt_Div;
i_instr_record *map_Div = &records[n_records++].i_instr;
map_Div->kind = INTRINSIC_INSTR;
map_Div->op = op_Div;
- map_Div->i_mapper = i_mapper_RuntimeCall;
+ map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
map_Div->ctx = &rt_Div;
}
+ /* ... nor a signed div instruction ... */
{
runtime_rt rt_Div;
i_instr_record *map_Div = &records[n_records++].i_instr;
map_Div->kind = INTRINSIC_INSTR;
map_Div->op = op_Div;
- map_Div->i_mapper = i_mapper_RuntimeCall;
+ map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
map_Div->ctx = &rt_Div;
}
+ /* ... nor a signed mod instruction ... */
{
runtime_rt rt_Mod;
i_instr_record *map_Mod = &records[n_records++].i_instr;
map_Mod->kind = INTRINSIC_INSTR;
map_Mod->op = op_Mod;
- map_Mod->i_mapper = i_mapper_RuntimeCall;
+ map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
map_Mod->ctx = &rt_Mod;
}
+ /* ... nor a unsigned mod. */
{
runtime_rt rt_Mod;
i_instr_record *map_Mod = &records[n_records++].i_instr;
map_Mod->kind = INTRINSIC_INSTR;
map_Mod->op = op_Mod;
- map_Mod->i_mapper = i_mapper_RuntimeCall;
+ map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
map_Mod->ctx = &rt_Mod;
}
*****************************************************************/
static arm_isa_t arm_isa_template = {
- &arm_isa_if, /* isa interface */
- &arm_general_purpose_regs[REG_R13], /* stack pointer */
- &arm_general_purpose_regs[REG_R11], /* base pointer */
- -1, /* stack direction */
- 0 /* number of codegenerator objects */
+ &arm_isa_if, /* isa interface */
+ &arm_gp_regs[REG_SP], /* stack pointer */
+ &arm_gp_regs[REG_R11], /* base pointer */
+ -1, /* stack direction */
+ 0, /* number of codegenerator objects */
+ 0, /* use generic register names instead of SP, LR, PC */
+ NULL, /* current code generator */
+ NULL, /* output file */
+ ARM_FPU_ARCH_FPE, /* FPU architecture */
};
/**
* Initializes the backend ISA and opens the output file.
*/
-static void *arm_init(void) {
+static void *arm_init(FILE *file_handle) {
static int inited = 0;
arm_isa_t *isa;
if(inited)
return NULL;
- isa = xcalloc(1, sizeof(*isa));
+ isa = xmalloc(sizeof(*isa));
memcpy(isa, &arm_isa_template, sizeof(*isa));
arm_register_init(isa);
+ if (isa->gen_reg_names) {
+ /* patch register names */
+ arm_gp_regs[REG_R11].name = "r11";
+ arm_gp_regs[REG_SP].name = "r13";
+ arm_gp_regs[REG_LR].name = "r14";
+ arm_gp_regs[REG_PC].name = "r15";
+ }
+
+ isa->cg = NULL;
+ isa->out = file_handle;
+
arm_create_opcodes();
+ arm_handle_intrinsics();
+ arm_switch_section(NULL, NO_SECTION);
inited = 1;
-
return isa;
}
/**
- * Closes the output file and frees the ISA structure.
+ * frees the ISA structure.
*/
static void arm_done(void *self) {
free(self);
}
-
+/**
+ * Report the number of register classes.
+ * If we don't have fp instructions, report only GP
+ * here to speed up register allocation (and makes dumps
+ * smaller and more readable).
+ */
static int arm_get_n_reg_class(const void *self) {
- return N_CLASSES;
+ const arm_isa_t *isa = self;
+
+ return isa->cg->have_fp ? 2 : 1;
}
+/**
+ * Return the register class with requested index.
+ */
static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
- assert(i >= 0 && i < N_CLASSES && "Invalid arm register class requested.");
- return &arm_reg_classes[i];
+ return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
}
-
-
/**
* Get the register class which shall be used to store a value of a given mode.
* @param self The this pointer.
*/
const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
if (mode_is_float(mode))
- return &arm_reg_classes[CLASS_arm_floating_point];
+ return &arm_reg_classes[CLASS_arm_fpa];
else
- return &arm_reg_classes[CLASS_arm_general_purpose];
+ return &arm_reg_classes[CLASS_arm_gp];
}
-
-
/**
* Produces the type which sits between the stack args and the locals on the stack.
* it will contain the return address and space to store the old base pointer.
*/
static ir_type *arm_get_between_type(void *self) {
static ir_type *between_type = NULL;
- static entity *old_bp_ent = NULL;
+ static ir_entity *old_bp_ent = NULL;
if(!between_type) {
- entity *ret_addr_ent;
+ ir_entity *ret_addr_ent;
ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
- set_entity_offset_bytes(old_bp_ent, 0);
- set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
+ set_entity_offset(old_bp_ent, 0);
+ set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
}
}
-
-
-
-
-
-
typedef struct {
be_abi_call_flags_bits_t flags;
const arch_env_t *arch_env;
static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
{
- arm_abi_env_t *env = xmalloc(sizeof(env[0]));
+ arm_abi_env_t *env = xmalloc(sizeof(env[0]));
be_abi_call_flags_t fl = be_abi_call_get_flags(call);
env->flags = fl.bits;
env->irg = irg;
static void arm_abi_dont_save_regs(void *self, pset *s)
{
arm_abi_env_t *env = self;
- if(env->flags.try_omit_fp)
+ if (env->flags.try_omit_fp)
pset_insert_ptr(s, env->isa->bp);
}
ir_node *block = get_irg_start_block(irg);
// ir_node *regs[16];
// int n_regs = 0;
- arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_general_purpose];
- static const arm_register_req_t *fp_req[] = {
- &arm_default_req_arm_general_purpose_r11
- };
+ arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
- ir_node *ip = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R12]);
+ ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
- ir_node *lr = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R14]);
- ir_node *pc = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R15]);
-// ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R0]);
-// ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R1]);
-// ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R2]);
-// ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R3]);
+ ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
+ ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
+// ir_node *r0 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R0]);
+// ir_node *r1 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R1]);
+// ir_node *r2 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R2]);
+// ir_node *r3 = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R3]);
if(env->flags.try_omit_fp)
return env->isa->sp;
ip = be_new_Copy(gp, irg, block, sp );
- arch_set_irn_register(env->arch_env, ip, &arm_general_purpose_regs[REG_R12]);
- be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_general_purpose_regs[REG_R12] );
+ arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
+ be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
// if (r0) regs[n_regs++] = r0;
// if (r1) regs[n_regs++] = r1;
// if (r2) regs[n_regs++] = r2;
// if (r3) regs[n_regs++] = r3;
// sp = new_r_arm_StoreStackMInc(irg, block, *mem, sp, n_regs, regs, get_irn_mode(sp));
-// set_arm_req_out(sp, &arm_default_req_arm_general_purpose_r13, 0);
+// set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
// arch_set_irn_register(env->arch_env, sp, env->isa->sp);
- store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem, mode_T);
- set_arm_req_out(store, &arm_default_req_arm_general_purpose_r13, 0);
-// arch_set_irn_register(env->arch_env, store, env->isa->sp);
+ store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
+ // TODO
+ // set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
+ // arch_set_irn_register(env->arch_env, store, env->isa->sp);
- sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, 0);
- arch_set_irn_register(env->arch_env, sp, env->isa->sp);
- *mem = new_r_Proj(irg, block, store, mode_M, 1);
+ sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
+ arch_set_irn_register(env->arch_env, sp, env->isa->sp);
+ *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
- be_node_set_reg_class(keep, 1, gp);
- arch_set_irn_register(env->arch_env, keep, &arm_general_purpose_regs[REG_R12]);
- be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_general_purpose_regs[REG_R12] );
-
- fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp) );
- set_arm_value(fp, new_tarval_from_long(4, mode_Iu));
- set_arm_req_out_all(fp, fp_req);
- //set_arm_req_out(fp, &arm_default_req_arm_general_purpose_r11, 0);
- arch_set_irn_register(env->arch_env, fp, env->isa->bp);
-
-// be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R0], r0);
-// be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R1], r1);
-// be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R2], r2);
-// be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R3], r3);
+ be_node_set_reg_class(keep, 1, gp);
+ arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
+ be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
+
+ fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
+ new_tarval_from_long(4, get_irn_mode(fp)));
+ // TODO...
+ //set_arm_req_out_all(fp, fp_req);
+ //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
+ arch_set_irn_register(env->arch_env, fp, env->isa->bp);
+
+// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
+// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
+// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R2], r2);
+// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R3], r3);
be_abi_reg_map_set(reg_map, env->isa->bp, fp);
- be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R12], keep);
+ be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
be_abi_reg_map_set(reg_map, env->isa->sp, sp);
- be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R14], lr);
- be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R15], pc);
+ be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
+ be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
return env->isa->bp;
}
arm_abi_env_t *env = self;
ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
- ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R15]);
- ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_general_purpose_regs[REG_R14]);
- static const arm_register_req_t *sub12_req[] = {
- &arm_default_req_arm_general_purpose_r13
- };
+ ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
+ ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
-// TODO: Activate Omit fp in epilogue
+ // TODO: Activate Omit fp in epilogue
if(env->flags.try_omit_fp) {
- curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
+ curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
+ add_irn_dep(curr_sp, *mem);
- curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_general_purpose], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
- be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_general_purpose]);
- arch_set_irn_register(env->arch_env, curr_lr, &arm_general_purpose_regs[REG_R14]);
- be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_general_purpose_regs[REG_R14] );
+ curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
+ be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
+ arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
+ be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
- curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_general_purpose], env->irg, bl, curr_lr );
- arch_set_irn_register(env->arch_env, curr_pc, &arm_general_purpose_regs[REG_R15]);
- be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_general_purpose_regs[REG_R15] );
+ curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
+ arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
+ be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
} else {
ir_node *sub12_node;
ir_node *load_node;
- sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu );
- set_arm_value(sub12_node, new_tarval_from_long(12,mode_Iu));
- set_arm_req_out_all(sub12_node, sub12_req);
+ tarval *tv = new_tarval_from_long(12,mode_Iu);
+ sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
+ // FIXME
+ //set_arm_req_out_all(sub12_node, sub12_req);
arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
- load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem, mode_T );
- set_arm_req_out(load_node, &arm_default_req_arm_general_purpose_r11, 0);
- set_arm_req_out(load_node, &arm_default_req_arm_general_purpose_r13, 1);
- set_arm_req_out(load_node, &arm_default_req_arm_general_purpose_r15, 2);
- curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, 0);
- curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, 1);
- curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, 2);
- *mem = new_r_Proj(env->irg, bl, load_node, mode_M, 3);
+ load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
+ // FIXME
+ //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
+ //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
+ //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
+ curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
+ curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
+ curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
+ *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
- arch_set_irn_register(env->arch_env, curr_pc, &arm_general_purpose_regs[REG_R15]);
+ arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
}
be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
- be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R14], curr_lr);
- be_abi_reg_map_set(reg_map, &arm_general_purpose_regs[REG_R15], curr_pc);
+ be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
+ be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
}
static const be_abi_callbacks_t arm_abi_callbacks = {
ir_mode *mode;
int i;
int n = get_method_n_params(method_type);
-// const arch_register_t *reg;
be_abi_call_flags_t flags = {
- 0, /* store from left to right */
- 0, /* store arguments sequential */
- 1, /* try to omit the frame pointer */
- 1, /* the function can use any register as frame pointer */
- 1 /* a call can take the callee's address as an immediate */
+ {
+ 0, /* store from left to right */
+ 0, /* store arguments sequential */
+ 1, /* try to omit the frame pointer */
+ 1, /* the function can use any register as frame pointer */
+ 1 /* a call can take the callee's address as an immediate */
+ }
};
/* set stack parameter passing style */
mode = get_type_mode(tp);
be_abi_call_res_reg(abi, 0,
- mode_is_float(mode) ? &arm_floating_point_regs[REG_F0] : &arm_general_purpose_regs[REG_R0]);
+ mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]);
}
}
/**
* Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
*/
-static const list_sched_selector_t *arm_get_list_sched_selector(const void *self) {
+static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
return &arm_sched_selector;
}
-#ifdef WITH_LIBCORE
-static void arm_register_options(lc_opt_entry_t *ent)
-{
+static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
+ return NULL;
+}
+
+/**
+ * Returns the necessary byte alignment for storing a register of given class.
+ */
+static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
+ ir_mode *mode = arch_register_class_mode(cls);
+ return get_mode_size_bytes(mode);
}
-#endif /* WITH_LIBCORE */
+
+static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
+ /* TODO */
+ assert(0);
+ return NULL;
+}
+
+static const be_machine_t *arm_get_machine(const void *self) {
+ /* TODO */
+ assert(0);
+ return NULL;
+}
+
+/**
+ * Return irp irgs in the desired order.
+ */
+static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
+ return NULL;
+}
+
+/**
+ * Returns the libFirm configuration parameter for this backend.
+ */
+static const backend_params *arm_get_libfirm_params(void) {
+ static arch_dep_params_t ad = {
+ 1, /* allow subs */
+ 0, /* Muls are fast enough on ARM */
+ 31, /* shift would be ok */
+ 0, /* SMUL is needed, only in Arch M*/
+ 0, /* UMUL is needed, only in Arch M */
+ 32, /* SMUL & UMUL available for 32 bit */
+ };
+ static backend_params p = {
+ NULL, /* no additional opcodes */
+ NULL, /* will be set later */
+ 1, /* need dword lowering */
+ NULL, /* but yet no creator function */
+ NULL, /* context for create_intrinsic_fkt */
+ };
+
+ p.dep_param = &ad;
+ return &p;
+}
+
+/* fpu set architectures. */
+static const lc_opt_enum_int_items_t arm_fpu_items[] = {
+ { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
+ { "fpe", ARM_FPU_ARCH_FPE },
+ { "fpa", ARM_FPU_ARCH_FPA },
+ { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
+ { "vfp1", ARM_FPU_ARCH_VFP_V1 },
+ { "vfp2", ARM_FPU_ARCH_VFP_V2 },
+ { NULL, 0 }
+};
+
+static lc_opt_enum_int_var_t arch_fpu_var = {
+ &arm_isa_template.fpu_arch, arm_fpu_items
+};
+
+static const lc_opt_table_entry_t arm_options[] = {
+ LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
+ LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
+ { NULL }
+};
const arch_isa_if_t arm_isa_if = {
-#ifdef WITH_LIBCORE
- arm_register_options,
-#endif
arm_init,
arm_done,
arm_get_n_reg_class,
arm_get_irn_handler,
arm_get_code_generator_if,
arm_get_list_sched_selector,
+ arm_get_ilp_sched_selector,
+ arm_get_reg_class_alignment,
+ arm_get_libfirm_params,
+ arm_get_allowed_execution_units,
+ arm_get_machine,
+ arm_get_irg_list,
};
+
+void be_init_arch_arm(void)
+{
+ lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
+ lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
+
+ lc_opt_add_table(arm_grp, arm_options);
+
+ be_register_isa_if("arm", &arm_isa_if);
+}
+
+BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
projects / libfirm / blobdiff