/*
- * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
- *
* This file is part of libFirm.
- *
- * This file may be distributed and/or modified under the terms of the
- * GNU General Public License version 2 as published by the Free Software
- * Foundation and appearing in the file LICENSE.GPL included in the
- * packaging of this file.
- *
- * Licensees holding valid libFirm Professional Edition licenses may use
- * this file in accordance with the libFirm Commercial License.
- * Agreement provided with the Software.
- *
- * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
- * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE.
+ * Copyright (C) 2012 University of Karlsruhe.
*/
/**
#include "arm_emitter.h"
#include "arm_map_regs.h"
-static arch_irn_class_t arm_classify(const ir_node *irn)
-{
- (void) irn;
- /* TODO: we should mark reload/spill instructions and classify them here */
- return arch_irn_class_none;
-}
-
static ir_entity *arm_get_frame_entity(const ir_node *irn)
{
const arm_attr_t *attr = get_arm_attr_const(irn);
/* fill register allocator interface */
static const arch_irn_ops_t arm_irn_ops = {
- arm_classify,
arm_get_frame_entity,
arm_set_stack_bias,
arm_get_sp_bias,
- NULL, /* get_inverse */
NULL, /* get_op_estimated_cost */
NULL, /* possible_memory_operand */
NULL, /* perform_memory_operand */
ir_node *proj;
ir_node *load;
- ir_node *sched_point = sched_prev(node);
-
load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
- sched_add_after(sched_point, load);
- sched_remove(node);
+ sched_replace(node, load);
proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
ir_node *val = get_irn_n(node, n_be_Spill_val);
ir_mode *mode = get_irn_mode(val);
ir_entity *entity = be_get_frame_entity(node);
- ir_node *sched_point;
ir_node *store;
- sched_point = sched_prev(node);
store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
true);
-
- sched_remove(node);
- sched_add_after(sched_point, store);
+ sched_replace(node, store);
exchange(node, store);
}
static void arm_after_ra_walker(ir_node *block, void *data)
{
- ir_node *node, *prev;
(void) data;
- for (node = sched_last(block); !sched_is_begin(node); node = prev) {
- prev = sched_prev(node);
-
+ sched_foreach_reverse_safe(block, node) {
if (be_is_Reload(node)) {
transform_Reload(node);
} else if (be_is_Spill(node)) {
be_sched_fix_flags(irg, &arm_reg_classes[CLASS_arm_flags], NULL, NULL);
}
-/**
- * Initializes the code generator.
- */
-static void arm_init_graph(ir_graph *irg)
-{
- (void) irg;
-}
-
-
/**
* Maps all intrinsic calls that the backend support
* and map all instructions the backend did not support
extern const arch_isa_if_t arm_isa_if;
static arm_isa_t arm_isa_template = {
{
- &arm_isa_if, /* isa interface */
+ &arm_isa_if, /* isa interface */
N_ARM_REGISTERS,
arm_registers,
N_ARM_CLASSES,
arm_reg_classes,
&arm_registers[REG_SP], /* stack pointer */
&arm_registers[REG_R11], /* base pointer */
- &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
- 2, /* power of two stack alignment for calls, 2^2 == 4 */
- NULL, /* main environment */
- 7, /* spill costs */
- 5, /* reload costs */
- true, /* we do have custom abi handling */
+ 2, /* power of two stack alignment for calls, 2^2 == 4 */
+ 7, /* spill costs */
+ 5, /* reload costs */
+ true, /* we do have custom abi handling */
},
- ARM_FPU_ARCH_FPE, /* FPU architecture */
+ ARM_FPU_ARCH_FPE, /* FPU architecture */
};
-/**
- * Initializes the backend ISA and opens the output file.
- */
-static arch_env_t *arm_init(const be_main_env_t *env)
+static void arm_init(void)
{
- arm_isa_t *isa = XMALLOC(arm_isa_t);
- *isa = arm_isa_template;
-
arm_register_init();
arm_create_opcodes(&arm_irn_ops);
- arm_handle_intrinsics();
+}
- be_gas_emit_types = false;
+static void arm_finish(void)
+{
+ arm_free_opcodes();
+}
+
+static arch_env_t *arm_begin_codegeneration(void)
+{
+ arm_isa_t *isa = XMALLOC(arm_isa_t);
+ *isa = arm_isa_template;
- be_emit_init(env->file_handle);
- be_gas_begin_compilation_unit(env);
+ be_gas_emit_types = false;
return &isa->base;
}
-
-
/**
* Closes the output file and frees the ISA structure.
*/
-static void arm_done(void *self)
+static void arm_end_codegeneration(void *self)
{
- arm_isa_t *isa = (arm_isa_t*)self;
-
- be_gas_end_compilation_unit(isa->base.main_env);
-
- be_emit_exit();
free(self);
}
static void arm_lower_for_target(void)
{
+ ir_mode *mode_gp = arm_reg_classes[CLASS_arm_gp].mode;
size_t i, n_irgs = get_irp_n_irgs();
/* lower compound param handling */
for (i = 0; i < n_irgs; ++i) {
ir_graph *irg = get_irp_irg(i);
- lower_switch(irg, 4, 256, false);
+ lower_switch(irg, 4, 256, mode_gp);
}
for (i = 0; i < n_irgs; ++i) {
const arch_isa_if_t arm_isa_if = {
arm_init,
- arm_lower_for_target,
- arm_done,
- NULL, /* handle_intrinsics */
- NULL,
+ arm_finish,
arm_get_libfirm_params,
- NULL, /* mark remat */
+ arm_lower_for_target,
arm_parse_asm_constraint,
arm_is_valid_clobber,
- arm_init_graph,
+ arm_begin_codegeneration,
+ arm_end_codegeneration,
+ NULL,
+ NULL, /* get call abi */
+ NULL, /* mark remat */
NULL, /* get_pic_base */
+ be_new_spill,
+ be_new_reload,
+ NULL, /* register_saved_by */
+
+ arm_handle_intrinsics, /* handle_intrinsics */
NULL, /* before_abi */
arm_prepare_graph,
arm_before_ra,
arm_finish_irg,
arm_gen_routine,
- NULL, /* register_saved_by */
- be_new_spill,
- be_new_reload,
};
BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm)
projects / libfirm / blobdiff