#include "config.h"
#endif
-#ifdef WITH_LIBCORE
#include <libcore/lc_opts.h>
#include <libcore/lc_opts_enum.h>
-#endif /* WITH_LIBCORE */
#include "pseudo_irg.h"
#include "irgwalk.h"
#include "bitset.h"
#include "debug.h"
-#include "../bearch.h" /* the general register allocator interface */
+#include "../bearch_t.h" /* the general register allocator interface */
#include "../benode_t.h"
#include "../belower.h"
#include "../besched_t.h"
#include "../be.h"
#include "../beabi.h"
+#include "../bemachine.h"
+#include "../beilpsched.h"
+#include "../bemodule.h"
+#include "../beirg_t.h"
#include "bearch_arm_t.h"
* |___/
**************************************************/
-static ir_node *my_skip_proj(const ir_node *n) {
- while (is_Proj(n))
- n = get_Proj_pred(n);
- return (ir_node *)n;
-}
-
/**
* Return register requirements for a arm node.
* If the node returns a tuple (mode_T) then the proj's
* will be asked for this information.
*/
-static const arch_register_req_t *arm_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
- const arm_register_req_t *irn_req;
+static const
+arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
+ int pos) {
long node_pos = pos == -1 ? 0 : pos;
- ir_mode *mode = get_irn_mode(irn);
+ ir_mode *mode = get_irn_mode(node);
FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
- if (is_Block(irn) || mode == mode_X || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
- return NULL;
+ if (is_Block(node) || mode == mode_X || mode == mode_M) {
+ DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", node));
+ return arch_no_register_req;
}
if (mode == mode_T && pos < 0) {
- DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
- return NULL;
+ DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", node));
+ return arch_no_register_req;
}
- DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
+ DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, node));
- if (is_Proj(irn)) {
+ if (is_Proj(node)) {
/* in case of a proj, we need to get the correct OUT slot */
/* of the node corresponding to the proj number */
if (pos == -1) {
- node_pos = arm_translate_proj_pos(irn);
+ node_pos = arm_translate_proj_pos(node);
}
else {
node_pos = pos;
}
- irn = my_skip_proj(irn);
+ node = skip_Proj_const(node);
- DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
+ DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", node, node_pos));
}
/* get requirements for our own nodes */
- if (is_arm_irn(irn)) {
+ if (is_arm_irn(node)) {
+ const arch_register_req_t *req;
if (pos >= 0) {
- irn_req = get_arm_in_req(irn, pos);
- }
- else {
- irn_req = get_arm_out_req(irn, node_pos);
+ req = get_arm_in_req(node, pos);
+ } else {
+ req = get_arm_out_req(node, node_pos);
}
- DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
-
- memcpy(req, &(irn_req->req), sizeof(*req));
-
- if (arch_register_req_is(&(irn_req->req), should_be_same)) {
- assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
- req->other_same = get_irn_n(irn, irn_req->same_pos);
- }
-
- if (arch_register_req_is(&(irn_req->req), should_be_different)) {
- assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
- req->other_different = get_irn_n(irn, irn_req->different_pos);
- }
+ DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", node, pos));
+ return req;
}
- /* get requirements for FIRM nodes */
- else {
- /* treat Phi like Const with default requirements */
- if (is_Phi(irn)) {
- DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
- if (mode_is_float(mode)) {
- memcpy(req, &(arm_default_req_arm_fpa.req), sizeof(*req));
- }
- else if (mode_is_int(mode) || mode_is_reference(mode)) {
- memcpy(req, &(arm_default_req_arm_gp.req), sizeof(*req));
- }
- else if (mode == mode_T || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
- return NULL;
- }
- else {
- assert(0 && "unsupported Phi-Mode");
- }
- }
- else {
- DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
- req = NULL;
- }
- }
+ /* unknown should be tranformed by now */
+ assert(!is_Unknown(node));
+ DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", node));
- return req;
+ return arch_no_register_req;
}
static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
}
pos = arm_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
+ irn = skip_Proj(irn);
}
if (is_arm_irn(irn)) {
}
pos = arm_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
+ irn = skip_Proj_const(irn);
}
if (is_arm_irn(irn)) {
}
static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
- irn = my_skip_proj(irn);
+ irn = skip_Proj_const(irn);
if (is_cfop(irn)) {
return arch_irn_class_branch;
}
static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
- irn = my_skip_proj(irn);
+ irn = skip_Proj_const(irn);
if (is_arm_irn(irn)) {
return get_arm_flags(irn);
return 0;
}
-static entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
+static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
/* TODO: return the entity assigned to the frame */
return NULL;
}
+static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
+ /* TODO: set the entity assigned to the frame */
+}
+
/**
* This function is called by the generic backend to correct offsets for
* nodes accessing the stack.
/* TODO: correct offset if irn accesses the stack */
}
+static int arm_get_sp_bias(const void *self, const ir_node *irn) {
+ return 0;
+}
+
/* fill register allocator interface */
static const arch_irn_ops_if_t arm_irn_ops_if = {
arm_classify,
arm_get_flags,
arm_get_frame_entity,
+ arm_set_frame_entity,
arm_set_stack_bias,
- NULL
+ arm_get_sp_bias,
+ NULL, /* get_inverse */
+ NULL, /* get_op_estimated_cost */
+ NULL, /* possible_memory_operand */
+ NULL, /* perform_memory_operand */
};
arm_irn_ops_t arm_irn_ops = {
irg_walk_graph(cg->irg, NULL, handle_calls, cg);
}
-static void *arm_cg_init(const be_irg_t *birg);
+static void *arm_cg_init(be_irg_t *birg);
static const arch_code_generator_if_t arm_code_gen_if = {
arm_cg_init,
arm_before_abi, /* before abi introduce */
arm_prepare_graph,
+ NULL, /* spill */
arm_before_sched, /* before scheduling hook */
arm_before_ra, /* before register allocation hook */
NULL, /* after register allocation */
/**
* Initializes the code generator.
*/
-static void *arm_cg_init(const be_irg_t *birg) {
+static void *arm_cg_init(be_irg_t *birg) {
static ir_type *int_tp = NULL;
arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
arm_code_gen_t *cg;
*/
static ir_type *arm_get_between_type(void *self) {
static ir_type *between_type = NULL;
- static entity *old_bp_ent = NULL;
+ static ir_entity *old_bp_ent = NULL;
if(!between_type) {
- entity *ret_addr_ent;
+ ir_entity *ret_addr_ent;
ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
- set_entity_offset_bytes(old_bp_ent, 0);
- set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
+ set_entity_offset(old_bp_ent, 0);
+ set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
}
// ir_node *regs[16];
// int n_regs = 0;
arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
- static const arm_register_req_t *fp_req[] = {
- &arm_default_req_arm_gp_r11
- };
ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
// set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
// arch_set_irn_register(env->arch_env, sp, env->isa->sp);
store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
- set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
-// arch_set_irn_register(env->arch_env, store, env->isa->sp);
+ // TODO
+ // set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
+ // arch_set_irn_register(env->arch_env, store, env->isa->sp);
sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
- arch_set_irn_register(env->arch_env, sp, env->isa->sp);
+ arch_set_irn_register(env->arch_env, sp, env->isa->sp);
*mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
- be_node_set_reg_class(keep, 1, gp);
- arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
- be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
+ be_node_set_reg_class(keep, 1, gp);
+ arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
+ be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
new_tarval_from_long(4, get_irn_mode(fp)));
- set_arm_req_out_all(fp, fp_req);
- //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
- arch_set_irn_register(env->arch_env, fp, env->isa->bp);
+ // TODO...
+ //set_arm_req_out_all(fp, fp_req);
+ //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
+ arch_set_irn_register(env->arch_env, fp, env->isa->bp);
// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
- static const arm_register_req_t *sub12_req[] = {
- &arm_default_req_arm_gp_sp
- };
-// TODO: Activate Omit fp in epilogue
+ // TODO: Activate Omit fp in epilogue
if(env->flags.try_omit_fp) {
- curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
+ curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
+ add_irn_dep(curr_sp, *mem);
curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
ir_node *load_node;
tarval *tv = new_tarval_from_long(12,mode_Iu);
sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
- set_arm_req_out_all(sub12_node, sub12_req);
+ // FIXME
+ //set_arm_req_out_all(sub12_node, sub12_req);
arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
- set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
- set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
- set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
+ // FIXME
+ //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
+ //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
+ //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
/**
* Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
*/
-static const list_sched_selector_t *arm_get_list_sched_selector(const void *self) {
+static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
return &arm_sched_selector;
}
+static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
+ return NULL;
+}
+
/**
* Returns the necessary byte alignment for storing a register of given class.
*/
return get_mode_size_bytes(mode);
}
+static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
+ /* TODO */
+ assert(0);
+ return NULL;
+}
+
+static const be_machine_t *arm_get_machine(const void *self) {
+ /* TODO */
+ assert(0);
+ return NULL;
+}
+
+/**
+ * Return irp irgs in the desired order.
+ */
+static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
+ return NULL;
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
return &p;
}
-#ifdef WITH_LIBCORE
-
/* fpu set architectures. */
static const lc_opt_enum_int_items_t arm_fpu_items[] = {
{ "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
{ NULL }
};
-/**
- * Register command line options for the ARM backend.
- *
- * Options so far:
- *
- * arm-fpuunit=unit select the floating point unit
- * arm-gen_reg_names use generic register names instead of SP, LR, PC
- */
-static void arm_register_options(lc_opt_entry_t *ent)
-{
- lc_opt_entry_t *be_grp_arm = lc_opt_get_grp(ent, "arm");
- lc_opt_add_table(be_grp_arm, arm_options);
-}
-#endif /* WITH_LIBCORE */
-
const arch_isa_if_t arm_isa_if = {
arm_init,
arm_done,
arm_get_irn_handler,
arm_get_code_generator_if,
arm_get_list_sched_selector,
+ arm_get_ilp_sched_selector,
arm_get_reg_class_alignment,
arm_get_libfirm_params,
-#ifdef WITH_LIBCORE
- arm_register_options
-#endif
+ arm_get_allowed_execution_units,
+ arm_get_machine,
+ arm_get_irg_list,
};
+
+void be_init_arch_arm(void)
+{
+ lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
+ lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
+
+ lc_opt_add_table(arm_grp, arm_options);
+
+ be_register_isa_if("arm", &arm_isa_if);
+}
+
+BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
projects / libfirm / blobdiff