/*
- * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
*
* This file is part of libFirm.
*
* @author Oliver Richter, Tobias Gneist
* @version $Id$
*/
-#ifdef HAVE_CONFIG_H
#include "config.h"
-#endif
-#include <libcore/lc_opts.h>
-#include <libcore/lc_opts_enum.h>
+#include "lc_opts.h"
+#include "lc_opts_enum.h"
#include "pseudo_irg.h"
#include "irgwalk.h"
#include "ircons.h"
#include "irgmod.h"
#include "irgopt.h"
+#include "iroptimize.h"
#include "lowering.h"
+#include "error.h"
#include "bitset.h"
#include "debug.h"
+#include "array_t.h"
#include "irtools.h"
#include "../bearch_t.h" /* the general register allocator interface */
#include "arm_new_nodes.h" /* arm nodes interface */
#include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
#include "arm_transform.h"
+#include "arm_optimize.h"
#include "arm_emitter.h"
#include "arm_map_regs.h"
* If the node returns a tuple (mode_T) then the proj's
* will be asked for this information.
*/
-static const
-arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
- int pos)
+static const arch_register_req_t *arm_get_irn_reg_req(const ir_node *node,
+ int pos)
{
long node_pos = pos == -1 ? 0 : pos;
ir_mode *mode = get_irn_mode(node);
- (void) self;
if (is_Block(node) || mode == mode_X) {
return arch_no_register_req;
return arch_no_register_req;
}
-static void arm_set_irn_reg(const void *self, ir_node *irn,
- const arch_register_t *reg)
-{
- int pos = 0;
- (void) self;
-
- if (get_irn_mode(irn) == mode_X) {
- return;
- }
-
- if (is_Proj(irn)) {
- pos = get_Proj_proj(irn);
- irn = skip_Proj(irn);
- }
-
- if (is_arm_irn(irn)) {
- const arch_register_t **slots;
-
- slots = get_arm_slots(irn);
- slots[pos] = reg;
- }
- else {
- /* here we set the registers for the Phi nodes */
- arm_set_firm_reg(irn, reg, cur_reg_set);
- }
-}
-
-static const arch_register_t *arm_get_irn_reg(const void *self,
- const ir_node *irn)
-{
- int pos = 0;
- const arch_register_t *reg = NULL;
- (void) self;
-
- if (is_Proj(irn)) {
-
- if (get_irn_mode(irn) == mode_X) {
- return NULL;
- }
-
- pos = get_Proj_proj(irn);
- irn = skip_Proj_const(irn);
- }
-
- if (is_arm_irn(irn)) {
- const arch_register_t **slots;
- slots = get_arm_slots(irn);
- reg = slots[pos];
- }
- else {
- reg = arm_get_firm_reg(irn, cur_reg_set);
- }
-
- return reg;
-}
-
-static arch_irn_class_t arm_classify(const void *self, const ir_node *irn)
+static arch_irn_class_t arm_classify(const ir_node *irn)
{
- (void) self;
irn = skip_Proj_const(irn);
if (is_cfop(irn)) {
return arch_irn_class_branch;
}
- else if (is_arm_irn(irn)) {
- return arch_irn_class_normal;
- }
return 0;
}
-static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn)
-{
- (void) self;
- irn = skip_Proj_const(irn);
-
- if (is_arm_irn(irn)) {
- return get_arm_flags(irn);
- }
- else if (is_Unknown(irn)) {
- return arch_irn_flags_ignore;
- }
-
- return 0;
-}
-
-static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn)
-{
- (void) self;
+static ir_entity *arm_get_frame_entity(const ir_node *irn) {
+ /* we do NOT transform be_Spill or be_Reload nodes, so we never
+ have frame access using ARM nodes. */
(void) irn;
- /* TODO: return the entity assigned to the frame */
return NULL;
}
-static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent)
-{
- (void) self;
+static void arm_set_frame_entity(ir_node *irn, ir_entity *ent) {
(void) irn;
(void) ent;
- /* TODO: set the entity assigned to the frame */
+ panic("arm_set_frame_entity() called. This should not happen.");
}
/**
* This function is called by the generic backend to correct offsets for
* nodes accessing the stack.
*/
-static void arm_set_stack_bias(const void *self, ir_node *irn, int bias)
+static void arm_set_stack_bias(ir_node *irn, int bias)
{
- (void) self;
(void) irn;
(void) bias;
/* TODO: correct offset if irn accesses the stack */
}
-static int arm_get_sp_bias(const void *self, const ir_node *irn)
+static int arm_get_sp_bias(const ir_node *irn)
{
- (void) self;
(void) irn;
return 0;
}
/* fill register allocator interface */
-static const arch_irn_ops_if_t arm_irn_ops_if = {
+static const arch_irn_ops_t arm_irn_ops = {
arm_get_irn_reg_req,
- arm_set_irn_reg,
- arm_get_irn_reg,
arm_classify,
- arm_get_flags,
arm_get_frame_entity,
arm_set_frame_entity,
arm_set_stack_bias,
NULL, /* perform_memory_operand */
};
-arm_irn_ops_t arm_irn_ops = {
- &arm_irn_ops_if,
- NULL
-};
-
-
-
/**************************************************
* _ _ __
* | | (_)/ _|
*/
static void arm_finish_irg(void *self)
{
- (void) self;
- /* TODO: - fix offsets for nodes accessing stack
- - ...
- */
-}
-
+ arm_code_gen_t *cg = self;
-/**
- * These are some hooks which must be filled but are probably not needed.
- */
-static void arm_before_sched(void *self)
-{
- (void) self;
- /* Some stuff you need to do after scheduling but before register allocation */
+ /* do peephole optimizations and fix stack offsets */
+ arm_peephole_optimization(cg);
}
+
static void arm_before_ra(void *self)
{
(void) self;
v = (v << 8) | get_tarval_sub_bits(tv, 1);
v = (v << 8) | get_tarval_sub_bits(tv, 0);
*resL = new_Const_long(mode_Is, v);
- }
- else if (get_irn_op(skip_Proj(arg)) == op_Load) {
+ } else if (is_Load(skip_Proj(arg))) {
/* FIXME: handling of low/high depends on LE/BE here */
- assert(0);
+ panic("Unimplemented convert_dbl_to_int() case");
}
else {
ir_graph *irg = current_ir_graph;
ir_node *conv;
- conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem);
+ conv = new_bd_arm_fpaDbl2GP(NULL, bl, arg, mem);
/* move high/low */
- *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
- *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
- mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
+ *resL = new_r_Proj(bl, conv, mode_Is, pn_arm_fpaDbl2GP_low);
+ *resH = new_r_Proj(bl, conv, mode_Is, pn_arm_fpaDbl2GP_high);
+ mem = new_r_Proj(bl, conv, mode_M, pn_arm_fpaDbl2GP_M);
}
return mem;
}
v = (v << 8) | get_tarval_sub_bits(tv, 1);
v = (v << 8) | get_tarval_sub_bits(tv, 0);
return new_Const_long(mode_Is, v);
- }
- else if (get_irn_op(skip_Proj(arg)) == op_Load) {
+ } else if (is_Load(skip_Proj(arg))) {
ir_node *load;
load = skip_Proj(arg);
}
- assert(0);
- return NULL;
+ panic("Unimplemented convert_sng_to_int() case");
}
/**
static const arch_code_generator_if_t arm_code_gen_if = {
arm_cg_init,
+ NULL, /* get_pic_base */
arm_before_abi, /* before abi introduce */
arm_prepare_graph,
NULL, /* spill */
- arm_before_sched, /* before scheduling hook */
arm_before_ra, /* before register allocation hook */
arm_after_ra,
arm_finish_irg,
*/
static void *arm_cg_init(be_irg_t *birg) {
static ir_type *int_tp = NULL;
- arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
+ arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env;
arm_code_gen_t *cg;
if (! int_tp) {
int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
}
- cg = xmalloc(sizeof(*cg));
+ cg = XMALLOC(arm_code_gen_t);
cg->impl = &arm_code_gen_if;
cg->irg = birg->irg;
cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
- cg->arch_env = birg->main_env->arch_env;
cg->isa = isa;
cg->birg = birg;
cg->int_tp = int_tp;
cur_reg_set = cg->reg_set;
- arm_irn_ops.cg = cg;
-
/* enter the current code generator */
isa->cg = cg;
&arm_isa_if, /* isa interface */
&arm_gp_regs[REG_SP], /* stack pointer */
&arm_gp_regs[REG_R11], /* base pointer */
+ &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
-1, /* stack direction */
+ 2, /* power of two stack alignment for calls, 2^2 == 4 */
NULL, /* main environment */
7, /* spill costs */
5, /* reload costs */
0, /* use generic register names instead of SP, LR, PC */
ARM_FPU_ARCH_FPE, /* FPU architecture */
NULL, /* current code generator */
- NULL_EMITTER, /* emitter environment */
};
/**
* Initializes the backend ISA and opens the output file.
*/
-static void *arm_init(FILE *file_handle) {
+static arch_env_t *arm_init(FILE *file_handle) {
static int inited = 0;
arm_isa_t *isa;
- if(inited)
+ if (inited)
return NULL;
- isa = xmalloc(sizeof(*isa));
+ isa = XMALLOC(arm_isa_t);
memcpy(isa, &arm_isa_template, sizeof(*isa));
arm_register_init();
isa->cg = NULL;
- be_emit_init_env(&isa->emit, file_handle);
+ be_emit_init(file_handle);
- arm_create_opcodes();
+ arm_create_opcodes(&arm_irn_ops);
arm_handle_intrinsics();
+ /* needed for the debug support */
+ be_gas_emit_switch_section(GAS_SECTION_TEXT);
+ be_emit_cstring(".Ltext0:\n");
+ be_emit_write_line();
+
/* we mark referenced global entities, so we can only emit those which
* are actually referenced. (Note: you mustn't use the type visited flag
* elsewhere in the backend)
inc_master_type_visited();
inited = 1;
- return isa;
+ return &isa->arch_env;
}
static void arm_done(void *self) {
arm_isa_t *isa = self;
- be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
+ be_gas_emit_decls(isa->arch_env.main_env, 1);
- be_emit_destroy_env(&isa->emit);
+ be_emit_exit();
free(self);
}
* here to speed up register allocation (and makes dumps
* smaller and more readable).
*/
-static int arm_get_n_reg_class(const void *self) {
- const arm_isa_t *isa = self;
-
- /* ARGH! is called BEFORE transform */
+static unsigned arm_get_n_reg_class(const void *self) {
+ (void) self;
return N_CLASSES;
- return isa->cg->have_fp_insn ? 2 : 1;
}
/**
* Return the register class with requested index.
*/
-static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
+static const arch_register_class_t *arm_get_reg_class(const void *self,
+ unsigned i) {
(void) self;
+ assert(i < N_CLASSES);
return &arm_reg_classes[i];
}
typedef struct {
be_abi_call_flags_bits_t flags;
const arch_env_t *arch_env;
- const arch_isa_t *isa;
ir_graph *irg;
} arm_abi_env_t;
static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
{
- arm_abi_env_t *env = xmalloc(sizeof(env[0]));
- be_abi_call_flags_t fl = be_abi_call_get_flags(call);
+ arm_abi_env_t *env = XMALLOC(arm_abi_env_t);
+ be_abi_call_flags_t fl = be_abi_call_get_flags(call);
env->flags = fl.bits;
env->irg = irg;
env->arch_env = arch_env;
- env->isa = arch_env->isa;
return env;
}
-static void arm_abi_dont_save_regs(void *self, pset *s)
-{
- arm_abi_env_t *env = self;
- if (env->flags.try_omit_fp)
- pset_insert_ptr(s, env->isa->bp);
-}
-
-
-
/**
- * Build the ARM prolog
+ * Generate the routine prologue.
+ *
+ * @param self The callback object.
+ * @param mem A pointer to the mem node. Update this if you define new memory.
+ * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param stack_bias Points to the current stack bias, can be modified if needed.
+ *
+ * @return The register which shall be used as a stack frame base.
+ *
+ * All nodes which define registers in @p reg_map must keep @p reg_map current.
*/
-static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
- ir_node *keep, *store;
- arm_abi_env_t *env = self;
- ir_graph *irg = env->irg;
- ir_node *block = get_irg_start_block(irg);
- arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
-
- ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
- ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
- ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
- ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
- ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
-
- if (env->flags.try_omit_fp)
- return env->isa->sp;
-
- ip = be_new_Copy(gp, irg, block, sp);
- arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
- be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
-
- store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
-
- sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
- arch_set_irn_register(env->arch_env, sp, env->isa->sp);
- *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
+static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias) {
+ arm_abi_env_t *env = self;
+ ir_node *store;
+ ir_graph *irg;
+ ir_node *block;
+ arch_register_class_t *gp;
- keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
- be_node_set_reg_class(keep, 1, gp);
- arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
- be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
+ ir_node *fp, *ip, *lr, *pc;
+ ir_node *sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
- fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
- new_tarval_from_long(4, get_irn_mode(fp)));
- arch_set_irn_register(env->arch_env, fp, env->isa->bp);
+ (void) stack_bias;
- be_abi_reg_map_set(reg_map, env->isa->bp, fp);
- be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
- be_abi_reg_map_set(reg_map, env->isa->sp, sp);
+ if (env->flags.try_omit_fp)
+ return env->arch_env->sp;
+
+ fp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
+ ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
+ lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
+ pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
+
+ gp = &arm_reg_classes[CLASS_arm_gp];
+ irg = env->irg;
+ block = get_irg_start_block(irg);
+
+ /* mark bp register as ignore */
+ be_set_constr_single_reg_out(get_Proj_pred(fp),
+ get_Proj_proj(fp), env->arch_env->bp,
+ arch_register_req_type_ignore);
+
+ /* copy SP to IP (so we can spill it */
+ ip = be_new_Copy(gp, block, sp);
+ be_set_constr_single_reg_out(ip, 0, &arm_gp_regs[REG_R12], 0);
+
+ /* spill stuff */
+ store = new_bd_arm_StoreStackM4Inc(NULL, block, sp, fp, ip, lr, pc, *mem);
+
+ sp = new_r_Proj(block, store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
+ arch_set_irn_register(sp, env->arch_env->sp);
+ *mem = new_r_Proj(block, store, mode_M, pn_arm_StoreStackM4Inc_M);
+
+ /* frame pointer is ip-4 (because ip is our old sp value) */
+ fp = new_bd_arm_Sub_i(NULL, block, ip, get_irn_mode(fp), 4);
+ arch_set_irn_register(fp, env->arch_env->bp);
+
+ /* beware: we change the fp but the StoreStackM4Inc above wants the old
+ * fp value. We are not allowed to spill or anything in the prolog, so we
+ * have to enforce some order here. (scheduler/regalloc are too stupid
+ * to extract this order from register requirements) */
+ add_irn_dep(fp, store);
+
+ fp = be_new_Copy(gp, block, fp); // XXX Gammelfix: only be_ have custom register requirements
+ be_set_constr_single_reg_out(fp, 0, env->arch_env->bp,
+ arch_register_req_type_ignore);
+ arch_set_irn_register(fp, env->arch_env->bp);
+
+ be_abi_reg_map_set(reg_map, env->arch_env->bp, fp);
+ be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], ip);
+ be_abi_reg_map_set(reg_map, env->arch_env->sp, sp);
be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
- return env->isa->bp;
+ return env->arch_env->bp;
}
/**
*/
static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
arm_abi_env_t *env = self;
- ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
- ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
+ ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
+ ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
// TODO: Activate Omit fp in epilogue
if (env->flags.try_omit_fp) {
- curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
- add_irn_dep(curr_sp, *mem);
-
- curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
- be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
- arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
- be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
-
- curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
- arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
- be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
- be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
+ curr_sp = be_new_IncSP(env->arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
+
+ curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
+ be_set_constr_single_reg_out(curr_lr, 0, &arm_gp_regs[REG_LR], 0);
+
+ curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], bl, curr_lr );
+ be_set_constr_single_reg_out(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC], 0);
} else {
- ir_node *sub12_node;
ir_node *load_node;
- tarval *tv = new_tarval_from_long(12,mode_Iu);
- sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
- // FIXME
- //set_arm_req_out_all(sub12_node, sub12_req);
- arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
- load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
- // FIXME
- //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
- //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
- //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
- curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
- curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
- curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
- *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
- arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
- arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
- arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
+
+ load_node = new_bd_arm_LoadStackM3Epilogue(NULL, bl, curr_bp, *mem);
+
+ curr_bp = new_r_Proj(bl, load_node, env->arch_env->bp->reg_class->mode, pn_arm_LoadStackM3Epilogue_res0);
+ curr_sp = new_r_Proj(bl, load_node, env->arch_env->sp->reg_class->mode, pn_arm_LoadStackM3Epilogue_res1);
+ curr_pc = new_r_Proj(bl, load_node, mode_Iu, pn_arm_LoadStackM3Epilogue_res2);
+ *mem = new_r_Proj(bl, load_node, mode_M, pn_arm_LoadStackM3Epilogue_M);
+ arch_set_irn_register(curr_bp, env->arch_env->bp);
+ arch_set_irn_register(curr_sp, env->arch_env->sp);
+ arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
}
- be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
- be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
+ be_abi_reg_map_set(reg_map, env->arch_env->sp, curr_sp);
+ be_abi_reg_map_set(reg_map, env->arch_env->bp, curr_bp);
be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
}
arm_abi_init,
free,
arm_get_between_type,
- arm_abi_dont_save_regs,
arm_abi_prologue,
arm_abi_epilogue,
};
ir_mode *mode;
int i;
int n = get_method_n_params(method_type);
- be_abi_call_flags_t flags = {
- {
- 0, /* store from left to right */
- 0, /* store arguments sequential */
- 1, /* try to omit the frame pointer */
- 1, /* the function can use any register as frame pointer */
- 1, /* a call can take the callee's address as an immediate */
- 0, /* IRG is a leaf function */
- 0 /* Set to one, if there is already enough room on the stack for call args. */
- }
- };
+ be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
(void) self;
+ /* set abi flags for calls */
+ call_flags.bits.left_to_right = 0;
+ call_flags.bits.store_args_sequential = 0;
+ /* call_flags.bits.try_omit_fp don't change this we can handle both */
+ call_flags.bits.fp_free = 0;
+ call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
+
/* set stack parameter passing style */
- be_abi_call_set_flags(abi, flags, &arm_abi_callbacks);
+ be_abi_call_set_flags(abi, call_flags, &arm_abi_callbacks);
for (i = 0; i < n; i++) {
/* reg = get reg for param i; */
/* be_abi_call_param_reg(abi, i, reg); */
- if (i < 4)
-
+ if (i < 4) {
be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i));
- else
- be_abi_call_param_stack(abi, i, 4, 0, 0);
+ } else {
+ tp = get_method_param_type(method_type, i);
+ mode = get_type_mode(tp);
+ be_abi_call_param_stack(abi, i, mode, 4, 0, 0);
+ }
}
/* set return registers */
}
}
-static const void *arm_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
- (void) self;
- (void) irn;
- return &arm_irn_ops;
-}
-
-const arch_irn_handler_t arm_irn_handler = {
- arm_get_irn_ops
-};
-
-const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
- (void) self;
- return &arm_irn_handler;
-}
-
int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
(void) block_env;
if(!is_arm_irn(irn))
*/
static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
(void) self;
- (void) selector;
- arm_sched_selector = reg_pressure_selector;
+ memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
+ /* arm_sched_selector.exectime = arm_sched_exectime; */
arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
return &arm_sched_selector;
+
}
static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
(void) self;
(void) irn;
/* TODO */
- assert(0);
- return NULL;
+ panic("Unimplemented arm_get_allowed_execution_units()");
}
static const be_machine_t *arm_get_machine(const void *self) {
(void) self;
/* TODO */
- assert(0);
- return NULL;
+ panic("Unimplemented arm_get_machine()");
}
/**
return 1;
}
+static asm_constraint_flags_t arm_parse_asm_constraint(const void *self, const char **c)
+{
+ /* asm not supported */
+ (void) self;
+ (void) c;
+ return ASM_CONSTRAINT_FLAG_INVALID;
+}
+
+static int arm_is_valid_clobber(const void *self, const char *clobber)
+{
+ (void) self;
+ (void) clobber;
+ return 0;
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
arm_is_psi_allowed /* allows or disallows Psi creation for given selector */
};
static ir_settings_arch_dep_t ad = {
- 1, /* allow subs */
- 1, /* Muls are fast enough on ARM but ... */
- 31, /* ... one shift would be possible better */
- 0, /* SMUL is needed, only in Arch M */
- 0, /* UMUL is needed, only in Arch M */
- 32, /* SMUL & UMUL available for 32 bit */
+ 1, /* allow subs */
+ 1, /* Muls are fast enough on ARM but ... */
+ 31, /* ... one shift would be possible better */
+ NULL, /* no evaluator function */
+ 0, /* SMUL is needed, only in Arch M */
+ 0, /* UMUL is needed, only in Arch M */
+ 32, /* SMUL & UMUL available for 32 bit */
};
static backend_params p = {
1, /* need dword lowering */
0, /* don't support inline assembler yet */
- NULL, /* no additional opcodes */
NULL, /* will be set later */
NULL, /* but yet no creator function */
NULL, /* context for create_intrinsic_fkt */
- NULL, /* will be set below */
+ NULL, /* ifconv_info will be set below */
+ NULL, /* float arithmetic mode (TODO) */
+ 0, /* no trampoline support: size 0 */
+ 0, /* no trampoline support: align 0 */
+ NULL, /* no trampoline support: no trampoline builder */
+ 4 /* alignment of stack parameter */
};
p.dep_param = &ad;
const arch_isa_if_t arm_isa_if = {
arm_init,
arm_done,
+ NULL, /* handle_intrinsics */
arm_get_n_reg_class,
arm_get_reg_class,
arm_get_reg_class_for_mode,
arm_get_call_abi,
- arm_get_irn_handler,
arm_get_code_generator_if,
arm_get_list_sched_selector,
arm_get_ilp_sched_selector,
arm_get_allowed_execution_units,
arm_get_machine,
arm_get_irg_list,
+ NULL, /* mark remat */
+ arm_parse_asm_constraint,
+ arm_is_valid_clobber
};
void be_init_arch_arm(void)
be_register_isa_if("arm", &arm_isa_if);
arm_init_transform();
+ arm_init_emitter();
}
BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);