#include "../besched.h"
#include "be.h"
#include "../bemachine.h"
-#include "../beilpsched.h"
#include "../bemodule.h"
#include "../beirg.h"
#include "../bespillslots.h"
{
(void) irn;
/* TODO: we should mark reload/spill instructions and classify them here */
- return 0;
+ return arch_irn_class_none;
}
static ir_entity *arm_get_frame_entity(const ir_node *irn)
const arm_attr_t *attr = get_arm_attr_const(irn);
if (is_arm_FrameAddr(irn)) {
- const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
+ const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(irn);
return attr->entity;
}
if (attr->is_load_store) {
static void arm_set_stack_bias(ir_node *irn, int bias)
{
if (is_arm_FrameAddr(irn)) {
- arm_SymConst_attr_t *attr = get_irn_generic_attr(irn);
+ arm_SymConst_attr_t *attr = get_arm_SymConst_attr(irn);
attr->fp_offset += bias;
} else {
arm_load_store_attr_t *attr = get_arm_load_store_attr(irn);
* Transforms the standard Firm graph into
* a ARM firm graph.
*/
-static void arm_prepare_graph(void *self)
+static void arm_prepare_graph(ir_graph *irg)
{
- arm_code_gen_t *cg = self;
-
/* transform nodes into assembler instructions */
- arm_transform_graph(cg);
+ arm_transform_graph(irg);
/* do local optimizations (mainly CSE) */
- local_optimize_graph(cg->irg);
-
- if (cg->dump)
- dump_ir_graph(cg->irg, "transformed");
+ local_optimize_graph(irg);
/* do code placement, to optimize the position of constants */
- place_code(cg->irg);
-
- if (cg->dump)
- dump_ir_graph(cg->irg, "place");
+ place_code(irg);
}
/**
* Called immediately before emit phase.
*/
-static void arm_finish_irg(void *self)
+static void arm_finish_irg(ir_graph *irg)
{
- arm_code_gen_t *cg = self;
-
/* do peephole optimizations and fix stack offsets */
- arm_peephole_optimization(cg);
+ arm_peephole_optimization(irg);
}
-static void arm_before_ra(void *self)
+static void arm_before_ra(ir_graph *irg)
{
- arm_code_gen_t *cg = self;
-
- be_sched_fix_flags(cg->irg, &arm_reg_classes[CLASS_arm_flags],
- NULL, NULL);
+ be_sched_fix_flags(irg, &arm_reg_classes[CLASS_arm_flags], NULL, NULL);
}
static void transform_Reload(ir_node *node)
{
ir_node *block = get_nodes_block(node);
dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *ptr = get_irn_n(node, be_pos_Reload_frame);
- ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
+ ir_node *ptr = get_irn_n(node, n_be_Reload_frame);
+ ir_node *mem = get_irn_n(node, n_be_Reload_mem);
ir_mode *mode = get_irn_mode(node);
ir_entity *entity = be_get_frame_entity(node);
const arch_register_t *reg;
{
ir_node *block = get_nodes_block(node);
dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *ptr = get_irn_n(node, be_pos_Spill_frame);
- ir_node *mem = new_NoMem();
- ir_node *val = get_irn_n(node, be_pos_Spill_val);
+ ir_node *ptr = get_irn_n(node, n_be_Spill_frame);
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *mem = get_irg_no_mem(irg);
+ ir_node *val = get_irn_n(node, n_be_Spill_val);
ir_mode *mode = get_irn_mode(val);
ir_entity *entity = be_get_frame_entity(node);
ir_node *sched_point;
static void arm_collect_frame_entity_nodes(ir_node *node, void *data)
{
- be_fec_env_t *env = data;
+ be_fec_env_t *env = (be_fec_env_t*)data;
const ir_mode *mode;
int align;
ir_entity *entity;
}
}
-static void arm_after_ra(void *self)
+static void arm_after_ra(ir_graph *irg)
{
- arm_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
-
- be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
+ be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
+ bool at_begin = stack_layout->sp_relative ? true : false;
+ be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env);
- be_assign_entities(fec_env, arm_set_frame_entity);
+ be_assign_entities(fec_env, arm_set_frame_entity, at_begin);
be_free_frame_entity_coalescer(fec_env);
- irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL);
+ irg_block_walk_graph(irg, NULL, arm_after_ra_walker, NULL);
}
-/**
- * Emits the code, closes the output file and frees
- * the code generator interface.
- */
-static void arm_emit_and_done(void *self)
-{
- arm_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
-
- arm_gen_routine(cg, irg);
-
- /* de-allocate code generator */
- free(self);
-}
-
-/* forward */
-static void *arm_cg_init(ir_graph *irg);
-
-static const arch_code_generator_if_t arm_code_gen_if = {
- arm_cg_init,
- NULL, /* get_pic_base */
- NULL, /* before abi introduce */
- arm_prepare_graph,
- NULL, /* spill */
- arm_before_ra, /* before register allocation hook */
- arm_after_ra,
- arm_finish_irg,
- arm_emit_and_done,
-};
-
/**
* Initializes the code generator.
*/
-static void *arm_cg_init(ir_graph *irg)
+static void arm_init_graph(ir_graph *irg)
{
- arm_isa_t *isa = (arm_isa_t*) be_get_irg_arch_env(irg);
- arm_code_gen_t *cg;
-
- cg = XMALLOCZ(arm_code_gen_t);
- cg->impl = &arm_code_gen_if;
- cg->irg = irg;
- cg->isa = isa;
- cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
-
- /* enter the current code generator */
- isa->cg = cg;
-
- return (arch_code_generator_t *)cg;
+ (void) irg;
}
lower_intrinsics(records, n_records, /*part_block_used=*/0);
}
-const arch_isa_if_t arm_isa_if;
+extern const arch_isa_if_t arm_isa_if;
static arm_isa_t arm_isa_template = {
{
&arm_isa_if, /* isa interface */
- &arm_gp_regs[REG_SP], /* stack pointer */
- &arm_gp_regs[REG_R11], /* base pointer */
+ N_ARM_REGISTERS,
+ arm_registers,
+ N_ARM_CLASSES,
+ arm_reg_classes,
+ &arm_registers[REG_SP], /* stack pointer */
+ &arm_registers[REG_R11], /* base pointer */
&arm_reg_classes[CLASS_arm_gp], /* static link pointer class */
- -1, /* stack direction */
2, /* power of two stack alignment for calls, 2^2 == 4 */
NULL, /* main environment */
7, /* spill costs */
true, /* we do have custom abi handling */
},
ARM_FPU_ARCH_FPE, /* FPU architecture */
- NULL, /* current code generator */
};
/**
*/
static arch_env_t *arm_init(FILE *file_handle)
{
- static int inited = 0;
- arm_isa_t *isa;
-
- if (inited)
- return NULL;
-
- isa = XMALLOC(arm_isa_t);
+ arm_isa_t *isa = XMALLOC(arm_isa_t);
memcpy(isa, &arm_isa_template, sizeof(*isa));
arm_register_init();
- isa->cg = NULL;
be_emit_init(file_handle);
arm_create_opcodes(&arm_irn_ops);
be_gas_emit_types = false;
- /* needed for the debug support */
- be_gas_emit_switch_section(GAS_SECTION_TEXT);
- be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
- be_emit_write_line();
-
- inited = 1;
return &isa->base;
}
*/
static void arm_done(void *self)
{
- arm_isa_t *isa = self;
+ arm_isa_t *isa = (arm_isa_t*)self;
be_gas_emit_decls(isa->base.main_env);
free(self);
}
-
-/**
- * Report the number of register classes.
- * If we don't have fp instructions, report only GP
- * here to speed up register allocation (and makes dumps
- * smaller and more readable).
- */
-static unsigned arm_get_n_reg_class(void)
-{
- return N_CLASSES;
-}
-
-/**
- * Return the register class with requested index.
- */
-static const arch_register_class_t *arm_get_reg_class(unsigned i)
-{
- assert(i < N_CLASSES);
- return &arm_reg_classes[i];
-}
-
/**
* Get the register class which shall be used to store a value of a given mode.
* @param self The this pointer.
return &arm_reg_classes[CLASS_arm_gp];
}
-static int arm_to_appear_in_schedule(void *block_env, const ir_node *irn)
-{
- (void) block_env;
- if (!is_arm_irn(irn))
- return -1;
-
- return 1;
-}
-
-/**
- * Initializes the code generator interface.
- */
-static const arch_code_generator_if_t *arm_get_code_generator_if(void *self)
-{
- (void) self;
- return &arm_code_gen_if;
-}
-
-list_sched_selector_t arm_sched_selector;
-
-/**
- * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
- */
-static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector)
-{
- (void) self;
- memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector));
- /* arm_sched_selector.exectime = arm_sched_exectime; */
- arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
- return &arm_sched_selector;
-
-}
-
-static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self)
-{
- (void) self;
- return NULL;
-}
-
/**
* Returns the necessary byte alignment for storing a register of given class.
*/
return 4;
}
-static const be_execution_unit_t ***arm_get_allowed_execution_units(const ir_node *irn)
-{
- (void) irn;
- /* TODO */
- panic("Unimplemented arm_get_allowed_execution_units()");
-}
-
-static const be_machine_t *arm_get_machine(const void *self)
-{
- (void) self;
- /* TODO */
- panic("Unimplemented arm_get_machine()");
-}
-
/**
* Return irp irgs in the desired order.
*/
(void) sel;
(void) mux_false;
(void) mux_true;
-
- return 0;
+ return false;
}
static asm_constraint_flags_t arm_parse_asm_constraint(const char **c)
return 0;
}
+static void arm_lower_for_target(void)
+{
+ size_t i, n_irgs = get_irp_n_irgs();
+
+ lower_params_t params = {
+ 4, /* def_ptr_alignment */
+ LF_COMPOUND_RETURN | LF_RETURN_HIDDEN, /* flags */
+ ADD_HIDDEN_ALWAYS_IN_FRONT, /* hidden_params */
+ NULL, /* find pointer type */
+ NULL, /* ret_compound_in_regs */
+ };
+
+ /* lower compound param handling */
+ lower_calls_with_compounds(¶ms);
+
+ for (i = 0; i < n_irgs; ++i) {
+ ir_graph *irg = get_irp_irg(i);
+ lower_switch(irg, 256, true);
+ }
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
{
static ir_settings_arch_dep_t ad = {
1, /* allow subs */
- 1, /* Muls are fast enough on ARM but ... */
+ 1, /* Muls are fast enough on ARM but ... */
31, /* ... one shift would be possible better */
NULL, /* no evaluator function */
0, /* SMUL is needed, only in Arch M */
0, /* don't support inline assembler yet */
1, /* support Rotl nodes */
1, /* big endian */
- NULL, /* lowering function */
&ad, /* will be set later */
arm_is_mux_allowed, /* allow_ifconv function */
NULL, /* float arithmetic mode (TODO) */
const arch_isa_if_t arm_isa_if = {
arm_init,
+ arm_lower_for_target,
arm_done,
NULL, /* handle_intrinsics */
- arm_get_n_reg_class,
- arm_get_reg_class,
arm_get_reg_class_for_mode,
NULL,
- arm_get_code_generator_if,
- arm_get_list_sched_selector,
- arm_get_ilp_sched_selector,
arm_get_reg_class_alignment,
arm_get_libfirm_params,
- arm_get_allowed_execution_units,
- arm_get_machine,
arm_get_irg_list,
NULL, /* mark remat */
arm_parse_asm_constraint,
- arm_is_valid_clobber
+ arm_is_valid_clobber,
+
+ arm_init_graph,
+ NULL, /* get_pic_base */
+ NULL, /* before_abi */
+ arm_prepare_graph,
+ arm_before_ra,
+ arm_after_ra,
+ arm_finish_irg,
+ arm_gen_routine,
};
-BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
+BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm)
void be_init_arch_arm(void)
{
lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
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