adapted to new code generator callback (spill)

[libfirm] / ir / be / arm / bearch_arm.c

diff --git a/ir/be/arm/bearch_arm.c b/ir/be/arm/bearch_arm.c
index c825bbf..48334f4 100644 (file)
--- a/ir/be/arm/bearch_arm.c
+++ b/ir/be/arm/bearch_arm.c
@@ -27,6 +27,8 @@
 #include "../besched_t.h"
 #include "../be.h"
 #include "../beabi.h"
+#include "../bemachine.h"
+#include "../beilpsched.h"
 
 #include "bearch_arm_t.h"
 
@@ -231,6 +233,10 @@ static entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
        return NULL;
 }
 
+static void arm_set_frame_entity(const void *self, ir_node *irn, entity *ent) {
+       /* TODO: set the entity assigned to the frame */
+}
+
 /**
  * This function is called by the generic backend to correct offsets for
  * nodes accessing the stack.
@@ -239,6 +245,10 @@ static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
        /* TODO: correct offset if irn accesses the stack */
 }
 
+static int arm_get_sp_bias(const void *self, const ir_node *irn) {
+       return 0;
+}
+
 /* fill register allocator interface */
 
 static const arch_irn_ops_if_t arm_irn_ops_if = {
@@ -248,8 +258,13 @@ static const arch_irn_ops_if_t arm_irn_ops_if = {
        arm_classify,
        arm_get_flags,
        arm_get_frame_entity,
+       arm_set_frame_entity,
        arm_set_stack_bias,
-       NULL
+       arm_get_sp_bias,
+       NULL,    /* get_inverse             */
+       NULL,    /* get_op_estimated_cost   */
+       NULL,    /* possible_memory_operand */
+       NULL,    /* perform_memory_operand  */
 };
 
 arm_irn_ops_t arm_irn_ops = {
@@ -286,7 +301,7 @@ static void arm_prepare_graph(void *self) {
 /**
  * Called immediately before emit phase.
  */
-static void arm_finish_irg(ir_graph *irg, arm_code_gen_t *cg) {
+static void arm_finish_irg(void *self) {
        /* TODO: - fix offsets for nodes accessing stack
                         - ...
        */
@@ -319,7 +334,6 @@ static void arm_emit_and_done(void *self) {
                cg->emit_decls = 0;
        }
 
-       arm_finish_irg(irg, cg);
        dump_ir_block_graph_sched(irg, "-arm-finished");
        arm_gen_routine(out, irg, cg);
 
@@ -529,9 +543,11 @@ static const arch_code_generator_if_t arm_code_gen_if = {
        arm_cg_init,
        arm_before_abi,     /* before abi introduce */
        arm_prepare_graph,
+       NULL,               /* spill */
        arm_before_sched,   /* before scheduling hook */
        arm_before_ra,      /* before register allocation hook */
        NULL,               /* after register allocation */
+       arm_finish_irg,
        arm_emit_and_done,
 };
 
@@ -928,7 +944,8 @@ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_m
 
 //     TODO: Activate Omit fp in epilogue
        if(env->flags.try_omit_fp) {
-               curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
+               curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
+               add_irn_dep(curr_sp, *mem);
 
                curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
                be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
@@ -1046,12 +1063,16 @@ list_sched_selector_t arm_sched_selector;
 /**
  * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded
  */
-static const list_sched_selector_t *arm_get_list_sched_selector(const void *self) {
+static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
        memcpy(&arm_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
        arm_sched_selector.to_appear_in_schedule = arm_to_appear_in_schedule;
        return &arm_sched_selector;
 }
 
+static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) {
+       return NULL;
+}
+
 /**
  * Returns the necessary byte alignment for storing a register of given class.
  */
@@ -1060,6 +1081,18 @@ static int arm_get_reg_class_alignment(const void *self, const arch_register_cla
        return get_mode_size_bytes(mode);
 }
 
+static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
+       /* TODO */
+       assert(0);
+       return NULL;
+}
+
+static const be_machine_t *arm_get_machine(const void *self) {
+       /* TODO */
+       assert(0);
+       return NULL;
+}
+
 /**
  * Returns the libFirm configuration parameter for this backend.
  */
@@ -1077,6 +1110,7 @@ static const backend_params *arm_get_libfirm_params(void) {
                NULL,  /* will be set later */
                1,     /* need dword lowering */
                NULL,  /* but yet no creator function */
+               NULL,  /* context for create_intrinsic_fkt */
        };
 
        p.dep_param = &ad;
@@ -1131,8 +1165,11 @@ const arch_isa_if_t arm_isa_if = {
        arm_get_irn_handler,
        arm_get_code_generator_if,
        arm_get_list_sched_selector,
+       arm_get_ilp_sched_selector,
        arm_get_reg_class_alignment,
        arm_get_libfirm_params,
+       arm_get_allowed_execution_units,
+       arm_get_machine,
 #ifdef WITH_LIBCORE
        arm_register_options
 #endif