-/* The main arm backend driver file. */
-/* $Id$ */
+/*
+ * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
+/**
+ * @file
+ * @brief The main arm backend driver file.
+ * @author Oliver Richter, Tobias Gneist
+ * @version $Id$
+ */
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
-#ifdef WITH_LIBCORE
#include <libcore/lc_opts.h>
#include <libcore/lc_opts_enum.h>
-#endif /* WITH_LIBCORE */
#include "pseudo_irg.h"
#include "irgwalk.h"
#include "bitset.h"
#include "debug.h"
-#include "../bearch.h" /* the general register allocator interface */
+#include "../bearch_t.h" /* the general register allocator interface */
#include "../benode_t.h"
#include "../belower.h"
#include "../besched_t.h"
#include "../beabi.h"
#include "../bemachine.h"
#include "../beilpsched.h"
+#include "../bemodule.h"
+#include "../beirg_t.h"
+#include "../bespillslots.h"
+#include "../begnuas.h"
#include "bearch_arm_t.h"
#include "arm_new_nodes.h" /* arm nodes interface */
#include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
-#include "arm_gen_decls.h" /* interface declaration emitter */
#include "arm_transform.h"
#include "arm_emitter.h"
#include "arm_map_regs.h"
* |___/
**************************************************/
-static ir_node *my_skip_proj(const ir_node *n) {
- while (is_Proj(n))
- n = get_Proj_pred(n);
- return (ir_node *)n;
-}
-
/**
* Return register requirements for a arm node.
* If the node returns a tuple (mode_T) then the proj's
* will be asked for this information.
*/
-static const arch_register_req_t *arm_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
- const arm_register_req_t *irn_req;
+static const
+arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
+ int pos) {
long node_pos = pos == -1 ? 0 : pos;
- ir_mode *mode = get_irn_mode(irn);
+ ir_mode *mode = get_irn_mode(node);
FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
- if (is_Block(irn) || mode == mode_X || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
- return NULL;
+ if (is_Block(node) || mode == mode_X || mode == mode_M) {
+ DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", node));
+ return arch_no_register_req;
}
if (mode == mode_T && pos < 0) {
- DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
- return NULL;
+ DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", node));
+ return arch_no_register_req;
}
- DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
+ DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, node));
- if (is_Proj(irn)) {
+ if (is_Proj(node)) {
/* in case of a proj, we need to get the correct OUT slot */
/* of the node corresponding to the proj number */
if (pos == -1) {
- node_pos = arm_translate_proj_pos(irn);
+ node_pos = arm_translate_proj_pos(node);
}
else {
node_pos = pos;
}
- irn = my_skip_proj(irn);
+ node = skip_Proj_const(node);
- DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
+ DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", node, node_pos));
}
/* get requirements for our own nodes */
- if (is_arm_irn(irn)) {
+ if (is_arm_irn(node)) {
+ const arch_register_req_t *req;
if (pos >= 0) {
- irn_req = get_arm_in_req(irn, pos);
- }
- else {
- irn_req = get_arm_out_req(irn, node_pos);
- }
-
- DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
-
- memcpy(req, &(irn_req->req), sizeof(*req));
-
- if (arch_register_req_is(&(irn_req->req), should_be_same)) {
- assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
- req->other_same = get_irn_n(irn, irn_req->same_pos);
+ req = get_arm_in_req(node, pos);
+ } else {
+ req = get_arm_out_req(node, node_pos);
}
- if (arch_register_req_is(&(irn_req->req), should_be_different)) {
- assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
- req->other_different = get_irn_n(irn, irn_req->different_pos);
- }
+ DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", node, pos));
+ return req;
}
- /* get requirements for FIRM nodes */
- else {
- /* treat Phi like Const with default requirements */
- if (is_Phi(irn)) {
- DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
- if (mode_is_float(mode)) {
- memcpy(req, &(arm_default_req_arm_fpa.req), sizeof(*req));
- }
- else if (mode_is_int(mode) || mode_is_reference(mode)) {
- memcpy(req, &(arm_default_req_arm_gp.req), sizeof(*req));
- }
- else if (mode == mode_T || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
- return NULL;
- }
- else {
- assert(0 && "unsupported Phi-Mode");
- }
- }
- else {
- DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
- req = NULL;
- }
- }
+ /* unknown should be tranformed by now */
+ assert(!is_Unknown(node));
+ DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", node));
- return req;
+ return arch_no_register_req;
}
static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
}
pos = arm_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
+ irn = skip_Proj(irn);
}
if (is_arm_irn(irn)) {
}
pos = arm_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
+ irn = skip_Proj_const(irn);
}
if (is_arm_irn(irn)) {
}
static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
- irn = my_skip_proj(irn);
+ irn = skip_Proj_const(irn);
if (is_cfop(irn)) {
return arch_irn_class_branch;
}
static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
- irn = my_skip_proj(irn);
+ irn = skip_Proj_const(irn);
if (is_arm_irn(irn)) {
return get_arm_flags(irn);
return 0;
}
-static entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
+static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
/* TODO: return the entity assigned to the frame */
return NULL;
}
-static void arm_set_frame_entity(const void *self, ir_node *irn, entity *ent) {
+static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
/* TODO: set the entity assigned to the frame */
}
/* Some stuff you need to do immediately after register allocation */
}
+/**
+ * We transform Spill and Reload here. This needs to be done before
+ * stack biasing otherwise we would miss the corrected offset for these nodes.
+ */
+static void arm_after_ra(void *self) {
+ arm_code_gen_t *cg = self;
+ be_coalesce_spillslots(cg->birg);
+}
/**
* Emits the code, closes the output file and frees
*/
static void arm_emit_and_done(void *self) {
arm_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
- FILE *out = cg->isa->out;
-
- if (cg->emit_decls) {
- arm_gen_decls(out);
- cg->emit_decls = 0;
- }
+ ir_graph *irg = cg->irg;
dump_ir_block_graph_sched(irg, "-arm-finished");
- arm_gen_routine(out, irg, cg);
+ arm_gen_routine(cg, irg);
cur_reg_set = NULL;
*
* Handle some special cases here:
* 1.) A constant: simply split into two
- * 2.) A load: siply split into two
+ * 2.) A load: simply split into two
*/
static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
ir_node **resH, ir_node **resL) {
*
* Handle some special cases here:
* 1.) A constant: simply move
- * 2.) A load: siply load
+ * 2.) A load: simply load
*/
static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
if (is_Const(arg)) {
irg_walk_graph(cg->irg, NULL, handle_calls, cg);
}
-static void *arm_cg_init(const be_irg_t *birg);
+static void *arm_cg_init(be_irg_t *birg);
static const arch_code_generator_if_t arm_code_gen_if = {
arm_cg_init,
arm_before_abi, /* before abi introduce */
arm_prepare_graph,
+ NULL, /* spill */
arm_before_sched, /* before scheduling hook */
arm_before_ra, /* before register allocation hook */
- NULL, /* after register allocation */
+ arm_after_ra,
arm_finish_irg,
arm_emit_and_done,
};
/**
* Initializes the code generator.
*/
-static void *arm_cg_init(const be_irg_t *birg) {
+static void *arm_cg_init(be_irg_t *birg) {
static ir_type *int_tp = NULL;
arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env->isa;
arm_code_gen_t *cg;
FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
- isa->num_codegens++;
-
- if (isa->num_codegens > 1)
- cg->emit_decls = 0;
- else
- cg->emit_decls = 1;
-
cur_reg_set = cg->reg_set;
arm_irn_ops.cg = cg;
* to runtime calls.
*/
static void arm_handle_intrinsics(void) {
- ir_type *tp, *int_tp, *uint_tp;
- i_record records[8];
- int n_records = 0;
+ ir_type *tp, *int_tp, *uint_tp;
+ i_record records[8];
+ int n_records = 0;
#define ID(x) new_id_from_chars(x, sizeof(x)-1)
- int_tp = new_type_primitive(ID("int"), mode_Is);
- uint_tp = new_type_primitive(ID("uint"), mode_Iu);
+ int_tp = new_type_primitive(ID("int"), mode_Is);
+ uint_tp = new_type_primitive(ID("uint"), mode_Iu);
/* ARM has neither a signed div instruction ... */
- {
- runtime_rt rt_Div;
- i_instr_record *map_Div = &records[n_records++].i_instr;
-
- tp = new_type_method(ID("rt_iDiv"), 2, 1);
- set_method_param_type(tp, 0, int_tp);
- set_method_param_type(tp, 1, int_tp);
- set_method_res_type(tp, 0, int_tp);
-
- rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
- rt_Div.mode = mode_T;
- rt_Div.mem_proj_nr = pn_Div_M;
- rt_Div.exc_proj_nr = pn_Div_X_except;
- rt_Div.exc_mem_proj_nr = pn_Div_M;
- rt_Div.res_proj_nr = pn_Div_res;
-
- set_entity_visibility(rt_Div.ent, visibility_external_allocated);
-
- map_Div->kind = INTRINSIC_INSTR;
- map_Div->op = op_Div;
- map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Div->ctx = &rt_Div;
- }
- /* ... nor a signed div instruction ... */
- {
- runtime_rt rt_Div;
- i_instr_record *map_Div = &records[n_records++].i_instr;
-
- tp = new_type_method(ID("rt_uDiv"), 2, 1);
- set_method_param_type(tp, 0, uint_tp);
- set_method_param_type(tp, 1, uint_tp);
- set_method_res_type(tp, 0, uint_tp);
-
- rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
- rt_Div.mode = mode_T;
- rt_Div.mem_proj_nr = pn_Div_M;
- rt_Div.exc_proj_nr = pn_Div_X_except;
- rt_Div.exc_mem_proj_nr = pn_Div_M;
- rt_Div.res_proj_nr = pn_Div_res;
-
- set_entity_visibility(rt_Div.ent, visibility_external_allocated);
-
- map_Div->kind = INTRINSIC_INSTR;
- map_Div->op = op_Div;
- map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Div->ctx = &rt_Div;
- }
+ {
+ runtime_rt rt_Div;
+ i_instr_record *map_Div = &records[n_records++].i_instr;
+
+ tp = new_type_method(ID("rt_iDiv"), 2, 1);
+ set_method_param_type(tp, 0, int_tp);
+ set_method_param_type(tp, 1, int_tp);
+ set_method_res_type(tp, 0, int_tp);
+
+ rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
+ rt_Div.mode = mode_T;
+ rt_Div.res_mode = mode_Is;
+ rt_Div.mem_proj_nr = pn_Div_M;
+ rt_Div.regular_proj_nr = pn_Div_X_regular;
+ rt_Div.exc_proj_nr = pn_Div_X_except;
+ rt_Div.exc_mem_proj_nr = pn_Div_M;
+ rt_Div.res_proj_nr = pn_Div_res;
+
+ set_entity_visibility(rt_Div.ent, visibility_external_allocated);
+
+ map_Div->kind = INTRINSIC_INSTR;
+ map_Div->op = op_Div;
+ map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+ map_Div->ctx = &rt_Div;
+ }
+ /* ... nor an unsigned div instruction ... */
+ {
+ runtime_rt rt_Div;
+ i_instr_record *map_Div = &records[n_records++].i_instr;
+
+ tp = new_type_method(ID("rt_uDiv"), 2, 1);
+ set_method_param_type(tp, 0, uint_tp);
+ set_method_param_type(tp, 1, uint_tp);
+ set_method_res_type(tp, 0, uint_tp);
+
+ rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
+ rt_Div.mode = mode_T;
+ rt_Div.res_mode = mode_Iu;
+ rt_Div.mem_proj_nr = pn_Div_M;
+ rt_Div.regular_proj_nr = pn_Div_X_regular;
+ rt_Div.exc_proj_nr = pn_Div_X_except;
+ rt_Div.exc_mem_proj_nr = pn_Div_M;
+ rt_Div.res_proj_nr = pn_Div_res;
+
+ set_entity_visibility(rt_Div.ent, visibility_external_allocated);
+
+ map_Div->kind = INTRINSIC_INSTR;
+ map_Div->op = op_Div;
+ map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+ map_Div->ctx = &rt_Div;
+ }
/* ... nor a signed mod instruction ... */
- {
- runtime_rt rt_Mod;
- i_instr_record *map_Mod = &records[n_records++].i_instr;
-
- tp = new_type_method(ID("rt_iMod"), 2, 1);
- set_method_param_type(tp, 0, int_tp);
- set_method_param_type(tp, 1, int_tp);
- set_method_res_type(tp, 0, int_tp);
-
- rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
- rt_Mod.mode = mode_T;
- rt_Mod.mem_proj_nr = pn_Mod_M;
- rt_Mod.exc_proj_nr = pn_Mod_X_except;
- rt_Mod.exc_mem_proj_nr = pn_Mod_M;
- rt_Mod.res_proj_nr = pn_Mod_res;
-
- set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
-
- map_Mod->kind = INTRINSIC_INSTR;
- map_Mod->op = op_Mod;
- map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Mod->ctx = &rt_Mod;
- }
- /* ... nor a unsigned mod. */
- {
- runtime_rt rt_Mod;
- i_instr_record *map_Mod = &records[n_records++].i_instr;
-
- tp = new_type_method(ID("rt_uMod"), 2, 1);
- set_method_param_type(tp, 0, uint_tp);
- set_method_param_type(tp, 1, uint_tp);
- set_method_res_type(tp, 0, uint_tp);
-
- rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
- rt_Mod.mode = mode_T;
- rt_Mod.mem_proj_nr = pn_Mod_M;
- rt_Mod.exc_proj_nr = pn_Mod_X_except;
- rt_Mod.exc_mem_proj_nr = pn_Mod_M;
- rt_Mod.res_proj_nr = pn_Mod_res;
-
- set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
-
- map_Mod->kind = INTRINSIC_INSTR;
- map_Mod->op = op_Mod;
- map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Mod->ctx = &rt_Mod;
- }
-
- if (n_records > 0)
- lower_intrinsics(records, n_records);
+ {
+ runtime_rt rt_Mod;
+ i_instr_record *map_Mod = &records[n_records++].i_instr;
+
+ tp = new_type_method(ID("rt_iMod"), 2, 1);
+ set_method_param_type(tp, 0, int_tp);
+ set_method_param_type(tp, 1, int_tp);
+ set_method_res_type(tp, 0, int_tp);
+
+ rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
+ rt_Mod.mode = mode_T;
+ rt_Mod.res_mode = mode_Is;
+ rt_Mod.mem_proj_nr = pn_Mod_M;
+ rt_Mod.regular_proj_nr = pn_Mod_X_regular;
+ rt_Mod.exc_proj_nr = pn_Mod_X_except;
+ rt_Mod.exc_mem_proj_nr = pn_Mod_M;
+ rt_Mod.res_proj_nr = pn_Mod_res;
+
+ set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
+
+ map_Mod->kind = INTRINSIC_INSTR;
+ map_Mod->op = op_Mod;
+ map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+ map_Mod->ctx = &rt_Mod;
+ }
+ /* ... nor an unsigned mod. */
+ {
+ runtime_rt rt_Mod;
+ i_instr_record *map_Mod = &records[n_records++].i_instr;
+
+ tp = new_type_method(ID("rt_uMod"), 2, 1);
+ set_method_param_type(tp, 0, uint_tp);
+ set_method_param_type(tp, 1, uint_tp);
+ set_method_res_type(tp, 0, uint_tp);
+
+ rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
+ rt_Mod.mode = mode_T;
+ rt_Mod.res_mode = mode_Iu;
+ rt_Mod.mem_proj_nr = pn_Mod_M;
+ rt_Mod.regular_proj_nr = pn_Mod_X_regular;
+ rt_Mod.exc_proj_nr = pn_Mod_X_except;
+ rt_Mod.exc_mem_proj_nr = pn_Mod_M;
+ rt_Mod.res_proj_nr = pn_Mod_res;
+
+ set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
+
+ map_Mod->kind = INTRINSIC_INSTR;
+ map_Mod->op = op_Mod;
+ map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+ map_Mod->ctx = &rt_Mod;
+ }
+
+ if (n_records > 0)
+ lower_intrinsics(records, n_records);
}
/*****************************************************************
*****************************************************************/
static arm_isa_t arm_isa_template = {
- &arm_isa_if, /* isa interface */
- &arm_gp_regs[REG_SP], /* stack pointer */
- &arm_gp_regs[REG_R11], /* base pointer */
- -1, /* stack direction */
- 0, /* number of codegenerator objects */
+ {
+ &arm_isa_if, /* isa interface */
+ &arm_gp_regs[REG_SP], /* stack pointer */
+ &arm_gp_regs[REG_R11], /* base pointer */
+ -1, /* stack direction */
+ NULL, /* main environment */
+ 7, /* spill costs */
+ 5, /* reload costs */
+ },
0, /* use generic register names instead of SP, LR, PC */
- NULL, /* current code generator */
- NULL, /* output file */
ARM_FPU_ARCH_FPE, /* FPU architecture */
+ NULL, /* current code generator */
+ { NULL, }, /* emitter environment */
};
/**
memcpy(isa, &arm_isa_template, sizeof(*isa));
arm_register_init(isa);
- if (isa->gen_reg_names) {
- /* patch register names */
- arm_gp_regs[REG_R11].name = "r11";
- arm_gp_regs[REG_SP].name = "r13";
- arm_gp_regs[REG_LR].name = "r14";
- arm_gp_regs[REG_PC].name = "r15";
- }
isa->cg = NULL;
- isa->out = file_handle;
+ be_emit_init_env(&isa->emit, file_handle);
arm_create_opcodes();
arm_handle_intrinsics();
- arm_switch_section(NULL, NO_SECTION);
+
+ /* we mark referenced global entities, so we can only emit those which
+ * are actually referenced. (Note: you mustn't use the type visited flag
+ * elsewhere in the backend)
+ */
+ inc_master_type_visited();
inited = 1;
return isa;
/**
- * frees the ISA structure.
+ * Closes the output file and frees the ISA structure.
*/
static void arm_done(void *self) {
+ arm_isa_t *isa = self;
+
+ be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
+
+ be_emit_destroy_env(&isa->emit);
free(self);
}
*/
static ir_type *arm_get_between_type(void *self) {
static ir_type *between_type = NULL;
- static entity *old_bp_ent = NULL;
+ static ir_entity *old_bp_ent = NULL;
if(!between_type) {
- entity *ret_addr_ent;
+ ir_entity *ret_addr_ent;
ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
- set_entity_offset_bytes(old_bp_ent, 0);
- set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
+ set_entity_offset(old_bp_ent, 0);
+ set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
}
// ir_node *regs[16];
// int n_regs = 0;
arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
- static const arm_register_req_t *fp_req[] = {
- &arm_default_req_arm_gp_r11
- };
ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
// set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
// arch_set_irn_register(env->arch_env, sp, env->isa->sp);
store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
- set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
-// arch_set_irn_register(env->arch_env, store, env->isa->sp);
+ // TODO
+ // set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
+ // arch_set_irn_register(env->arch_env, store, env->isa->sp);
sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
- arch_set_irn_register(env->arch_env, sp, env->isa->sp);
+ arch_set_irn_register(env->arch_env, sp, env->isa->sp);
*mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
- be_node_set_reg_class(keep, 1, gp);
- arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
- be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
+ be_node_set_reg_class(keep, 1, gp);
+ arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
+ be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
new_tarval_from_long(4, get_irn_mode(fp)));
- set_arm_req_out_all(fp, fp_req);
- //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
- arch_set_irn_register(env->arch_env, fp, env->isa->bp);
+ // TODO...
+ //set_arm_req_out_all(fp, fp_req);
+ //set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
+ arch_set_irn_register(env->arch_env, fp, env->isa->bp);
// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
// be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
- static const arm_register_req_t *sub12_req[] = {
- &arm_default_req_arm_gp_sp
- };
-// TODO: Activate Omit fp in epilogue
+ // TODO: Activate Omit fp in epilogue
if(env->flags.try_omit_fp) {
curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
add_irn_dep(curr_sp, *mem);
curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
+ be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
} else {
ir_node *sub12_node;
ir_node *load_node;
tarval *tv = new_tarval_from_long(12,mode_Iu);
sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
- set_arm_req_out_all(sub12_node, sub12_req);
+ // FIXME
+ //set_arm_req_out_all(sub12_node, sub12_req);
arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
- set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
- set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
- set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
+ // FIXME
+ //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
+ //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
+ //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
}
int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
- return is_arm_irn(irn);
+ if(!is_arm_irn(irn))
+ return -1;
+
+ return 1;
}
/**
return NULL;
}
+/**
+ * Return irp irgs in the desired order.
+ */
+static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
+ return NULL;
+}
+
+/**
+ * Called by the frontend to encode a register name into a backend specific way
+ */
+static unsigned arm_register_from_name(const char *regname) {
+ /* NYI */
+ return 0;
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
static const backend_params *arm_get_libfirm_params(void) {
static arch_dep_params_t ad = {
1, /* allow subs */
- 0, /* Muls are fast enough on ARM */
- 31, /* shift would be ok */
+ 1, /* Muls are fast enough on ARM but ... */
+ 1, /* ... one shift would be possible better */
0, /* SMUL is needed, only in Arch M*/
0, /* UMUL is needed, only in Arch M */
32, /* SMUL & UMUL available for 32 bit */
};
static backend_params p = {
+ 1, /* need dword lowering */
+ 0, /* don't support inlien assembler yet */
NULL, /* no additional opcodes */
NULL, /* will be set later */
- 1, /* need dword lowering */
NULL, /* but yet no creator function */
NULL, /* context for create_intrinsic_fkt */
+ arm_register_from_name, /* register names */
};
p.dep_param = &ad;
return &p;
}
-#ifdef WITH_LIBCORE
-
/* fpu set architectures. */
static const lc_opt_enum_int_items_t arm_fpu_items[] = {
{ "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
{ NULL }
};
-/**
- * Register command line options for the ARM backend.
- *
- * Options so far:
- *
- * arm-fpuunit=unit select the floating point unit
- * arm-gen_reg_names use generic register names instead of SP, LR, PC
- */
-static void arm_register_options(lc_opt_entry_t *ent)
-{
- lc_opt_entry_t *be_grp_arm = lc_opt_get_grp(ent, "arm");
- lc_opt_add_table(be_grp_arm, arm_options);
-}
-#endif /* WITH_LIBCORE */
-
const arch_isa_if_t arm_isa_if = {
arm_init,
arm_done,
arm_get_libfirm_params,
arm_get_allowed_execution_units,
arm_get_machine,
-#ifdef WITH_LIBCORE
- arm_register_options
-#endif
+ arm_get_irg_list,
};
+
+void be_init_arch_arm(void)
+{
+ lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
+ lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
+
+ lc_opt_add_table(arm_grp, arm_options);
+
+ be_register_isa_if("arm", &arm_isa_if);
+}
+
+BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);
projects / libfirm / blobdiff