-/* The main arm backend driver file. */
-/* $Id$ */
+/*
+ * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
+/**
+ * @file
+ * @brief The main arm backend driver file.
+ * @author Oliver Richter, Tobias Gneist
+ * @version $Id$
+ */
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "../beilpsched.h"
#include "../bemodule.h"
#include "../beirg_t.h"
+#include "../bespillslots.h"
+#include "../begnuas.h"
#include "bearch_arm_t.h"
#include "arm_new_nodes.h" /* arm nodes interface */
#include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
-#include "arm_gen_decls.h" /* interface declaration emitter */
#include "arm_transform.h"
#include "arm_emitter.h"
#include "arm_map_regs.h"
/* Some stuff you need to do immediately after register allocation */
}
+/**
+ * We transform Spill and Reload here. This needs to be done before
+ * stack biasing otherwise we would miss the corrected offset for these nodes.
+ */
+static void arm_after_ra(void *self) {
+ arm_code_gen_t *cg = self;
+ be_coalesce_spillslots(cg->birg);
+}
/**
* Emits the code, closes the output file and frees
*/
static void arm_emit_and_done(void *self) {
arm_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
- FILE *out = cg->isa->out;
-
- if (cg->emit_decls) {
- arm_gen_decls(out);
- cg->emit_decls = 0;
- }
+ ir_graph *irg = cg->irg;
dump_ir_block_graph_sched(irg, "-arm-finished");
- arm_gen_routine(out, irg, cg);
+ arm_gen_routine(cg, irg);
cur_reg_set = NULL;
*
* Handle some special cases here:
* 1.) A constant: simply split into two
- * 2.) A load: siply split into two
+ * 2.) A load: simply split into two
*/
static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
ir_node **resH, ir_node **resL) {
*
* Handle some special cases here:
* 1.) A constant: simply move
- * 2.) A load: siply load
+ * 2.) A load: simply load
*/
static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
if (is_Const(arg)) {
NULL, /* spill */
arm_before_sched, /* before scheduling hook */
arm_before_ra, /* before register allocation hook */
- NULL, /* after register allocation */
+ arm_after_ra,
arm_finish_irg,
arm_emit_and_done,
};
FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
- isa->num_codegens++;
-
- if (isa->num_codegens > 1)
- cg->emit_decls = 0;
- else
- cg->emit_decls = 1;
-
cur_reg_set = cg->reg_set;
arm_irn_ops.cg = cg;
* to runtime calls.
*/
static void arm_handle_intrinsics(void) {
- ir_type *tp, *int_tp, *uint_tp;
- i_record records[8];
- int n_records = 0;
+ ir_type *tp, *int_tp, *uint_tp;
+ i_record records[8];
+ int n_records = 0;
#define ID(x) new_id_from_chars(x, sizeof(x)-1)
- int_tp = new_type_primitive(ID("int"), mode_Is);
- uint_tp = new_type_primitive(ID("uint"), mode_Iu);
+ int_tp = new_type_primitive(ID("int"), mode_Is);
+ uint_tp = new_type_primitive(ID("uint"), mode_Iu);
/* ARM has neither a signed div instruction ... */
- {
- runtime_rt rt_Div;
- i_instr_record *map_Div = &records[n_records++].i_instr;
-
- tp = new_type_method(ID("rt_iDiv"), 2, 1);
- set_method_param_type(tp, 0, int_tp);
- set_method_param_type(tp, 1, int_tp);
- set_method_res_type(tp, 0, int_tp);
-
- rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
- rt_Div.mode = mode_T;
- rt_Div.mem_proj_nr = pn_Div_M;
- rt_Div.exc_proj_nr = pn_Div_X_except;
- rt_Div.exc_mem_proj_nr = pn_Div_M;
- rt_Div.res_proj_nr = pn_Div_res;
-
- set_entity_visibility(rt_Div.ent, visibility_external_allocated);
-
- map_Div->kind = INTRINSIC_INSTR;
- map_Div->op = op_Div;
- map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Div->ctx = &rt_Div;
- }
- /* ... nor a signed div instruction ... */
- {
- runtime_rt rt_Div;
- i_instr_record *map_Div = &records[n_records++].i_instr;
-
- tp = new_type_method(ID("rt_uDiv"), 2, 1);
- set_method_param_type(tp, 0, uint_tp);
- set_method_param_type(tp, 1, uint_tp);
- set_method_res_type(tp, 0, uint_tp);
-
- rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
- rt_Div.mode = mode_T;
- rt_Div.mem_proj_nr = pn_Div_M;
- rt_Div.exc_proj_nr = pn_Div_X_except;
- rt_Div.exc_mem_proj_nr = pn_Div_M;
- rt_Div.res_proj_nr = pn_Div_res;
-
- set_entity_visibility(rt_Div.ent, visibility_external_allocated);
-
- map_Div->kind = INTRINSIC_INSTR;
- map_Div->op = op_Div;
- map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Div->ctx = &rt_Div;
- }
+ {
+ runtime_rt rt_Div;
+ i_instr_record *map_Div = &records[n_records++].i_instr;
+
+ tp = new_type_method(ID("rt_iDiv"), 2, 1);
+ set_method_param_type(tp, 0, int_tp);
+ set_method_param_type(tp, 1, int_tp);
+ set_method_res_type(tp, 0, int_tp);
+
+ rt_Div.ent = new_entity(get_glob_type(), ID("__divsi3"), tp);
+ rt_Div.mode = mode_T;
+ rt_Div.res_mode = mode_Is;
+ rt_Div.mem_proj_nr = pn_Div_M;
+ rt_Div.regular_proj_nr = pn_Div_X_regular;
+ rt_Div.exc_proj_nr = pn_Div_X_except;
+ rt_Div.exc_mem_proj_nr = pn_Div_M;
+ rt_Div.res_proj_nr = pn_Div_res;
+
+ set_entity_visibility(rt_Div.ent, visibility_external_allocated);
+
+ map_Div->kind = INTRINSIC_INSTR;
+ map_Div->op = op_Div;
+ map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+ map_Div->ctx = &rt_Div;
+ }
+ /* ... nor an unsigned div instruction ... */
+ {
+ runtime_rt rt_Div;
+ i_instr_record *map_Div = &records[n_records++].i_instr;
+
+ tp = new_type_method(ID("rt_uDiv"), 2, 1);
+ set_method_param_type(tp, 0, uint_tp);
+ set_method_param_type(tp, 1, uint_tp);
+ set_method_res_type(tp, 0, uint_tp);
+
+ rt_Div.ent = new_entity(get_glob_type(), ID("__udivsi3"), tp);
+ rt_Div.mode = mode_T;
+ rt_Div.res_mode = mode_Iu;
+ rt_Div.mem_proj_nr = pn_Div_M;
+ rt_Div.regular_proj_nr = pn_Div_X_regular;
+ rt_Div.exc_proj_nr = pn_Div_X_except;
+ rt_Div.exc_mem_proj_nr = pn_Div_M;
+ rt_Div.res_proj_nr = pn_Div_res;
+
+ set_entity_visibility(rt_Div.ent, visibility_external_allocated);
+
+ map_Div->kind = INTRINSIC_INSTR;
+ map_Div->op = op_Div;
+ map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+ map_Div->ctx = &rt_Div;
+ }
/* ... nor a signed mod instruction ... */
- {
- runtime_rt rt_Mod;
- i_instr_record *map_Mod = &records[n_records++].i_instr;
-
- tp = new_type_method(ID("rt_iMod"), 2, 1);
- set_method_param_type(tp, 0, int_tp);
- set_method_param_type(tp, 1, int_tp);
- set_method_res_type(tp, 0, int_tp);
-
- rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
- rt_Mod.mode = mode_T;
- rt_Mod.mem_proj_nr = pn_Mod_M;
- rt_Mod.exc_proj_nr = pn_Mod_X_except;
- rt_Mod.exc_mem_proj_nr = pn_Mod_M;
- rt_Mod.res_proj_nr = pn_Mod_res;
-
- set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
-
- map_Mod->kind = INTRINSIC_INSTR;
- map_Mod->op = op_Mod;
- map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Mod->ctx = &rt_Mod;
- }
- /* ... nor a unsigned mod. */
- {
- runtime_rt rt_Mod;
- i_instr_record *map_Mod = &records[n_records++].i_instr;
-
- tp = new_type_method(ID("rt_uMod"), 2, 1);
- set_method_param_type(tp, 0, uint_tp);
- set_method_param_type(tp, 1, uint_tp);
- set_method_res_type(tp, 0, uint_tp);
-
- rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
- rt_Mod.mode = mode_T;
- rt_Mod.mem_proj_nr = pn_Mod_M;
- rt_Mod.exc_proj_nr = pn_Mod_X_except;
- rt_Mod.exc_mem_proj_nr = pn_Mod_M;
- rt_Mod.res_proj_nr = pn_Mod_res;
-
- set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
-
- map_Mod->kind = INTRINSIC_INSTR;
- map_Mod->op = op_Mod;
- map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
- map_Mod->ctx = &rt_Mod;
- }
-
- if (n_records > 0)
- lower_intrinsics(records, n_records);
+ {
+ runtime_rt rt_Mod;
+ i_instr_record *map_Mod = &records[n_records++].i_instr;
+
+ tp = new_type_method(ID("rt_iMod"), 2, 1);
+ set_method_param_type(tp, 0, int_tp);
+ set_method_param_type(tp, 1, int_tp);
+ set_method_res_type(tp, 0, int_tp);
+
+ rt_Mod.ent = new_entity(get_glob_type(), ID("__modsi3"), tp);
+ rt_Mod.mode = mode_T;
+ rt_Mod.res_mode = mode_Is;
+ rt_Mod.mem_proj_nr = pn_Mod_M;
+ rt_Mod.regular_proj_nr = pn_Mod_X_regular;
+ rt_Mod.exc_proj_nr = pn_Mod_X_except;
+ rt_Mod.exc_mem_proj_nr = pn_Mod_M;
+ rt_Mod.res_proj_nr = pn_Mod_res;
+
+ set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
+
+ map_Mod->kind = INTRINSIC_INSTR;
+ map_Mod->op = op_Mod;
+ map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+ map_Mod->ctx = &rt_Mod;
+ }
+ /* ... nor an unsigned mod. */
+ {
+ runtime_rt rt_Mod;
+ i_instr_record *map_Mod = &records[n_records++].i_instr;
+
+ tp = new_type_method(ID("rt_uMod"), 2, 1);
+ set_method_param_type(tp, 0, uint_tp);
+ set_method_param_type(tp, 1, uint_tp);
+ set_method_res_type(tp, 0, uint_tp);
+
+ rt_Mod.ent = new_entity(get_glob_type(), ID("__umodsi3"), tp);
+ rt_Mod.mode = mode_T;
+ rt_Mod.res_mode = mode_Iu;
+ rt_Mod.mem_proj_nr = pn_Mod_M;
+ rt_Mod.regular_proj_nr = pn_Mod_X_regular;
+ rt_Mod.exc_proj_nr = pn_Mod_X_except;
+ rt_Mod.exc_mem_proj_nr = pn_Mod_M;
+ rt_Mod.res_proj_nr = pn_Mod_res;
+
+ set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
+
+ map_Mod->kind = INTRINSIC_INSTR;
+ map_Mod->op = op_Mod;
+ map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+ map_Mod->ctx = &rt_Mod;
+ }
+
+ if (n_records > 0)
+ lower_intrinsics(records, n_records);
}
/*****************************************************************
*****************************************************************/
static arm_isa_t arm_isa_template = {
- &arm_isa_if, /* isa interface */
- &arm_gp_regs[REG_SP], /* stack pointer */
- &arm_gp_regs[REG_R11], /* base pointer */
- -1, /* stack direction */
- 0, /* number of codegenerator objects */
+ {
+ &arm_isa_if, /* isa interface */
+ &arm_gp_regs[REG_SP], /* stack pointer */
+ &arm_gp_regs[REG_R11], /* base pointer */
+ -1, /* stack direction */
+ NULL, /* main environment */
+ 7, /* spill costs */
+ 5, /* reload costs */
+ },
0, /* use generic register names instead of SP, LR, PC */
- NULL, /* current code generator */
- NULL, /* output file */
ARM_FPU_ARCH_FPE, /* FPU architecture */
+ NULL, /* current code generator */
+ { NULL, }, /* emitter environment */
};
/**
memcpy(isa, &arm_isa_template, sizeof(*isa));
arm_register_init(isa);
- if (isa->gen_reg_names) {
- /* patch register names */
- arm_gp_regs[REG_R11].name = "r11";
- arm_gp_regs[REG_SP].name = "r13";
- arm_gp_regs[REG_LR].name = "r14";
- arm_gp_regs[REG_PC].name = "r15";
- }
isa->cg = NULL;
- isa->out = file_handle;
+ be_emit_init_env(&isa->emit, file_handle);
arm_create_opcodes();
arm_handle_intrinsics();
- arm_switch_section(NULL, NO_SECTION);
+
+ /* we mark referenced global entities, so we can only emit those which
+ * are actually referenced. (Note: you mustn't use the type visited flag
+ * elsewhere in the backend)
+ */
+ inc_master_type_visited();
inited = 1;
return isa;
/**
- * frees the ISA structure.
+ * Closes the output file and frees the ISA structure.
*/
static void arm_done(void *self) {
+ arm_isa_t *isa = self;
+
+ be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
+
+ be_emit_destroy_env(&isa->emit);
free(self);
}
curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
+ be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
} else {
ir_node *sub12_node;
ir_node *load_node;
}
int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
- return is_arm_irn(irn);
+ if(!is_arm_irn(irn))
+ return -1;
+
+ return 1;
}
/**
return NULL;
}
+/**
+ * Called by the frontend to encode a register name into a backend specific way
+ */
+static unsigned arm_register_from_name(const char *regname) {
+ /* NYI */
+ return 0;
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
static const backend_params *arm_get_libfirm_params(void) {
static arch_dep_params_t ad = {
1, /* allow subs */
- 0, /* Muls are fast enough on ARM */
- 31, /* shift would be ok */
+ 1, /* Muls are fast enough on ARM but ... */
+ 1, /* ... one shift would be possible better */
0, /* SMUL is needed, only in Arch M*/
0, /* UMUL is needed, only in Arch M */
32, /* SMUL & UMUL available for 32 bit */
};
static backend_params p = {
+ 1, /* need dword lowering */
+ 0, /* don't support inlien assembler yet */
NULL, /* no additional opcodes */
NULL, /* will be set later */
- 1, /* need dword lowering */
NULL, /* but yet no creator function */
NULL, /* context for create_intrinsic_fkt */
+ arm_register_from_name, /* register names */
};
p.dep_param = &ad;
projects / libfirm / blobdiff