use default error handler if none is specified

[libfirm] / ir / be / arm / bearch_arm.c

diff --git a/ir/be/arm/bearch_arm.c b/ir/be/arm/bearch_arm.c
index 6cec1ee..3040ca4 100644 (file)
--- a/ir/be/arm/bearch_arm.c
+++ b/ir/be/arm/bearch_arm.c
@@ -23,9 +23,7 @@
  * @author  Oliver Richter, Tobias Gneist
  * @version $Id$
  */
-#ifdef HAVE_CONFIG_H
 #include "config.h"
-#endif
 
 #include "lc_opts.h"
 #include "lc_opts_enum.h"
@@ -191,9 +189,6 @@ static arch_irn_class_t arm_classify(const ir_node *irn)
        if (is_cfop(irn)) {
                return arch_irn_class_branch;
        }
-       else if (is_arm_irn(irn)) {
-               return arch_irn_class_normal;
-       }
 
        return 0;
 }
@@ -585,7 +580,6 @@ static void *arm_cg_init(be_irg_t *birg) {
        cg->impl         = &arm_code_gen_if;
        cg->irg          = birg->irg;
        cg->reg_set      = new_set(arm_cmp_irn_reg_assoc, 1024);
-       cg->arch_env     = birg->main_env->arch_env;
        cg->isa          = isa;
        cg->birg         = birg;
        cg->int_tp       = int_tp;
@@ -937,24 +931,24 @@ static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *
        block = get_irg_start_block(irg);
 
        ip = be_new_Copy(gp, irg, block, sp);
-       arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
+       arch_set_irn_register(ip, &arm_gp_regs[REG_R12]);
        be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
 
        store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
 
        sp = new_r_Proj(irg, block, store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
-       arch_set_irn_register(env->arch_env, sp, env->arch_env->sp);
+       arch_set_irn_register(sp, env->arch_env->sp);
        *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
 
        keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
        be_node_set_reg_class(keep, 1, gp);
-       arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
+       arch_set_irn_register(keep, &arm_gp_regs[REG_R12]);
        be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
 
        fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), 4);
-       arch_set_irn_register(env->arch_env, fp, env->arch_env->bp);
+       arch_set_irn_register(fp, env->arch_env->bp);
        fp = be_new_Copy(gp, irg, block, fp); // XXX Gammelfix: only be_ nodes can have the ignore flag set
-       arch_set_irn_register(env->arch_env, fp, env->arch_env->bp);
+       arch_set_irn_register(fp, env->arch_env->bp);
        be_node_set_flags(fp, BE_OUT_POS(0), arch_irn_flags_ignore);
 
        be_abi_reg_map_set(reg_map, env->arch_env->bp, fp);
@@ -982,11 +976,11 @@ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_m
 
                curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
                be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
-               arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
+               arch_set_irn_register(curr_lr, &arm_gp_regs[REG_LR]);
                be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
 
                curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
-               arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
+               arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
                be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
                be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
        } else {
@@ -995,7 +989,7 @@ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_m
                sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, 12);
                // FIXME
                //set_arm_req_out_all(sub12_node, sub12_req);
-               arch_set_irn_register(env->arch_env, sub12_node, env->arch_env->sp);
+               arch_set_irn_register(sub12_node, env->arch_env->sp);
                load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
                // FIXME
                //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
@@ -1005,9 +999,9 @@ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_m
                curr_sp = new_r_Proj(env->irg, bl, load_node, env->arch_env->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
                curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
                *mem    = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
-               arch_set_irn_register(env->arch_env, curr_bp, env->arch_env->bp);
-               arch_set_irn_register(env->arch_env, curr_sp, env->arch_env->sp);
-               arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
+               arch_set_irn_register(curr_bp, env->arch_env->bp);
+               arch_set_irn_register(curr_sp, env->arch_env->sp);
+               arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
        }
        be_abi_reg_map_set(reg_map, env->arch_env->sp, curr_sp);
        be_abi_reg_map_set(reg_map, env->arch_env->bp, curr_bp);