* @author Oliver Richter, Tobias Gneist
* @version $Id$
*/
-#ifdef HAVE_CONFIG_H
#include "config.h"
-#endif
#include "lc_opts.h"
#include "lc_opts_enum.h"
#include "irgopt.h"
#include "iroptimize.h"
#include "lowering.h"
+#include "error.h"
#include "bitset.h"
#include "debug.h"
+#include "array_t.h"
#include "irtools.h"
#include "../bearch_t.h" /* the general register allocator interface */
#include "arm_new_nodes.h" /* arm nodes interface */
#include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */
#include "arm_transform.h"
+#include "arm_optimize.h"
#include "arm_emitter.h"
#include "arm_map_regs.h"
if (is_cfop(irn)) {
return arch_irn_class_branch;
}
- else if (is_arm_irn(irn)) {
- return arch_irn_class_normal;
- }
return 0;
}
return flags;
}
-static ir_entity *arm_get_frame_entity(const ir_node *irn)
-{
+static ir_entity *arm_get_frame_entity(const ir_node *irn) {
+ /* we do NOT transform be_Spill or be_Reload nodes, so we never
+ have frame access using ARM nodes. */
(void) irn;
- /* TODO: return the entity assigned to the frame */
return NULL;
}
-static void arm_set_frame_entity(ir_node *irn, ir_entity *ent)
-{
+static void arm_set_frame_entity(ir_node *irn, ir_entity *ent) {
(void) irn;
(void) ent;
- /* TODO: set the entity assigned to the frame */
+ panic("arm_set_frame_entity() called. This should not happen.");
}
/**
*/
static void arm_finish_irg(void *self)
{
- (void) self;
- /* TODO: - fix offsets for nodes accessing stack
- - ...
- */
+ arm_code_gen_t *cg = self;
+
+ /* do peephole optimizations and fix stack offsets */
+ arm_peephole_optimization(cg);
}
v = (v << 8) | get_tarval_sub_bits(tv, 1);
v = (v << 8) | get_tarval_sub_bits(tv, 0);
*resL = new_Const_long(mode_Is, v);
- }
- else if (get_irn_op(skip_Proj(arg)) == op_Load) {
+ } else if (is_Load(skip_Proj(arg))) {
/* FIXME: handling of low/high depends on LE/BE here */
- assert(0);
+ panic("Unimplemented convert_dbl_to_int() case");
}
else {
ir_graph *irg = current_ir_graph;
v = (v << 8) | get_tarval_sub_bits(tv, 1);
v = (v << 8) | get_tarval_sub_bits(tv, 0);
return new_Const_long(mode_Is, v);
- }
- else if (get_irn_op(skip_Proj(arg)) == op_Load) {
+ } else if (is_Load(skip_Proj(arg))) {
ir_node *load;
load = skip_Proj(arg);
}
- assert(0);
- return NULL;
+ panic("Unimplemented convert_sng_to_int() case");
}
/**
*/
static void *arm_cg_init(be_irg_t *birg) {
static ir_type *int_tp = NULL;
- arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env.isa;
+ arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env;
arm_code_gen_t *cg;
if (! int_tp) {
int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is);
}
- cg = xmalloc(sizeof(*cg));
+ cg = XMALLOC(arm_code_gen_t);
cg->impl = &arm_code_gen_if;
cg->irg = birg->irg;
cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024);
- cg->arch_env = &birg->main_env->arch_env;
cg->isa = isa;
cg->birg = birg;
cg->int_tp = int_tp;
&arm_gp_regs[REG_SP], /* stack pointer */
&arm_gp_regs[REG_R11], /* base pointer */
-1, /* stack direction */
- 1, /* stack alignment for calls */
+ 2, /* power of two stack alignment for calls, 2^2 == 4 */
NULL, /* main environment */
7, /* spill costs */
5, /* reload costs */
/**
* Initializes the backend ISA and opens the output file.
*/
-static void *arm_init(FILE *file_handle) {
+static arch_env_t *arm_init(FILE *file_handle) {
static int inited = 0;
arm_isa_t *isa;
- if(inited)
+ if (inited)
return NULL;
- isa = xmalloc(sizeof(*isa));
+ isa = XMALLOC(arm_isa_t);
memcpy(isa, &arm_isa_template, sizeof(*isa));
arm_register_init();
arm_create_opcodes(&arm_irn_ops);
arm_handle_intrinsics();
+ /* needed for the debug support */
+ be_gas_emit_switch_section(GAS_SECTION_TEXT);
+ be_emit_cstring(".Ltext0:\n");
+ be_emit_write_line();
+
/* we mark referenced global entities, so we can only emit those which
* are actually referenced. (Note: you mustn't use the type visited flag
* elsewhere in the backend)
inc_master_type_visited();
inited = 1;
- return isa;
+ return &isa->arch_env;
}
static void arm_done(void *self) {
arm_isa_t *isa = self;
- be_gas_emit_decls(isa->arch_isa.main_env, 1);
+ be_gas_emit_decls(isa->arch_env.main_env, 1);
be_emit_exit();
free(self);
typedef struct {
be_abi_call_flags_bits_t flags;
const arch_env_t *arch_env;
- const arch_isa_t *isa;
ir_graph *irg;
} arm_abi_env_t;
static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
{
- arm_abi_env_t *env = xmalloc(sizeof(env[0]));
- be_abi_call_flags_t fl = be_abi_call_get_flags(call);
+ arm_abi_env_t *env = XMALLOC(arm_abi_env_t);
+ be_abi_call_flags_t fl = be_abi_call_get_flags(call);
env->flags = fl.bits;
env->irg = irg;
env->arch_env = arch_env;
- env->isa = arch_env->isa;
return env;
}
+/**
+ * Put all registers which are saved by the prologue/epilogue in a set.
+ *
+ * @param self The callback object.
+ * @param s The result set.
+ */
static void arm_abi_dont_save_regs(void *self, pset *s)
{
arm_abi_env_t *env = self;
if (env->flags.try_omit_fp)
- pset_insert_ptr(s, env->isa->bp);
+ pset_insert_ptr(s, env->arch_env->bp);
}
-
-
/**
- * Build the ARM prolog
+ * Generate the routine prologue.
+ *
+ * @param self The callback object.
+ * @param mem A pointer to the mem node. Update this if you define new memory.
+ * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param stack_bias Points to the current stack bias, can be modified if needed.
+ *
+ * @return The register which shall be used as a stack frame base.
+ *
+ * All nodes which define registers in @p reg_map must keep @p reg_map current.
*/
-static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) {
- ir_node *keep, *store;
- arm_abi_env_t *env = self;
- ir_graph *irg = env->irg;
- ir_node *block = get_irg_start_block(irg);
- arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
+static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias) {
+ arm_abi_env_t *env = self;
+ ir_node *keep, *store;
+ ir_graph *irg;
+ ir_node *block;
+ arch_register_class_t *gp;
- ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
- ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
- ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp);
- ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
- ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
+ ir_node *fp, *ip, *lr, *pc;
+ ir_node *sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
+
+ (void) stack_bias;
if (env->flags.try_omit_fp)
- return env->isa->sp;
+ return env->arch_env->sp;
+
+ fp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
+ ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
+ lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
+ pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
+
+ gp = &arm_reg_classes[CLASS_arm_gp];
+ irg = env->irg;
+ block = get_irg_start_block(irg);
ip = be_new_Copy(gp, irg, block, sp);
- arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]);
+ arch_set_irn_register(ip, &arm_gp_regs[REG_R12]);
be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
- sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
- arch_set_irn_register(env->arch_env, sp, env->isa->sp);
+ sp = new_r_Proj(irg, block, store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
+ arch_set_irn_register(sp, env->arch_env->sp);
*mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
be_node_set_reg_class(keep, 1, gp);
- arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
+ arch_set_irn_register(keep, &arm_gp_regs[REG_R12]);
be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), 4);
- arch_set_irn_register(env->arch_env, fp, env->isa->bp);
+ arch_set_irn_register(fp, env->arch_env->bp);
+ fp = be_new_Copy(gp, irg, block, fp); // XXX Gammelfix: only be_ nodes can have the ignore flag set
+ arch_set_irn_register(fp, env->arch_env->bp);
+ be_node_set_flags(fp, BE_OUT_POS(0), arch_irn_flags_ignore);
- be_abi_reg_map_set(reg_map, env->isa->bp, fp);
+ be_abi_reg_map_set(reg_map, env->arch_env->bp, fp);
be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
- be_abi_reg_map_set(reg_map, env->isa->sp, sp);
+ be_abi_reg_map_set(reg_map, env->arch_env->sp, sp);
be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr);
be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc);
- return env->isa->bp;
+ return env->arch_env->bp;
}
/**
*/
static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) {
arm_abi_env_t *env = self;
- ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
- ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
+ ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->arch_env->sp);
+ ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->arch_env->bp);
ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
// TODO: Activate Omit fp in epilogue
if (env->flags.try_omit_fp) {
- curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
- add_irn_dep(curr_sp, *mem);
+ curr_sp = be_new_IncSP(env->arch_env->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
- arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]);
+ arch_set_irn_register(curr_lr, &arm_gp_regs[REG_LR]);
be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
- arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
+ arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
} else {
sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, 12);
// FIXME
//set_arm_req_out_all(sub12_node, sub12_req);
- arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
+ arch_set_irn_register(sub12_node, env->arch_env->sp);
load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
// FIXME
//set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
//set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
//set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
- curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
- curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
+ curr_bp = new_r_Proj(env->irg, bl, load_node, env->arch_env->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
+ curr_sp = new_r_Proj(env->irg, bl, load_node, env->arch_env->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
*mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M);
- arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp);
- arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp);
- arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
+ arch_set_irn_register(curr_bp, env->arch_env->bp);
+ arch_set_irn_register(curr_sp, env->arch_env->sp);
+ arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
}
- be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
- be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
+ be_abi_reg_map_set(reg_map, env->arch_env->sp, curr_sp);
+ be_abi_reg_map_set(reg_map, env->arch_env->bp, curr_bp);
be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr);
be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc);
}
(void) self;
(void) irn;
/* TODO */
- assert(0);
- return NULL;
+ panic("Unimplemented arm_get_allowed_execution_units()");
}
static const be_machine_t *arm_get_machine(const void *self) {
(void) self;
/* TODO */
- assert(0);
- return NULL;
+ panic("Unimplemented arm_get_machine()");
}
/**
return 1;
}
+static asm_constraint_flags_t arm_parse_asm_constraint(const void *self, const char **c)
+{
+ /* asm not supported */
+ (void) self;
+ (void) c;
+ return ASM_CONSTRAINT_FLAG_INVALID;
+}
+
+static int arm_is_valid_clobber(const void *self, const char *clobber)
+{
+ (void) self;
+ (void) clobber;
+ return 0;
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
static backend_params p = {
1, /* need dword lowering */
0, /* don't support inline assembler yet */
+ 0, /* no immediate floating point mode. */
NULL, /* no additional opcodes */
NULL, /* will be set later */
NULL, /* but yet no creator function */
NULL, /* context for create_intrinsic_fkt */
NULL, /* will be set below */
+ NULL /* no immediate fp mode */
};
p.dep_param = &ad;
arm_get_allowed_execution_units,
arm_get_machine,
arm_get_irg_list,
+ NULL, /* mark remat */
+ arm_parse_asm_constraint,
+ arm_is_valid_clobber
};
void be_init_arch_arm(void)
projects / libfirm / blobdiff