* @file
* @brief The codegenerator (transform FIRM into arm FIRM)
* @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
- * @version $Id$
*/
#include "config.h"
#include "irmode_t.h"
#include "irgmod.h"
#include "iredges.h"
-#include "irvrfy.h"
#include "ircons.h"
#include "irprintf.h"
#include "dbginfo.h"
#include "iropt_t.h"
#include "debug.h"
#include "error.h"
+#include "util.h"
-#include "../benode.h"
-#include "../beirg.h"
-#include "../beutil.h"
-#include "../betranshlp.h"
-#include "../beabihelper.h"
-#include "../beabi.h"
+#include "benode.h"
+#include "beirg.h"
+#include "beutil.h"
+#include "betranshlp.h"
+#include "beabihelper.h"
+#include "beabi.h"
#include "bearch_arm_t.h"
#include "arm_nodes_attr.h"
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-/** hold the current code generator during transformation */
-static arm_code_gen_t *env_cg;
-
-static const arch_register_t *sp_reg = &arm_gp_regs[REG_SP];
+static const arch_register_t *sp_reg = &arm_registers[REG_SP];
static ir_mode *mode_gp;
static ir_mode *mode_fp;
static beabi_helper_env_t *abihelper;
+static be_stackorder_t *stackorder;
static calling_convention_t *cconv = NULL;
+static arm_isa_t *isa;
static pmap *node_to_stack;
+static const arch_register_t *const callee_saves[] = {
+ &arm_registers[REG_R4],
+ &arm_registers[REG_R5],
+ &arm_registers[REG_R6],
+ &arm_registers[REG_R7],
+ &arm_registers[REG_R8],
+ &arm_registers[REG_R9],
+ &arm_registers[REG_R10],
+ &arm_registers[REG_R11],
+ &arm_registers[REG_LR],
+};
+
+static const arch_register_t *const caller_saves[] = {
+ &arm_registers[REG_R0],
+ &arm_registers[REG_R1],
+ &arm_registers[REG_R2],
+ &arm_registers[REG_R3],
+ &arm_registers[REG_LR],
+
+ &arm_registers[REG_F0],
+ &arm_registers[REG_F1],
+ &arm_registers[REG_F2],
+ &arm_registers[REG_F3],
+ &arm_registers[REG_F4],
+ &arm_registers[REG_F5],
+ &arm_registers[REG_F6],
+ &arm_registers[REG_F7],
+};
+
static bool mode_needs_gp_reg(ir_mode *mode)
{
return mode_is_int(mode) || mode_is_reference(mode);
if (vn.ops < v.ops) {
/* remove bits */
result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
- be_dep_on_frame(result);
for (cnt = 1; cnt < vn.ops; ++cnt) {
result = new_bd_arm_Bic_imm(dbgi, block, result,
} else {
/* add bits */
result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
- be_dep_on_frame(result);
for (cnt = 1; cnt < v.ops; ++cnt) {
result = new_bd_arm_Or_imm(dbgi, block, result,
*/
static ir_node *create_const_graph(ir_node *irn, ir_node *block)
{
- tarval *tv = get_Const_tarval(irn);
- ir_mode *mode = get_tarval_mode(tv);
- unsigned value;
+ ir_tarval *tv = get_Const_tarval(irn);
+ ir_mode *mode = get_tarval_mode(tv);
+ unsigned value;
if (mode_is_reference(mode)) {
/* ARM is 32bit, so we can safely convert a reference tarval into Iu */
return new_op;
if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
- if (USE_FPA(env_cg->isa)) {
+ if (USE_FPA(isa)) {
if (mode_is_float(src_mode)) {
if (mode_is_float(dst_mode)) {
/* from float to float */
return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
}
}
- } else if (USE_VFP(env_cg->isa)) {
+ } else if (USE_VFP(isa)) {
panic("VFP not supported yet");
} else {
panic("Softfloat not supported yet");
MATCH_SIZE_NEUTRAL = 1 << 2,
MATCH_SKIP_NOT = 1 << 3, /**< skip Not on ONE input */
} match_flags_t;
+ENUM_BITSET(match_flags_t)
/**
* possible binop constructors.
}
if (try_encode_as_immediate(op2, &imm)) {
- ir_node *new_op1 = be_transform_node(op1);
+ new_op1 = be_transform_node(op1);
return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
}
new_op2 = be_transform_node(op2);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *new_op1 = be_transform_node(op1);
ir_node *new_op2 = be_transform_node(op2);
- if (USE_FPA(env_cg->isa)) {
+ if (USE_FPA(isa)) {
return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
- } else if (USE_VFP(env_cg->isa)) {
- assert(mode != mode_E && "IEEE Extended FP not supported");
+ } else if (USE_VFP(isa)) {
panic("VFP not supported yet");
} else {
panic("Softfloat not supported yet");
dbg_info *dbg = get_irn_dbg_info(node);
if (mode_is_float(mode)) {
- if (USE_FPA(env_cg->isa)) {
+ if (USE_FPA(isa)) {
return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
- } else if (USE_VFP(env_cg->isa)) {
- assert(mode != mode_E && "IEEE Extended FP not supported");
+ } else if (USE_VFP(isa)) {
panic("VFP not supported yet");
} else {
panic("Softfloat not supported yet");
return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
}
-static ir_node *gen_Quot(ir_node *node)
+static ir_node *gen_Div(ir_node *node)
{
ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *op1 = get_Quot_left(node);
+ ir_node *op1 = get_Div_left(node);
ir_node *new_op1 = be_transform_node(op1);
- ir_node *op2 = get_Quot_right(node);
+ ir_node *op2 = get_Div_right(node);
ir_node *new_op2 = be_transform_node(op2);
- ir_mode *mode = get_irn_mode(node);
+ ir_mode *mode = get_Div_resmode(node);
dbg_info *dbg = get_irn_dbg_info(node);
- assert(mode != mode_E && "IEEE Extended FP not supported");
+ /* integer division should be replaced by builtin call */
+ assert(mode_is_float(mode));
- if (USE_FPA(env_cg->isa)) {
+ if (USE_FPA(isa)) {
return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
- } else if (USE_VFP(env_cg->isa)) {
- assert(mode != mode_E && "IEEE Extended FP not supported");
+ } else if (USE_VFP(isa)) {
panic("VFP not supported yet");
} else {
panic("Softfloat not supported yet");
dbg_info *dbgi = get_irn_dbg_info(node);
if (mode_is_float(mode)) {
- if (USE_FPA(env_cg->isa)) {
+ if (USE_FPA(isa)) {
return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
- } else if (USE_VFP(env_cg->isa)) {
- assert(mode != mode_E && "IEEE Extended FP not supported");
+ } else if (USE_VFP(isa)) {
panic("VFP not supported yet");
} else {
panic("Softfloat not supported yet");
ir_node *op1 = get_binop_left(node);
ir_node *op2 = get_binop_right(node);
dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
ir_node *new_op1;
ir_node *new_op2;
+ if (get_mode_modulo_shift(mode) != 32)
+ panic("modulo shift!=32 not supported");
+
if (flags & MATCH_SIZE_NEUTRAL) {
op1 = arm_skip_downconv(op1);
op2 = arm_skip_downconv(op2);
new_op1 = be_transform_node(op1);
if (is_Const(op2)) {
- tarval *tv = get_Const_tarval(op2);
+ ir_tarval *tv = get_Const_tarval(op2);
unsigned int val = get_tarval_long(tv);
assert(tarval_is_long(tv));
if (can_use_shift_constant(val, shift_modifier)) {
if (is_Add(op2)) {
ir_node *right = get_Add_right(op2);
if (is_Const(right)) {
- tarval *tv = get_Const_tarval(right);
- ir_mode *mode = get_irn_mode(node);
- long bits = get_mode_size_bits(mode);
- ir_node *left = get_Add_left(op2);
+ ir_tarval *tv = get_Const_tarval(right);
+ ir_mode *mode = get_irn_mode(node);
+ long bits = get_mode_size_bits(mode);
+ ir_node *left = get_Add_left(op2);
if (is_Minus(left) &&
tarval_is_long(tv) &&
} else if (is_Sub(op2)) {
ir_node *left = get_Sub_left(op2);
if (is_Const(left)) {
- tarval *tv = get_Const_tarval(left);
- ir_mode *mode = get_irn_mode(node);
- long bits = get_mode_size_bits(mode);
- ir_node *right = get_Sub_right(op2);
+ ir_tarval *tv = get_Const_tarval(left);
+ ir_mode *mode = get_irn_mode(node);
+ long bits = get_mode_size_bits(mode);
+ ir_node *right = get_Sub_right(op2);
if (tarval_is_long(tv) &&
get_tarval_long(tv) == bits &&
rotate = gen_Ror(node, op1, right);
}
} else if (is_Const(op2)) {
- tarval *tv = get_Const_tarval(op2);
- ir_mode *mode = get_irn_mode(node);
- long bits = get_mode_size_bits(mode);
+ ir_tarval *tv = get_Const_tarval(op2);
+ ir_mode *mode = get_irn_mode(node);
+ long bits = get_mode_size_bits(mode);
if (tarval_is_long(tv) && bits == 32) {
ir_node *block = be_transform_node(get_nodes_block(node));
ir_mode *mode = get_irn_mode(node);
if (mode_is_float(mode)) {
- if (USE_FPA(env_cg->isa)) {
+ if (USE_FPA(isa)) {
return new_bd_arm_Mvf(dbgi, block, op, mode);
- } else if (USE_VFP(env_cg->isa)) {
- assert(mode != mode_E && "IEEE Extended FP not supported");
+ } else if (USE_VFP(isa)) {
panic("VFP not supported yet");
} else {
panic("Softfloat not supported yet");
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *new_load = NULL;
+ if (get_Load_unaligned(node) == align_non_aligned)
+ panic("unaligned Loads not supported yet");
+
if (mode_is_float(mode)) {
- if (USE_FPA(env_cg->isa)) {
+ if (USE_FPA(isa)) {
new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
NULL, 0, 0, false);
- } else if (USE_VFP(env_cg->isa)) {
- assert(mode != mode_E && "IEEE Extended FP not supported");
+ } else if (USE_VFP(isa)) {
panic("VFP not supported yet");
} else {
panic("Softfloat not supported yet");
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *new_store = NULL;
+ if (get_Store_unaligned(node) == align_non_aligned)
+ panic("unaligned Stores not supported yet");
+
if (mode_is_float(mode)) {
- if (USE_FPA(env_cg->isa)) {
+ if (USE_FPA(isa)) {
new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
new_mem, mode, NULL, 0, 0, false);
- } else if (USE_VFP(env_cg->isa)) {
- assert(mode != mode_E && "IEEE Extended FP not supported");
+ } else if (USE_VFP(isa)) {
panic("VFP not supported yet");
} else {
panic("Softfloat not supported yet");
return new_bd_arm_Jmp(dbgi, new_block);
}
-static ir_node *gen_SwitchJmp(ir_node *node)
+static ir_node *gen_Switch(ir_node *node)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *selector = get_Cond_selector(node);
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *new_op = be_transform_node(selector);
- ir_node *const_graph;
- ir_node *sub;
-
- ir_node *proj;
- const ir_edge_t *edge;
- int min = INT_MAX;
- int max = INT_MIN;
- int translation;
- int pn;
- int n_projs;
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *selector = get_Switch_selector(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_op = be_transform_node(selector);
+ ir_mode *mode = get_irn_mode(selector);
+ const ir_switch_table *table = get_Switch_table(node);
+ unsigned n_outs = get_Switch_n_outs(node);
- foreach_out_edge(node, edge) {
- proj = get_edge_src_irn(edge);
- assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
+ table = ir_switch_table_duplicate(irg, table);
- pn = get_Proj_proj(proj);
+ /* switch with smaller modes not implemented yet */
+ assert(get_mode_size_bits(mode) == 32);
- min = pn<min ? pn : min;
- max = pn>max ? pn : max;
- }
- translation = min;
- n_projs = max - translation + 1;
-
- foreach_out_edge(node, edge) {
- proj = get_edge_src_irn(edge);
- assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
-
- pn = get_Proj_proj(proj) - translation;
- set_Proj_proj(proj, pn);
- }
-
- const_graph = create_const_graph_value(dbgi, block, translation);
- sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
- return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
+ return new_bd_arm_SwitchJmp(dbgi, block, new_op, n_outs, table);
}
static ir_node *gen_Cmp(ir_node *node)
static ir_node *gen_Cond(ir_node *node)
{
- ir_node *selector = get_Cond_selector(node);
- ir_mode *mode = get_irn_mode(selector);
- ir_node *block;
- ir_node *flag_node;
- dbg_info *dbgi;
+ ir_node *selector = get_Cond_selector(node);
+ ir_relation relation;
+ ir_node *block;
+ ir_node *flag_node;
+ dbg_info *dbgi;
- if (mode != mode_b) {
- return gen_SwitchJmp(node);
- }
- assert(is_Proj(selector));
+ assert(is_Cmp(selector));
block = be_transform_node(get_nodes_block(node));
dbgi = get_irn_dbg_info(node);
- flag_node = be_transform_node(get_Proj_pred(selector));
+ flag_node = be_transform_node(selector);
+ relation = get_Cmp_relation(selector);
- return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector));
+ return new_bd_arm_B(dbgi, block, flag_node, relation);
}
-static tarval *fpa_imm[3][fpa_max];
+enum fpa_imm_mode {
+ FPA_IMM_FLOAT = 0,
+ FPA_IMM_DOUBLE = 1,
+ FPA_IMM_MAX = FPA_IMM_DOUBLE
+};
+
+static ir_tarval *fpa_imm[FPA_IMM_MAX + 1][fpa_max];
#if 0
/**
switch (get_mode_size_bits(mode)) {
case 32:
- i = 0;
+ i = FPA_IMM_FLOAT;
break;
case 64:
- i = 1;
+ i = FPA_IMM_DOUBLE;
break;
- default:
- i = 2;
}
if (tarval_is_negative(tv)) {
dbg_info *dbg = get_irn_dbg_info(node);
if (mode_is_float(mode)) {
- if (USE_FPA(env_cg->isa)) {
- tarval *tv = get_Const_tarval(node);
- node = new_bd_arm_fConst(dbg, block, tv);
- be_dep_on_frame(node);
+ if (USE_FPA(isa)) {
+ ir_tarval *tv = get_Const_tarval(node);
+ node = new_bd_arm_fConst(dbg, block, tv);
return node;
- } else if (USE_VFP(env_cg->isa)) {
- assert(mode != mode_E && "IEEE Extended FP not supported");
+ } else if (USE_VFP(isa)) {
panic("VFP not supported yet");
} else {
panic("Softfloat not supported yet");
ir_node *new_node;
new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
- be_dep_on_frame(new_node);
return new_node;
}
* registers... */
ir_graph *irg = current_ir_graph;
ir_node *stack = get_irg_frame(irg);
- ir_node *nomem = new_NoMem();
+ ir_node *nomem = get_irg_no_mem(irg);
ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
NULL, 0, 0, true);
ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
set_irn_pinned(ldf, op_pin_state_floats);
- return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
+ return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
}
static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
{
ir_graph *irg = current_ir_graph;
ir_node *stack = get_irg_frame(irg);
- ir_node *nomem = new_NoMem();
+ ir_node *nomem = get_irg_no_mem(irg);
ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
NULL, 0, 0, true);
ir_node *ldf;
ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
set_irn_pinned(ldf, op_pin_state_floats);
- return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
+ return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
}
static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
{
ir_graph *irg = current_ir_graph;
ir_node *stack = get_irg_frame(irg);
- ir_node *nomem = new_NoMem();
+ ir_node *nomem = get_irg_no_mem(irg);
ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
NULL, 0, 0, true);
ir_node *ldr;
ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
set_irn_pinned(ldr, op_pin_state_floats);
- return new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
+ return new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
}
static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
{
ir_graph *irg = current_ir_graph;
ir_node *stack = get_irg_frame(irg);
- ir_node *nomem = new_NoMem();
+ ir_node *nomem = get_irg_no_mem(irg);
ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
NULL, 0, 0, true);
ir_node *ldr0, *ldr1;
ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
set_irn_pinned(ldr1, op_pin_state_floats);
- *out_value0 = new_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
- *out_value1 = new_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
+ *out_value0 = new_r_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
+ *out_value1 = new_r_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
}
static ir_node *gen_CopyB(ir_node *node)
ir_node *src_copy;
ir_node *dst_copy;
- src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
- dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
+ src_copy = be_new_Copy(block, new_src);
+ dst_copy = be_new_Copy(block, new_dst);
return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
new_bd_arm_EmptyReg(dbg, block),
case ir_bk_inner_trampoline:
break;
}
- panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
+ panic("Builtin %s not implemented", get_builtin_kind_name(kind));
}
/**
case ir_bk_parity:
case ir_bk_popcount:
case ir_bk_bswap:
- assert(get_Proj_proj(proj) == pn_Builtin_1_result);
+ assert(get_Proj_proj(proj) == pn_Builtin_max+1);
return new_node;
case ir_bk_trap:
case ir_bk_debugbreak:
case ir_bk_inner_trampoline:
break;
}
- panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
+ panic("Builtin %s not implemented", get_builtin_kind_name(kind));
}
static ir_node *gen_Proj_Load(ir_node *node)
panic("Unsupported Proj from CopyB");
}
-static ir_node *gen_Proj_Quot(ir_node *node)
+static ir_node *gen_Proj_Div(ir_node *node)
{
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);
long proj = get_Proj_proj(node);
switch (proj) {
- case pn_Quot_M:
- if (is_arm_Dvf(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
- }
- break;
- case pn_Quot_res:
- if (is_arm_Dvf(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
- }
- break;
+ case pn_Div_M:
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
+ case pn_Div_res:
+ return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
default:
break;
}
- panic("Unsupported Proj from Quot");
-}
-
-/**
- * Transform the Projs from a Cmp.
- */
-static ir_node *gen_Proj_Cmp(ir_node *node)
-{
- (void) node;
- /* we should only be here in case of a Mux node */
- panic("Mux NYI");
+ panic("Unsupported Proj from Div");
}
static ir_node *gen_Proj_Start(ir_node *node)
{
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
- ir_node *barrier = be_transform_node(get_Proj_pred(node));
long proj = get_Proj_proj(node);
switch ((pn_Start) proj) {
return new_bd_arm_Jmp(NULL, new_block);
case pn_Start_M:
- return new_r_Proj(barrier, mode_M, 0);
+ return be_prolog_get_memory(abihelper);
case pn_Start_T_args:
- return barrier;
+ return new_r_Bad(get_irn_irg(block), mode_T);
case pn_Start_P_frame_base:
return be_prolog_get_reg_value(abihelper, sp_reg);
-
- case pn_Start_P_tls:
- return new_Bad();
-
- case pn_Start_max:
- break;
}
panic("unexpected start proj: %ld\n", proj);
}
ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
mode_gp, param->entity,
0, 0, true);
- value1 = new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
+ value1 = new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
}
/* convert integer value to float */
*/
static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
{
- int n_outs = arch_irn_get_n_outs(node);
+ int n_outs = arch_get_irn_n_outs(node);
int o;
for (o = 0; o < n_outs; ++o) {
- const arch_register_req_t *req = arch_get_out_register_req(node, o);
+ const arch_register_req_t *req = arch_get_irn_register_req_out(node, o);
if (req == reg->single_req)
return o;
}
ir_node *call = get_Proj_pred(get_Proj_pred(node));
ir_node *new_call = be_transform_node(call);
ir_type *function_type = get_Call_type(call);
- calling_convention_t *cconv = arm_decide_calling_convention(function_type);
+ calling_convention_t *cconv
+ = arm_decide_calling_convention(NULL, function_type);
const reg_or_stackslot_t *res = &cconv->results[pn];
ir_mode *mode;
int regn;
case pn_Call_X_regular:
case pn_Call_X_except:
case pn_Call_T_result:
- case pn_Call_P_value_res_base:
- case pn_Call_max:
break;
}
panic("Unexpected Call proj %ld\n", pn);
return gen_Proj_Call(node);
case iro_CopyB:
return gen_Proj_CopyB(node);
- case iro_Quot:
- return gen_Proj_Quot(node);
- case iro_Cmp:
- return gen_Proj_Cmp(node);
+ case iro_Div:
+ return gen_Proj_Div(node);
case iro_Start:
return gen_Proj_Start(node);
case iro_Cond:
+ case iro_Switch:
/* nothing to do */
return be_duplicate_node(node);
case iro_Proj: {
typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
-static inline ir_node *create_const(ir_node **place,
+static inline ir_node *create_const(ir_graph *irg, ir_node **place,
create_const_node_func func,
const arch_register_t* reg)
{
if (*place != NULL)
return *place;
- block = get_irg_start_block(env_cg->irg);
+ block = get_irg_start_block(irg);
res = func(NULL, block);
arch_set_irn_register(res, reg);
*place = res;
/* just produce a 0 */
ir_mode *mode = get_irn_mode(node);
if (mode_is_float(mode)) {
- tarval *tv = get_mode_null(mode);
- ir_node *node = new_bd_arm_fConst(dbgi, new_block, tv);
- be_dep_on_frame(node);
- return node;
+ ir_tarval *tv = get_mode_null(mode);
+ ir_node *fconst = new_bd_arm_fConst(dbgi, new_block, tv);
+ return fconst;
} else if (mode_needs_gp_reg(mode)) {
return create_const_graph_value(dbgi, new_block, 0);
}
layout->frame_type = get_irg_frame_type(irg);
layout->between_type = arm_get_between_type();
layout->arg_type = arg_type;
- layout->param_map = NULL; /* TODO */
layout->initial_offset = 0;
layout->initial_bias = 0;
- layout->stack_dir = -1;
layout->sp_relative = true;
assert(N_FRAME_TYPES == 3);
}
/**
- * transform the start node to the prolog code + initial barrier
+ * transform the start node to the prolog code
*/
static ir_node *gen_Start(ir_node *node)
{
ir_node *new_block = be_transform_node(block);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *start;
- ir_node *incsp;
- ir_node *sp;
- ir_node *barrier;
- int i;
+ size_t i;
/* stackpointer is important at function prolog */
be_prolog_add_reg(abihelper, sp_reg,
for (i = 0; i < get_method_n_params(function_type); ++i) {
const reg_or_stackslot_t *param = &cconv->parameters[i];
if (param->reg0 != NULL)
- be_prolog_add_reg(abihelper, param->reg0, 0);
+ be_prolog_add_reg(abihelper, param->reg0, arch_register_req_type_none);
if (param->reg1 != NULL)
- be_prolog_add_reg(abihelper, param->reg1, 0);
+ be_prolog_add_reg(abihelper, param->reg1, arch_register_req_type_none);
}
/* announce that we need the values of the callee save regs */
- for (i = 0; i < (int) (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
- be_prolog_add_reg(abihelper, callee_saves[i], 0);
+ for (i = 0; i != ARRAY_SIZE(callee_saves); ++i) {
+ be_prolog_add_reg(abihelper, callee_saves[i], arch_register_req_type_none);
}
start = be_prolog_create_start(abihelper, dbgi, new_block);
- sp = be_prolog_get_reg_value(abihelper, sp_reg);
- incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
- be_prolog_set_reg_value(abihelper, sp_reg, incsp);
- barrier = be_prolog_create_barrier(abihelper, new_block);
-
- return barrier;
+ return start;
}
static ir_node *get_stack_pointer_for(ir_node *node)
{
/* get predecessor in stack_order list */
- ir_node *stack_pred = be_get_stack_pred(abihelper, node);
- ir_node *stack_pred_transformed;
+ ir_node *stack_pred = be_get_stack_pred(stackorder, node);
ir_node *stack;
if (stack_pred == NULL) {
return sp_proj;
}
- stack_pred_transformed = be_transform_node(stack_pred);
- stack = pmap_get(node_to_stack, stack_pred);
+ be_transform_node(stack_pred);
+ stack = pmap_get(ir_node, node_to_stack, stack_pred);
if (stack == NULL) {
return get_stack_pointer_for(stack_pred);
}
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *mem = get_Return_mem(node);
ir_node *new_mem = be_transform_node(mem);
- int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
+ size_t n_callee_saves = ARRAY_SIZE(callee_saves);
ir_node *sp_proj = get_stack_pointer_for(node);
- int n_res = get_Return_n_ress(node);
+ size_t n_res = get_Return_n_ress(node);
ir_node *bereturn;
- ir_node *incsp;
- int i;
+ size_t i;
be_epilog_begin(abihelper);
be_epilog_set_memory(abihelper, new_mem);
const reg_or_stackslot_t *slot = &cconv->results[i];
const arch_register_t *reg = slot->reg0;
assert(slot->reg1 == NULL);
- be_epilog_add_reg(abihelper, reg, 0, new_res_value);
+ be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, new_res_value);
}
/* connect callee saves with their values at the function begin */
for (i = 0; i < n_callee_saves; ++i) {
const arch_register_t *reg = callee_saves[i];
ir_node *value = be_prolog_get_reg_value(abihelper, reg);
- be_epilog_add_reg(abihelper, reg, 0, value);
+ be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, value);
}
- /* create the barrier before the epilog code */
- be_epilog_create_barrier(abihelper, new_block);
-
/* epilog code: an incsp */
- sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
- incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
- BE_STACK_FRAME_SIZE_SHRINK, 0);
- be_epilog_set_reg_value(abihelper, sp_reg, incsp);
-
bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
-
return bereturn;
}
ir_node *new_mem = be_transform_node(mem);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_type *type = get_Call_type(node);
- calling_convention_t *cconv = arm_decide_calling_convention(type);
- int n_params = get_Call_n_params(node);
- int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
+ calling_convention_t *cconv = arm_decide_calling_convention(NULL, type);
+ size_t n_params = get_Call_n_params(node);
+ size_t const n_param_regs = cconv->n_reg_params;
/* max inputs: memory, callee, register arguments */
- int max_inputs = 2 + n_param_regs;
+ size_t const max_inputs = 2 + n_param_regs;
ir_node **in = ALLOCAN(ir_node*, max_inputs);
ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
struct obstack *obst = be_get_be_obst(irg);
const arch_register_req_t **in_req
= OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
- int in_arity = 0;
- int sync_arity = 0;
- int n_caller_saves
- = sizeof(caller_saves)/sizeof(caller_saves[0]);
- ir_entity *entity = NULL;
- ir_node *incsp = NULL;
+ size_t in_arity = 0;
+ size_t sync_arity = 0;
+ size_t const n_caller_saves = ARRAY_SIZE(caller_saves);
+ ir_entity *entity = NULL;
+ ir_node *incsp = NULL;
int mem_pos;
ir_node *res;
- int p;
- int o;
- int out_arity;
+ size_t p;
+ size_t o;
+ size_t out_arity;
assert(n_params == get_method_n_params(type));
pmap_insert(node_to_stack, node, incsp);
}
- set_arm_in_req_all(res, in_req);
+ arch_set_irn_register_reqs_in(res, in_req);
/* create output register reqs */
- arch_set_out_register_req(res, 0, arch_no_register_req);
+ arch_set_irn_register_req_out(res, 0, arch_no_register_req);
for (o = 0; o < n_caller_saves; ++o) {
const arch_register_t *reg = caller_saves[o];
- arch_set_out_register_req(res, o+1, reg->single_req);
+ arch_set_irn_register_req_out(res, o+1, reg->single_req);
}
/* copy pinned attribute */
/* must be the frame pointer all other sels must have been lowered
* already */
assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
- /* we should not have value types from parameters anymore - they should be
- lowered */
- assert(get_entity_owner(entity) !=
- get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
}
-/**
- * Change some phi modes
- */
static ir_node *gen_Phi(ir_node *node)
{
+ ir_mode *mode = get_irn_mode(node);
const arch_register_req_t *req;
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *mode = get_irn_mode(node);
- ir_node *phi;
-
if (mode_needs_gp_reg(mode)) {
/* we shouldn't have any 64bit stuff around anymore */
assert(get_mode_size_bits(mode) <= 32);
req = arch_no_register_req;
}
- /* phi nodes allow loops, so we use the old arguments for now
- * and fix this later */
- phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
- get_irn_in(node) + 1);
- copy_node_attr(irg, node, phi);
- be_duplicate_deps(node, phi);
-
- arch_set_out_register_req(phi, 0, req);
-
- be_enqueue_preds(node);
-
- return phi;
+ return be_transform_phi(node, req);
}
-
/**
* Enters all transform functions into the generic pointer
*/
be_set_transform_function(op_Const, gen_Const);
be_set_transform_function(op_Conv, gen_Conv);
be_set_transform_function(op_CopyB, gen_CopyB);
+ be_set_transform_function(op_Div, gen_Div);
be_set_transform_function(op_Eor, gen_Eor);
be_set_transform_function(op_Jmp, gen_Jmp);
be_set_transform_function(op_Load, gen_Load);
be_set_transform_function(op_Or, gen_Or);
be_set_transform_function(op_Phi, gen_Phi);
be_set_transform_function(op_Proj, gen_Proj);
- be_set_transform_function(op_Quot, gen_Quot);
be_set_transform_function(op_Return, gen_Return);
be_set_transform_function(op_Rotl, gen_Rotl);
be_set_transform_function(op_Sel, gen_Sel);
be_set_transform_function(op_Start, gen_Start);
be_set_transform_function(op_Store, gen_Store);
be_set_transform_function(op_Sub, gen_Sub);
+ be_set_transform_function(op_Switch, gen_Switch);
be_set_transform_function(op_SymConst, gen_SymConst);
be_set_transform_function(op_Unknown, gen_Unknown);
be_set_transform_function(op_Builtin, gen_Builtin);
static void arm_init_fpa_immediate(void)
{
/* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
- fpa_imm[0][fpa_null] = get_mode_null(mode_F);
- fpa_imm[0][fpa_one] = get_mode_one(mode_F);
- fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
- fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
- fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
- fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
- fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
- fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
-
- fpa_imm[1][fpa_null] = get_mode_null(mode_D);
- fpa_imm[1][fpa_one] = get_mode_one(mode_D);
- fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
- fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
- fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
- fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
- fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
- fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
-
- fpa_imm[2][fpa_null] = get_mode_null(mode_E);
- fpa_imm[2][fpa_one] = get_mode_one(mode_E);
- fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
- fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
- fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
- fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
- fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
- fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
+ fpa_imm[FPA_IMM_FLOAT][fpa_null] = get_mode_null(mode_F);
+ fpa_imm[FPA_IMM_FLOAT][fpa_one] = get_mode_one(mode_F);
+ fpa_imm[FPA_IMM_FLOAT][fpa_two] = new_tarval_from_str("2", 1, mode_F);
+ fpa_imm[FPA_IMM_FLOAT][fpa_three] = new_tarval_from_str("3", 1, mode_F);
+ fpa_imm[FPA_IMM_FLOAT][fpa_four] = new_tarval_from_str("4", 1, mode_F);
+ fpa_imm[FPA_IMM_FLOAT][fpa_five] = new_tarval_from_str("5", 1, mode_F);
+ fpa_imm[FPA_IMM_FLOAT][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
+ fpa_imm[FPA_IMM_FLOAT][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
+
+ fpa_imm[FPA_IMM_DOUBLE][fpa_null] = get_mode_null(mode_D);
+ fpa_imm[FPA_IMM_DOUBLE][fpa_one] = get_mode_one(mode_D);
+ fpa_imm[FPA_IMM_DOUBLE][fpa_two] = new_tarval_from_str("2", 1, mode_D);
+ fpa_imm[FPA_IMM_DOUBLE][fpa_three] = new_tarval_from_str("3", 1, mode_D);
+ fpa_imm[FPA_IMM_DOUBLE][fpa_four] = new_tarval_from_str("4", 1, mode_D);
+ fpa_imm[FPA_IMM_DOUBLE][fpa_five] = new_tarval_from_str("5", 1, mode_D);
+ fpa_imm[FPA_IMM_DOUBLE][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
+ fpa_imm[FPA_IMM_DOUBLE][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
}
/**
* Transform a Firm graph into an ARM graph.
*/
-void arm_transform_graph(arm_code_gen_t *cg)
+void arm_transform_graph(ir_graph *irg)
{
static int imm_initialized = 0;
- ir_graph *irg = cg->irg;
ir_entity *entity = get_irg_entity(irg);
+ const arch_env_t *arch_env = be_get_irg_arch_env(irg);
ir_type *frame_type;
mode_gp = mode_Iu;
- mode_fp = mode_E;
+ mode_fp = mode_F;
if (! imm_initialized) {
arm_init_fpa_immediate();
imm_initialized = 1;
}
arm_register_transformers();
- env_cg = cg;
+
+ isa = (arm_isa_t*) arch_env;
node_to_stack = pmap_create();
assert(abihelper == NULL);
abihelper = be_abihelper_prepare(irg);
- be_collect_stacknodes(abihelper);
+ stackorder = be_collect_stacknodes(irg);
assert(cconv == NULL);
- cconv = arm_decide_calling_convention(get_entity_type(entity));
+ cconv = arm_decide_calling_convention(irg, get_entity_type(entity));
create_stacklayout(irg);
- be_transform_graph(cg->irg, NULL);
+ be_transform_graph(irg, NULL);
be_abihelper_finish(abihelper);
abihelper = NULL;
+ be_free_stackorder(stackorder);
+ stackorder = NULL;
arm_free_calling_convention(cconv);
cconv = NULL;
projects / libfirm / blobdiff