-/* The codegenrator (transform FIRM into arm FIRM */
-/* $Id$ */
+/*
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
-#ifdef HAVE_CONFIG_H
+/**
+ * @file
+ * @brief The codegenerator (transform FIRM into arm FIRM)
+ * @author Oliver Richter, Tobias Gneist, Michael Beck
+ * @version $Id$
+ */
#include "config.h"
-#endif
#include "irnode_t.h"
#include "irgraph_t.h"
#include "dbginfo.h"
#include "iropt_t.h"
#include "debug.h"
+#include "error.h"
-#include "../benode_t.h"
+#include "../benode.h"
+#include "../beirg.h"
+#include "../beutil.h"
+#include "../betranshlp.h"
#include "bearch_arm_t.h"
#include "arm_nodes_attr.h"
-#include "../arch/archop.h" /* we need this for Min and Max nodes */
#include "arm_transform.h"
+#include "arm_optimize.h"
#include "arm_new_nodes.h"
#include "arm_map_regs.h"
#include <limits.h>
+DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-extern ir_op *get_op_Mulh(void);
-
+/** hold the current code generator during transformation */
+static arm_code_gen_t *env_cg;
-
-/****************************************************************************************************
- * _ _ __ _ _
- * | | | | / _| | | (_)
- * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
- * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
- * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
- * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
- *
- ****************************************************************************************************/
-
-typedef struct vals_ {
- int ops;
- unsigned char values[4];
- unsigned char shifts[4];
-} vals;
-
-/** Execute ROL. */
-static unsigned do_rol(unsigned v, unsigned rol) {
- return (v << rol) | (v >> (32 - rol));
+static inline int mode_needs_gp_reg(ir_mode *mode)
+{
+ return mode_is_int(mode) || mode_is_reference(mode);
}
/**
- * construct 8bit values und rot amounts for a value
+ * Creates a possible DAG for an constant.
*/
-static void gen_vals_from_word(unsigned int value, vals *result)
+static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
+ unsigned int value)
{
- int initial = 0;
+ ir_node *result;
+ arm_vals v, vn;
+ int cnt;
- memset(result, 0, sizeof(*result));
+ arm_gen_vals_from_word(value, &v);
+ arm_gen_vals_from_word(~value, &vn);
- /* special case: we prefer shift amount 0 */
- if (value < 0x100) {
- result->values[0] = value;
- result->ops = 1;
- return;
- }
-
- while (value != 0) {
- if (value & 0xFF) {
- unsigned v = do_rol(value, 8) & 0xFFFFFF;
- int shf = 0;
- for (;;) {
- if ((v & 3) != 0)
- break;
- shf += 2;
- v >>= 2;
- }
- v &= 0xFF;
- shf = (initial + shf - 8) & 0x1F;
- result->values[result->ops] = v;
- result->shifts[result->ops] = shf;
- ++result->ops;
+ if (vn.ops < v.ops) {
+ /* remove bits */
+ result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
+ be_dep_on_frame(result);
- value ^= do_rol(v, shf) >> initial;
+ for (cnt = 1; cnt < vn.ops; ++cnt) {
+ result = new_bd_arm_Bic_imm(dbgi, block, result,
+ vn.values[cnt], vn.rors[cnt]);
}
- else {
- value >>= 8;
- initial += 8;
+ } else {
+ /* add bits */
+ result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
+ be_dep_on_frame(result);
+
+ for (cnt = 1; cnt < v.ops; ++cnt) {
+ result = new_bd_arm_Or_imm(dbgi, block, result,
+ v.values[cnt], v.rors[cnt]);
}
}
+ return result;
}
/**
- * Creates a arm_Const node.
+ * Create a DAG constructing a given Const.
+ *
+ * @param irn a Firm const
*/
-static ir_node *create_const_node(ir_node *irn, ir_node *block, long value) {
- tarval *tv = new_tarval_from_long(value, mode_Iu);
- dbg_info *dbg = get_irn_dbg_info(irn);
- return new_rd_arm_Mov_i(dbg, current_ir_graph, block, get_irn_mode(irn), tv);
+static ir_node *create_const_graph(ir_node *irn, ir_node *block)
+{
+ tarval *tv = get_Const_tarval(irn);
+ ir_mode *mode = get_tarval_mode(tv);
+ unsigned value;
+
+ if (mode_is_reference(mode)) {
+ /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
+ assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
+ tv = tarval_convert_to(tv, mode_Iu);
+ }
+ value = get_tarval_long(tv);
+ return create_const_graph_value(get_irn_dbg_info(irn), block, value);
}
/**
- * Creates a arm_Const_Neg node.
+ * Create an And that will zero out upper bits.
+ *
+ * @param dbgi debug info
+ * @param block the basic block
+ * @param op the original node
+ * param src_bits number of lower bits that will remain
*/
-static ir_node *create_const_neg_node(ir_node *irn, ir_node *block, long value) {
- tarval *tv = new_tarval_from_long(value, mode_Iu);
- dbg_info *dbg = get_irn_dbg_info(irn);
- return new_rd_arm_Mvn_i(dbg, current_ir_graph, block, get_irn_mode(irn), tv);
+static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
+ int src_bits)
+{
+ if (src_bits == 8) {
+ return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
+ } else if (src_bits == 16) {
+ ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
+ ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
+ return rshift;
+ } else {
+ panic("zero extension only supported for 8 and 16 bits");
+ }
}
-#define NEW_BINOP_NODE(opname, env, op1, op2) new_rd_arm_##opname(env->dbg, current_ir_graph, env->block, op1, op2, env->mode)
-
/**
- * Encodes an immediate with shifter operand
+ * Generate code for a sign extension.
*/
-static unsigned int arm_encode_imm_w_shift(unsigned int shift, unsigned int immediate) {
- return immediate | ((shift>>1)<<8);
+static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
+ int src_bits)
+{
+ int shift_width = 32 - src_bits;
+ ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
+ ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
+ return rshift_node;
}
-/**
- * Decode an immediate with shifter operand
- */
-unsigned int arm_decode_imm_w_shift(tarval *tv) {
- unsigned l = get_tarval_long(tv);
- unsigned rol = (l & ~0xFF) >> 7;
+static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
+ ir_mode *orig_mode)
+{
+ int bits = get_mode_size_bits(orig_mode);
+ if (bits == 32)
+ return op;
- return do_rol(l & 0xFF, rol);
+ if (mode_is_signed(orig_mode)) {
+ return gen_sign_extension(dbgi, block, op, bits);
+ } else {
+ return gen_zero_extension(dbgi, block, op, bits);
+ }
}
/**
- * Creates a possible DAG for an constant.
+ * returns true if it is assured, that the upper bits of a node are "clean"
+ * which means for a 16 or 8 bit value, that the upper bits in the register
+ * are 0 for unsigned and a copy of the last significant bit for signed
+ * numbers.
*/
-static ir_node *create_const_graph_value(ir_node *irn, ir_node *block, unsigned int value) {
- ir_node *result;
- int negate = 0;
- vals v, vn;
- int cnt;
- ir_mode *mode = get_irn_mode(irn);
- dbg_info *dbg = get_irn_dbg_info(irn);
+static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
+{
+ (void) transformed_node;
+ (void) mode;
+ /* TODO */
+ return false;
+}
- gen_vals_from_word(value, &v);
- gen_vals_from_word(~value, &vn);
+/**
+ * Transforms a Conv node.
+ *
+ * @return The created ia32 Conv node
+ */
+static ir_node *gen_Conv(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *op = get_Conv_op(node);
+ ir_node *new_op = be_transform_node(op);
+ ir_mode *src_mode = get_irn_mode(op);
+ ir_mode *dst_mode = get_irn_mode(node);
+ dbg_info *dbg = get_irn_dbg_info(node);
+
+ if (src_mode == dst_mode)
+ return new_op;
+
+ if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
+ env_cg->have_fp_insn = 1;
+
+ if (USE_FPA(env_cg->isa)) {
+ if (mode_is_float(src_mode)) {
+ if (mode_is_float(dst_mode)) {
+ /* from float to float */
+ return new_bd_arm_fpaMvf(dbg, block, new_op, dst_mode);
+ }
+ else {
+ /* from float to int */
+ return new_bd_arm_fpaFix(dbg, block, new_op, dst_mode);
+ }
+ }
+ else {
+ /* from int to float */
+ return new_bd_arm_fpaFlt(dbg, block, new_op, dst_mode);
+ }
+ } else if (USE_VFP(env_cg->isa)) {
+ panic("VFP not supported yet");
+ } else {
+ panic("Softfloat not supported yet");
+ }
+ } else { /* complete in gp registers */
+ int src_bits = get_mode_size_bits(src_mode);
+ int dst_bits = get_mode_size_bits(dst_mode);
+ int min_bits;
+ ir_mode *min_mode;
+
+ if (src_bits == dst_bits) {
+ /* kill unneccessary conv */
+ return new_op;
+ }
- if (vn.ops < v.ops) {
- /* remove bits */
- result = create_const_neg_node(irn, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0]));
+ if (src_bits < dst_bits) {
+ min_bits = src_bits;
+ min_mode = src_mode;
+ } else {
+ min_bits = dst_bits;
+ min_mode = dst_mode;
+ }
- for (cnt = 1; cnt < vn.ops; ++cnt) {
- tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]), mode_Iu);
- ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, tv);
- result = bic_i_node;
+ if (upper_bits_clean(new_op, min_mode)) {
+ return new_op;
}
- }
- else {
- /* add bits */
- result = create_const_node(irn, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0]));
- for (cnt = 1; cnt < v.ops; ++cnt) {
- tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]), mode_Iu);
- ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, tv);
- result = orr_i_node;
+ if (mode_is_signed(min_mode)) {
+ return gen_sign_extension(dbg, block, new_op, min_bits);
+ } else {
+ return gen_zero_extension(dbg, block, new_op, min_bits);
}
}
- return result;
}
-/**
- * Create a DAG constructing a given Const.
- *
- * @param irn a Firm const
- */
-static ir_node *create_const_graph(ir_node *irn, ir_node *block) {
- int value = get_tarval_long(get_Const_tarval(irn));
- return create_const_graph_value(irn, block, value);
-}
+typedef struct {
+ unsigned char imm_8;
+ unsigned char rot;
+} arm_immediate_t;
+static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
+{
+ unsigned val, low_pos, high_pos;
+ if (!is_Const(node))
+ return false;
-static ir_node *gen_Const(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *result;
- ir_graph *irg = current_ir_graph;
- ir_node *block = get_nodes_block(irn);
- ir_mode *mode = get_irn_mode(irn);
- dbg_info *dbg = get_irn_dbg_info(irn);
+ val = get_tarval_long(get_Const_tarval(node));
- assert(mode != mode_E && "IEEE Extended FP not supported");
- if (mode == mode_F)
- result = new_rd_arm_fConst(dbg, irg, block, mode, get_Const_tarval(irn));
- else if (mode == mode_D)
- result = new_rd_arm_fConst(dbg, irg, block, mode, get_Const_tarval(irn));
- else if (mode == mode_P)
- return irn;
- else
- result = create_const_graph(irn, block);
- return result;
-}
+ if (val == 0) {
+ res->imm_8 = 0;
+ res->rot = 0;
+ return true;
+ }
+ if (val <= 0xff) {
+ res->imm_8 = val;
+ res->rot = 0;
+ return true;
+ }
+ /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
+ (= 0, 2, 4, 6, ...).
+ So we determine the smallest even position with a bit set
+ and the highest even position with no bit set anymore.
+ If the difference between these 2 is <= 8, then we can encode the value
+ as immediate.
+ */
+ low_pos = ntz(val) & ~1u;
+ high_pos = (32-nlz(val)+1) & ~1u;
+
+ if (high_pos - low_pos <= 8) {
+ res->imm_8 = val >> low_pos;
+ res->rot = 32 - low_pos;
+ return true;
+ }
-static ir_node *gen_mask(ir_node *irn, ir_node *op, int result_bits) {
- ir_node *block = get_nodes_block(irn);
- unsigned mask_bits = (1 << result_bits) - 1;
- ir_node *mask_node = create_const_graph_value(irn, block, mask_bits);
- dbg_info *dbg = get_irn_dbg_info(irn);
- return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, get_irn_mode(irn), ARM_SHF_NONE, NULL);
-}
+ if (high_pos > 24) {
+ res->rot = 34 - high_pos;
+ val = val >> (32-res->rot) | val << (res->rot);
+ if (val <= 0xff) {
+ res->imm_8 = val;
+ return true;
+ }
+ }
-static ir_node *gen_sign_extension(ir_node *irn, ir_node *op, int result_bits) {
- ir_node *block = get_nodes_block(irn);
- int shift_width = 32 - result_bits;
- ir_graph *irg = current_ir_graph;
- ir_node *shift_const_node = create_const_graph_value(irn, block, shift_width);
- dbg_info *dbg = get_irn_dbg_info(irn);
- ir_node *lshift_node = new_rd_arm_Shl(dbg, irg, block, op, shift_const_node, get_irn_mode(op));
- ir_node *rshift_node = new_rd_arm_Shrs(dbg, irg, block, lshift_node, shift_const_node, get_irn_mode(irn));
- return rshift_node;
+ return false;
}
-/**
- * Transforms a Conv node.
- *
- * @param env The transformation environment
- * @return the created arm Conv node
- */
-static ir_node *gen_Conv(ir_node *irn, arm_code_gen_t *cg) {
- ir_graph *irg = current_ir_graph;
- ir_node *block = get_nodes_block(irn);
- ir_node *op = get_Conv_op(irn);
- ir_mode *in_mode = get_irn_mode(op);
- ir_mode *out_mode = get_irn_mode(irn);
- dbg_info *dbg = get_irn_dbg_info(irn);
-
- assert( in_mode != mode_E && "");
- assert( in_mode != mode_Ls && "");
- assert( in_mode != mode_Lu && "");
- assert( out_mode != mode_E && "");
- assert( out_mode != mode_Ls && "");
- assert( out_mode != mode_Lu && "");
-
- if (in_mode == out_mode)
- return op;
+static int is_downconv(const ir_node *node)
+{
+ ir_mode *src_mode;
+ ir_mode *dest_mode;
- if ((mode_is_int(in_mode) || mode_is_reference(in_mode))
- && (mode_is_reference(out_mode) || mode_is_int(out_mode))) {
- int in_bits = get_mode_size_bits(in_mode);
- int out_bits = get_mode_size_bits(out_mode);
- int in_sign = get_mode_sign(in_mode);
- int out_sign = get_mode_sign(out_mode);
-
- // 32 -> 32
- // NOPpen
- if (in_bits == out_bits && in_bits == 32)
- return op;
-
- // 16 -> 16
- // unsigned -> unsigned
- // NOP
- // unsigned -> signed
- // sign extension (31:16)=(15)
- // signed -> unsigned
- // maskieren (31:16)=0
- // signed -> signed
- // NOP
- if (in_bits == out_bits && out_bits < 32) {
- if (in_sign && !out_sign) {
- return gen_mask(irn, op, out_bits);
- } else {
- return gen_sign_extension(irn, op, out_bits);
- }
- }
+ if (!is_Conv(node))
+ return 0;
- // 16 -> 32
- // unsigned -> unsigned
- // NOP
- // unsigned -> signed
- // NOP
- // signed -> unsigned
- // sign extension (31:16)=(15)
- // signed -> signed
- // sign extension (31:16)=(15)
- if (in_bits < out_bits) {
- if (in_sign) {
- return gen_sign_extension(irn, op, out_bits);
- } else {
- return op;
- }
- }
+ /* we only want to skip the conv when we're the only user
+ * (not optimal but for now...)
+ */
+ if (get_irn_n_edges(node) > 1)
+ return 0;
- // 32 -> 16
- // unsigned -> unsigned
- // maskieren (31:16)=0
- // unsigned -> signed
- // maskieren (31:16)=0
- // signed -> unsigned
- // maskieren (31:16)=0
- // signed -> signed
- // sign extension (erledigt auch maskieren) (31:16)=(15)
- if (in_bits > out_bits) {
- if (in_sign && out_sign) {
- return gen_sign_extension(irn, op, out_bits);
- } else {
- return gen_mask(irn, op, out_bits);
- }
- }
- assert(0 && "recheck integer conversion logic!");
- return irn;
- } else if (in_mode == mode_D && out_mode == mode_F) {
- return new_rd_arm_fConvD2S(dbg, irg, block, op, out_mode);
- } else if (in_mode == mode_F && out_mode == mode_D) {
- return new_rd_arm_fConvS2D(dbg, irg, block, op, out_mode);
- } else if (mode_is_int(in_mode) && mode_is_float(out_mode)) {
- cg->have_fp = 1;
- return irn; /* TODO: implement int->float conversion*/
- } else if (mode_is_float(in_mode) && mode_is_int(out_mode)) {
- cg->have_fp = 1;
- return irn; /* TODO: implement float->int conversion*/
- } else {
- assert(0 && "not implemented conversion");
- return irn;
- }
+ src_mode = get_irn_mode(get_Conv_op(node));
+ dest_mode = get_irn_mode(node);
+ return
+ mode_needs_gp_reg(src_mode) &&
+ mode_needs_gp_reg(dest_mode) &&
+ get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
}
-/**
- * Return true if an operand is a shifter operand
- */
-static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) {
- arm_shift_modifier mod = ARM_SHF_NONE;
+static ir_node *arm_skip_downconv(ir_node *node)
+{
+ while (is_downconv(node))
+ node = get_Conv_op(node);
+ return node;
+}
+
+typedef enum {
+ MATCH_NONE = 0,
+ MATCH_COMMUTATIVE = 1 << 0,
+ MATCH_SIZE_NEUTRAL = 1 << 1,
+} match_flags_t;
- if (is_arm_Mov(n))
- mod = get_arm_shift_modifier(n);
+typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
+typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
+
+static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
+ new_binop_reg_func new_reg, new_binop_imm_func new_imm)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *op1 = get_binop_left(node);
+ ir_node *new_op1;
+ ir_node *op2 = get_binop_right(node);
+ ir_node *new_op2;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ arm_immediate_t imm;
+
+ if (flags & MATCH_SIZE_NEUTRAL) {
+ op1 = arm_skip_downconv(op1);
+ op2 = arm_skip_downconv(op2);
+ } else {
+ assert(get_mode_size_bits(get_irn_mode(node)) == 32);
+ }
- *pmod = mod;
- if (mod != ARM_SHF_NONE) {
- long v = get_tarval_long(get_arm_value(n));
- if (v < 32)
- return (int)v;
+ if (try_encode_as_immediate(op2, &imm)) {
+ ir_node *new_op1 = be_transform_node(op1);
+ return new_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
+ }
+ new_op2 = be_transform_node(op2);
+ if ((flags & MATCH_COMMUTATIVE) && try_encode_as_immediate(op1, &imm)) {
+ return new_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
}
- return 0;
+ new_op1 = be_transform_node(op1);
+
+ return new_reg(dbgi, block, new_op1, new_op2);
}
/**
- * Creates an arm Add.
+ * Creates an ARM Add.
*
- * @param env The transformation environment
* @return the created arm Add node
*/
-static ir_node *gen_Add(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *block = get_nodes_block(irn);
- ir_node *op1 = get_Add_left(irn);
- ir_node *op2 = get_Add_right(irn);
- ir_mode *mode = get_irn_mode(irn);
- ir_graph *irg = current_ir_graph;
- ir_node *op3;
- int v;
- arm_shift_modifier mod;
- dbg_info *dbg = get_irn_dbg_info(irn);
-
- assert(mode != mode_E && "IEEE Extended FP not supported");
+static ir_node *gen_Add(ir_node *node)
+{
+ ir_mode *mode = get_irn_mode(node);
if (mode_is_float(mode)) {
- cg->have_fp = 1;
- return new_rd_arm_fAdd(dbg, irg, block, op1, op2, mode);
- }
- if (mode_is_numP(mode)) {
- if (is_arm_Mov_i(op1))
- return new_rd_arm_Add_i(dbg, irg, block, op2, mode, get_arm_value(op1));
- if (is_arm_Mov_i(op2))
- return new_rd_arm_Add_i(dbg, irg, block, op1, mode, get_arm_value(op2));
-
- /* check for MLA */
- if (is_arm_Mul(op1) && get_irn_n_edges(op1) == 1) {
- op3 = op2;
- op2 = get_irn_n(op1, 1);
- op1 = get_irn_n(op1, 0);
-
- return new_rd_arm_Mla(dbg, irg, block, op1, op2, op3, mode);
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *op1 = get_Add_left(node);
+ ir_node *op2 = get_Add_right(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_op1 = be_transform_node(op1);
+ ir_node *new_op2 = be_transform_node(op2);
+ env_cg->have_fp_insn = 1;
+ if (USE_FPA(env_cg->isa)) {
+#if 0
+ if (is_arm_fpaMvf_i(new_op1))
+ return new_bd_arm_fpaAdf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1));
+ if (is_arm_fpaMvf_i(new_op2))
+ return new_bd_arm_fpaAdf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2));
+#endif
+ return new_bd_arm_fpaAdf(dbgi, block, new_op1, new_op2, mode);
+ } else if (USE_VFP(env_cg->isa)) {
+ assert(mode != mode_E && "IEEE Extended FP not supported");
+ panic("VFP not supported yet");
}
- if (is_arm_Mul(op2) && get_irn_n_edges(op2) == 1) {
- op3 = op1;
- op1 = get_irn_n(op2, 0);
- op2 = get_irn_n(op2, 1);
-
- return new_rd_arm_Mla(dbg, irg, block, op1, op2, op3, mode);
+ else {
+ panic("Softfloat not supported yet");
}
+ } else {
+#if 0
+ /* check for MLA */
+ if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
+ new_op3 = new_op2;
+ new_op2 = get_irn_n(new_op1, 1);
+ new_op1 = get_irn_n(new_op1, 0);
- /* is the first a shifter */
- v = is_shifter_operand(op1, &mod);
- if (v) {
- op1 = get_irn_n(op1, 0);
- return new_rd_arm_Add(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu));
+ return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
}
- /* is the second a shifter */
- v = is_shifter_operand(op2, &mod);
- if (v) {
- op2 = get_irn_n(op2, 0);
- return new_rd_arm_Add(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu));
+ if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
+ new_op3 = new_op1;
+ new_op1 = get_irn_n(new_op2, 0);
+ new_op2 = get_irn_n(new_op2, 1);
+
+ return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
}
+#endif
- /* normal ADD */
- return new_rd_arm_Add(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL);
+ return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
+ new_bd_arm_Add_reg, new_bd_arm_Add_imm);
}
-
- assert(0 && "unknown mode for add");
- return NULL;
}
/**
- * Creates an arm Mul.
+ * Creates an ARM Mul.
*
- * @param env The transformation environment
* @return the created arm Mul node
*/
-static ir_node *gen_Mul(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *block = get_nodes_block(irn);
- ir_node *op1 = get_Mul_left(irn);
- ir_node *op2 = get_Mul_right(irn);
- ir_mode *mode = get_irn_mode(irn);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbg = get_irn_dbg_info(irn);
-
- assert(mode != mode_E && "IEEE Extended FP not supported");
+static ir_node *gen_Mul(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *op1 = get_Mul_left(node);
+ ir_node *new_op1 = be_transform_node(op1);
+ ir_node *op2 = get_Mul_right(node);
+ ir_node *new_op2 = be_transform_node(op2);
+ ir_mode *mode = get_irn_mode(node);
+ dbg_info *dbg = get_irn_dbg_info(node);
if (mode_is_float(mode)) {
- cg->have_fp = 1;
- return new_rd_arm_fMul(dbg, irg, block, op1, op2, mode);
+ env_cg->have_fp_insn = 1;
+ if (USE_FPA(env_cg->isa)) {
+#if 0
+ if (is_arm_Mov_i(new_op1))
+ return new_bd_arm_fpaMuf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
+ if (is_arm_Mov_i(new_op2))
+ return new_bd_arm_fpaMuf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
+#endif
+ return new_bd_arm_fpaMuf(dbg, block, new_op1, new_op2, mode);
+ }
+ else if (USE_VFP(env_cg->isa)) {
+ assert(mode != mode_E && "IEEE Extended FP not supported");
+ panic("VFP not supported yet");
+ }
+ else {
+ panic("Softfloat not supported yet");
+ }
}
- return new_rd_arm_Mul(dbg, irg, block, op1, op2, mode);
+ assert(mode_is_data(mode));
+ return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
}
/**
- * Creates an arm floating point Div.
+ * Creates an ARM floating point Div.
*
* @param env The transformation environment
* @return the created arm fDiv node
*/
-static ir_node *gen_Quot(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *block = get_nodes_block(irn);
- ir_node *op1 = get_Quot_left(irn);
- ir_node *op2 = get_Quot_right(irn);
- ir_mode *mode = get_irn_mode(irn);
- dbg_info *dbg = get_irn_dbg_info(irn);
+static ir_node *gen_Quot(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *op1 = get_Quot_left(node);
+ ir_node *new_op1 = be_transform_node(op1);
+ ir_node *op2 = get_Quot_right(node);
+ ir_node *new_op2 = be_transform_node(op2);
+ ir_mode *mode = get_irn_mode(node);
+ dbg_info *dbg = get_irn_dbg_info(node);
assert(mode != mode_E && "IEEE Extended FP not supported");
- return new_rd_arm_fDiv(dbg, current_ir_graph, block, op1, op2, mode);
-}
-
-#define GEN_INT_OP(op) \
-static ir_node *gen_ ## op(ir_node *irn, arm_code_gen_t *cg) { \
- ir_graph *irg = current_ir_graph; \
- ir_node *block = get_nodes_block(irn); \
- ir_node *op1 = get_ ## op ## _left(irn); \
- ir_node *op2 = get_ ## op ## _right(irn); \
- int v; \
- arm_shift_modifier mod; \
- ir_mode *mode = get_irn_mode(irn); \
- dbg_info *dbg = get_irn_dbg_info(irn); \
- \
- if (is_arm_Mov_i(op1)) \
- return new_rd_arm_ ## op ## _i(dbg, irg, block, op2, mode, get_arm_value(op1)); \
- if (is_arm_Mov_i(op2)) \
- return new_rd_arm_ ## op ## _i(dbg, irg, block, op1, mode, get_arm_value(op2)); \
- /* is the first a shifter */ \
- v = is_shifter_operand(op1, &mod); \
- if (v) { \
- op1 = get_irn_n(op1, 0); \
- return new_rd_arm_ ## op(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu)); \
- } \
- /* is the second a shifter */ \
- v = is_shifter_operand(op2, &mod); \
- if (v) { \
- op2 = get_irn_n(op2, 0); \
- return new_rd_arm_ ## op(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu)); \
- } \
- /* Normal op */ \
- return new_rd_arm_ ## op(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL); \
+ env_cg->have_fp_insn = 1;
+ if (USE_FPA(env_cg->isa)) {
+#if 0
+ if (is_arm_Mov_i(new_op1))
+ return new_bd_arm_fpaRdf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
+ if (is_arm_Mov_i(new_op2))
+ return new_bd_arm_fpaDvf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
+#endif
+ return new_bd_arm_fpaDvf(dbg, block, new_op1, new_op2, mode);
+ } else if (USE_VFP(env_cg->isa)) {
+ assert(mode != mode_E && "IEEE Extended FP not supported");
+ panic("VFP not supported yet");
+ }
+ else {
+ panic("Softfloat not supported yet");
+ }
}
-
/**
- * Creates an arm And.
+ * Creates an ARM And.
*
- * @param env The transformation environment
* @return the created arm And node
*/
-static ir_node *gen_And(ir_node *irn, arm_code_gen_t *cg);
-GEN_INT_OP(And)
+static ir_node *gen_And(ir_node *node)
+{
+ return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
+ new_bd_arm_And_reg, new_bd_arm_And_imm);
+}
/**
- * Creates an arm Orr.
+ * Creates an ARM Orr.
*
* @param env The transformation environment
* @return the created arm Or node
*/
-static ir_node *gen_Or(ir_node *irn, arm_code_gen_t *cg);
-GEN_INT_OP(Or)
+static ir_node *gen_Or(ir_node *node)
+{
+ return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
+ new_bd_arm_Or_reg, new_bd_arm_Or_imm);
+}
/**
- * Creates an arm Eor.
+ * Creates an ARM Eor.
*
- * @param env The transformation environment
* @return the created arm Eor node
*/
-static ir_node *gen_Eor(ir_node *irn, arm_code_gen_t *cg);
-GEN_INT_OP(Eor)
+static ir_node *gen_Eor(ir_node *node)
+{
+ return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
+ new_bd_arm_Eor_reg, new_bd_arm_Eor_imm);
+}
/**
- * Creates an arm Sub.
+ * Creates an ARM Sub.
*
- * @param env The transformation environment
* @return the created arm Sub node
*/
-static ir_node *gen_Sub(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *block = get_nodes_block(irn);
- ir_node *op1 = get_Sub_left(irn);
- ir_node *op2 = get_Sub_right(irn);
- int v;
- arm_shift_modifier mod;
- ir_mode *mode = get_irn_mode(irn);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbg = get_irn_dbg_info(irn);
-
- assert(mode != mode_E && "IEEE Extended FP not supported");
+static ir_node *gen_Sub(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *op1 = get_Sub_left(node);
+ ir_node *new_op1 = be_transform_node(op1);
+ ir_node *op2 = get_Sub_right(node);
+ ir_node *new_op2 = be_transform_node(op2);
+ ir_mode *mode = get_irn_mode(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
if (mode_is_float(mode)) {
- cg->have_fp = 1;
- return new_rd_arm_fSub(dbg, irg, block, op1, op2, mode);
- }
- if (mode_is_numP(mode)) {
- if (is_arm_Mov_i(op1))
- return new_rd_arm_Rsb_i(dbg, irg, block, op2, mode, get_arm_value(op1));
- if (is_arm_Mov_i(op2))
- return new_rd_arm_Sub_i(dbg, irg, block, op1, mode, get_arm_value(op2));
-
- /* is the first a shifter */
- v = is_shifter_operand(op1, &mod);
- if (v) {
- op1 = get_irn_n(op1, 0);
- return new_rd_arm_Rsb(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu));
- }
- /* is the second a shifter */
- v = is_shifter_operand(op2, &mod);
- if (v) {
- op2 = get_irn_n(op2, 0);
- return new_rd_arm_Sub(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu));
+ env_cg->have_fp_insn = 1;
+ if (USE_FPA(env_cg->isa)) {
+#if 0
+ if (is_arm_Mov_i(new_op1))
+ return new_bd_arm_fpaRsf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1));
+ if (is_arm_Mov_i(new_op2))
+ return new_bd_arm_fpaSuf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2));
+#endif
+ return new_bd_arm_fpaSuf(dbgi, block, new_op1, new_op2, mode);
+ } else if (USE_VFP(env_cg->isa)) {
+ assert(mode != mode_E && "IEEE Extended FP not supported");
+ panic("VFP not supported yet");
+ } else {
+ panic("Softfloat not supported yet");
}
- /* normal sub */
- return new_rd_arm_Sub(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL);
+ } else {
+ return gen_int_binop(node, MATCH_SIZE_NEUTRAL,
+ new_bd_arm_Sub_reg, new_bd_arm_Sub_imm);
}
- assert(0 && "unknown mode for sub");
- return NULL;
+}
+
+static ir_node *make_shift(ir_node *node, match_flags_t flags,
+ arm_shift_modifier shift_modifier)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *op1 = get_binop_left(node);
+ ir_node *op2 = get_binop_right(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_op1;
+ ir_node *new_op2;
+
+ if (flags & MATCH_SIZE_NEUTRAL) {
+ op1 = arm_skip_downconv(op1);
+ op2 = arm_skip_downconv(op2);
+ }
+ new_op1 = be_transform_node(op1);
+ new_op2 = be_transform_node(op2);
+ return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2, shift_modifier);
}
/**
- * Creates an arm Shl.
+ * Creates an ARM Shl.
*
- * @param env The transformation environment
- * @return the created arm Shl node
+ * @return the created ARM Shl node
*/
-static ir_node *gen_Shl(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *result;
- ir_node *block = get_nodes_block(irn);
- ir_node *op1 = get_Shl_left(irn);
- ir_node *op2 = get_Shl_right(irn);
- ir_mode *mode = get_irn_mode(irn);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbg = get_irn_dbg_info(irn);
-
- if (is_arm_Mov_i(op2)) {
- result = new_rd_arm_Mov(dbg, irg, block, op1, mode, ARM_SHF_LSL, get_arm_value(op2));
- } else {
- result = new_rd_arm_Shl(dbg, irg, block, op1, op2, mode);
- }
- return result;
+static ir_node *gen_Shl(ir_node *node)
+{
+ return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
}
/**
- * Creates an arm Shr.
+ * Creates an ARM Shr.
*
- * @param env The transformation environment
- * @return the created arm Shr node
+ * @return the created ARM Shr node
*/
-static ir_node *gen_Shr(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *result;
- ir_node *block = get_nodes_block(irn);
- ir_node *op1 = get_Shr_left(irn);
- ir_node *op2 = get_Shr_right(irn);
- ir_mode *mode = get_irn_mode(irn);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbg = get_irn_dbg_info(irn);
-
- if (is_arm_Mov_i(op2)) {
- result = new_rd_arm_Mov(dbg, irg, block, op1, mode, ARM_SHF_LSR, get_arm_value(op2));
- } else {
- result = new_rd_arm_Shr(dbg, irg, block, op1, op2, mode);
- }
- return result;
+static ir_node *gen_Shr(ir_node *node)
+{
+ return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
}
/**
- * Creates an arm Shrs.
+ * Creates an ARM Shrs.
*
- * @param env The transformation environment
- * @return the created arm Shrs node
+ * @return the created ARM Shrs node
*/
-static ir_node *gen_Shrs(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *result;
- ir_node *block = get_nodes_block(irn);
- ir_node *op1 = get_Shrs_left(irn);
- ir_node *op2 = get_Shrs_right(irn);
- ir_mode *mode = get_irn_mode(irn);
- dbg_info *dbg = get_irn_dbg_info(irn);
-
- if (is_arm_Mov_i(op2)) {
- result = new_rd_arm_Mov(dbg, current_ir_graph, block, op1, mode, ARM_SHF_ASR, get_arm_value(op2));
- } else {
- result = new_rd_arm_Shrs(dbg, current_ir_graph, block, op1, op2, mode);
+static ir_node *gen_Shrs(ir_node *node)
+{
+ return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
+}
+
+/**
+ * Creates an ARM Ror.
+ *
+ * @return the created ARM Ror node
+ */
+static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *new_op1 = be_transform_node(op1);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_op2 = be_transform_node(op2);
+
+ return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
+ ARM_SHF_ROR_REG);
+}
+
+/**
+ * Creates an ARM Rol.
+ *
+ * @return the created ARM Rol node
+ *
+ * Note: there is no Rol on arm, we have to use Ror
+ */
+static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *new_op1 = be_transform_node(op1);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_op2 = be_transform_node(op2);
+
+ new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
+ return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
+ ARM_SHF_ROR_REG);
+}
+
+/**
+ * Creates an ARM ROR from a Firm Rotl.
+ *
+ * @return the created ARM Ror node
+ */
+static ir_node *gen_Rotl(ir_node *node)
+{
+ ir_node *rotate = NULL;
+ ir_node *op1 = get_Rotl_left(node);
+ ir_node *op2 = get_Rotl_right(node);
+
+ /* Firm has only RotL, so we are looking for a right (op2)
+ operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
+ that means we can create a RotR. */
+
+ if (is_Add(op2)) {
+ ir_node *right = get_Add_right(op2);
+ if (is_Const(right)) {
+ tarval *tv = get_Const_tarval(right);
+ ir_mode *mode = get_irn_mode(node);
+ long bits = get_mode_size_bits(mode);
+ ir_node *left = get_Add_left(op2);
+
+ if (is_Minus(left) &&
+ tarval_is_long(tv) &&
+ get_tarval_long(tv) == bits &&
+ bits == 32)
+ rotate = gen_Ror(node, op1, get_Minus_op(left));
+ }
+ } else if (is_Sub(op2)) {
+ ir_node *left = get_Sub_left(op2);
+ if (is_Const(left)) {
+ tarval *tv = get_Const_tarval(left);
+ ir_mode *mode = get_irn_mode(node);
+ long bits = get_mode_size_bits(mode);
+ ir_node *right = get_Sub_right(op2);
+
+ if (tarval_is_long(tv) &&
+ get_tarval_long(tv) == bits &&
+ bits == 32)
+ rotate = gen_Ror(node, op1, right);
+ }
+ } else if (is_Const(op2)) {
+ tarval *tv = get_Const_tarval(op2);
+ ir_mode *mode = get_irn_mode(node);
+ long bits = get_mode_size_bits(mode);
+
+ if (tarval_is_long(tv) && bits == 32) {
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *new_op1 = be_transform_node(op1);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+
+ bits = (bits - get_tarval_long(tv)) & 31;
+ rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
+ }
}
- return result;
+
+ if (rotate == NULL) {
+ rotate = gen_Rol(node, op1, op2);
+ }
+
+ return rotate;
}
/**
* Transforms a Not node.
*
- * @param env The transformation environment
- * @return the created arm Not node
+ * @return the created ARM Not node
*/
-static ir_node *gen_Not(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *block = get_nodes_block(irn);
- ir_node *op = get_Not_op(irn);
- int v;
- arm_shift_modifier mod = ARM_SHF_NONE;
- tarval *tv = NULL;
- dbg_info *dbg = get_irn_dbg_info(irn);
-
- v = is_shifter_operand(op, &mod);
- if (v) {
- op = get_irn_n(op, 0);
- tv = new_tarval_from_long(v, mode_Iu);
- }
- return new_rd_arm_Mvn(dbg, current_ir_graph, block, op, get_irn_mode(irn), mod, tv);
+static ir_node *gen_Not(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *op = get_Not_op(node);
+ ir_node *new_op = be_transform_node(op);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+
+ /* TODO: we could do alot more here with all the Mvn variations */
+
+ return new_bd_arm_Mvn_reg(dbgi, block, new_op);
}
/**
* Transforms an Abs node.
*
* @param env The transformation environment
- * @return the created arm Abs node
+ * @return the created ARM Abs node
*/
-static ir_node *gen_Abs(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *block = get_nodes_block(irn);
- ir_node *op = get_Abs_op(irn);
- ir_mode *mode = get_irn_mode(irn);
- dbg_info *dbg = get_irn_dbg_info(irn);
-
- assert(mode != mode_E && "IEEE Extended FP not supported");
+static ir_node *gen_Abs(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *op = get_Abs_op(node);
+ ir_node *new_op = be_transform_node(op);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
if (mode_is_float(mode)) {
- cg->have_fp = 1;
- return new_rd_arm_fAbs(dbg, current_ir_graph, block, op, mode);
+ env_cg->have_fp_insn = 1;
+ if (USE_FPA(env_cg->isa))
+ return new_bd_arm_fpaAbs(dbgi, block, new_op, mode);
+ else if (USE_VFP(env_cg->isa)) {
+ assert(mode != mode_E && "IEEE Extended FP not supported");
+ panic("VFP not supported yet");
+ }
+ else {
+ panic("Softfloat not supported yet");
+ }
}
- return new_rd_arm_Abs(dbg, current_ir_graph, block, op, mode);
+ assert(mode_is_data(mode));
+ return new_bd_arm_Abs(dbgi, block, new_op);
}
/**
* Transforms a Minus node.
*
- * @param env The transformation environment
- * @return the created arm Minus node
+ * @return the created ARM Minus node
*/
-static ir_node *gen_Minus(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *block = get_nodes_block(irn);
- ir_node *op = get_Minus_op(irn);
- ir_mode *mode = get_irn_mode(irn);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbg = get_irn_dbg_info(irn);
+static ir_node *gen_Minus(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *op = get_Minus_op(node);
+ ir_node *new_op = be_transform_node(op);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
if (mode_is_float(mode)) {
- return new_rd_arm_fNeg(dbg, irg, block, op, mode);
+ env_cg->have_fp_insn = 1;
+ if (USE_FPA(env_cg->isa))
+ return new_bd_arm_fpaMvf(dbgi, block, op, mode);
+ else if (USE_VFP(env_cg->isa)) {
+ assert(mode != mode_E && "IEEE Extended FP not supported");
+ panic("VFP not supported yet");
+ }
+ else {
+ panic("Softfloat not supported yet");
+ }
}
- return new_rd_arm_Rsb_i(dbg, irg, block, op, mode, get_mode_null(mode));
+ assert(mode_is_data(mode));
+ return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
}
/**
* Transforms a Load.
*
- * @param mod the debug module
- * @param block the block the new node should belong to
- * @param node the ir Load node
- * @param mode node mode
- * @return the created arm Load node
+ * @return the created ARM Load node
*/
-static ir_node *gen_Load(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *block = get_nodes_block(irn);
- ir_mode *mode = get_Load_mode(irn);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbg = get_irn_dbg_info(irn);
+static ir_node *gen_Load(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *ptr = get_Load_ptr(node);
+ ir_node *new_ptr = be_transform_node(ptr);
+ ir_node *mem = get_Load_mem(node);
+ ir_node *new_mem = be_transform_node(mem);
+ ir_mode *mode = get_Load_mode(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_load = NULL;
if (mode_is_float(mode)) {
- cg->have_fp = 1;
- /* FIXME: set the load mode */
- return new_rd_arm_fLoad(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn), mode_T);
- }
- if (mode == mode_Bu) {
- return new_rd_arm_Loadb(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn), mode_T);
- }
- if (mode == mode_Bs) {
- return new_rd_arm_Loadbs(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn), mode_T);
- }
- if (mode == mode_Hu) {
- return new_rd_arm_Loadh(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn), mode_T);
- }
- if (mode == mode_Hs) {
- return new_rd_arm_Loadhs(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn), mode_T);
+ env_cg->have_fp_insn = 1;
+ if (USE_FPA(env_cg->isa))
+ new_load = new_bd_arm_fpaLdf(dbgi, block, new_ptr, new_mem, mode);
+ else if (USE_VFP(env_cg->isa)) {
+ assert(mode != mode_E && "IEEE Extended FP not supported");
+ panic("VFP not supported yet");
+ } else {
+ panic("Softfloat not supported yet");
+ }
+ } else {
+ assert(mode_is_data(mode) && "unsupported mode for Load");
+
+ new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
}
- if (mode_is_reference(mode)) {
- return new_rd_arm_Load(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn), mode_T);
+ set_irn_pinned(new_load, get_irn_pinned(node));
+
+ /* check for special case: the loaded value might not be used */
+ if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
+ /* add a result proj and a Keep to produce a pseudo use */
+ ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
+ be_new_Keep(block, 1, &proj);
}
- return new_rd_arm_Load(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn), mode_T);
+
+ return new_load;
}
/**
* Transforms a Store.
*
- * @param mod the debug module
- * @param block the block the new node should belong to
- * @param node the ir Store node
- * @param mode node mode
- * @return the created arm Store node
+ * @return the created ARM Store node
*/
-static ir_node *gen_Store(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *block = get_nodes_block(irn);
- ir_mode *mode = get_irn_mode(get_Store_value(irn));
- ir_graph *irg = current_ir_graph;
- dbg_info *dbg = get_irn_dbg_info(irn);
+static ir_node *gen_Store(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *ptr = get_Store_ptr(node);
+ ir_node *new_ptr = be_transform_node(ptr);
+ ir_node *mem = get_Store_mem(node);
+ ir_node *new_mem = be_transform_node(mem);
+ ir_node *val = get_Store_value(node);
+ ir_node *new_val = be_transform_node(val);
+ ir_mode *mode = get_irn_mode(val);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_store = NULL;
- assert(mode != mode_E && "IEEE Extended FP not supported");
if (mode_is_float(mode)) {
- cg->have_fp = 1;
- /* FIXME: set the store mode */
- return new_rd_arm_fStore(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn), mode_T);
- }
- if (mode == mode_Bu) {
- return new_rd_arm_Storeb(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn), mode_T);
- }
- if (mode == mode_Bs) {
- return new_rd_arm_Storebs(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn), mode_T);
- }
- if (mode == mode_Hu) {
- return new_rd_arm_Storeh(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn), mode_T);
- }
- if (mode == mode_Hs) {
- return new_rd_arm_Storehs(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn), mode_T);
+ env_cg->have_fp_insn = 1;
+ if (USE_FPA(env_cg->isa))
+ new_store = new_bd_arm_fpaStf(dbgi, block, new_ptr, new_val,
+ new_mem, mode);
+ else if (USE_VFP(env_cg->isa)) {
+ assert(mode != mode_E && "IEEE Extended FP not supported");
+ panic("VFP not supported yet");
+ } else {
+ panic("Softfloat not supported yet");
+ }
+ } else {
+ assert(mode_is_data(mode) && "unsupported mode for Store");
+ new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
+ NULL, 0, 0, false);
}
- return new_rd_arm_Store(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn), mode_T);
+ set_irn_pinned(new_store, get_irn_pinned(node));
+ return new_store;
}
+static ir_node *gen_Jmp(ir_node *node)
+{
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ dbg_info *dbgi = get_irn_dbg_info(node);
-static ir_node *gen_Cond(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *result = NULL;
- ir_node *selector = get_Cond_selector(irn);
- ir_node *block = get_nodes_block(irn);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbg = get_irn_dbg_info(irn);
-
- if ( get_irn_mode(selector) == mode_b ) {
- //CondJmp
- ir_node *proj_node = get_Cond_selector(irn);
- ir_node *cmp_node = get_Proj_pred(proj_node);
- ir_node *op1 = get_Cmp_left(cmp_node);
- ir_node *op2 = get_Cmp_right(cmp_node);
- result = new_rd_arm_CondJmp(dbg, irg, block, op1, op2, mode_T);
- set_arm_proj_num(result, get_Proj_proj(proj_node));
- } else {
- //SwitchJmp
- ir_node *op = get_irn_n(irn, 0);
- ir_node *const_graph;
- ir_node *sub;
- ir_node *const_node;
-
- ir_node *proj;
- const ir_edge_t *edge;
- int min = INT_MAX;
- int max = INT_MIN;
- int translation;
- int norm_max;
- int norm_min;
- int pn;
- int n_projs;
- ir_node **projs;
-
- foreach_out_edge(irn, edge) {
- proj = get_edge_src_irn(edge);
- assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
-
- pn = get_Proj_proj(proj);
-
- min = pn<min ? pn : min;
- max = pn>max ? pn : max;
- }
- translation = min;
- norm_max = max - translation;
- norm_min = min - translation;
+ return new_bd_arm_Jmp(dbgi, new_block);
+}
+
+static ir_node *gen_be_Call(ir_node *node)
+{
+ ir_node *res = be_duplicate_node(node);
+ arch_irn_add_flags(res, arch_irn_flags_modify_flags);
+
+ return res;
+}
- n_projs = norm_max + 1;
- projs = xcalloc(n_projs , sizeof(ir_node*));
+static ir_node *gen_SwitchJmp(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *selector = get_Cond_selector(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_op = be_transform_node(selector);
+ ir_node *const_graph;
+ ir_node *sub;
+
+ ir_node *proj;
+ const ir_edge_t *edge;
+ int min = INT_MAX;
+ int max = INT_MIN;
+ int translation;
+ int pn;
+ int n_projs;
+
+ foreach_out_edge(node, edge) {
+ proj = get_edge_src_irn(edge);
+ assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
+
+ pn = get_Proj_proj(proj);
+
+ min = pn<min ? pn : min;
+ max = pn>max ? pn : max;
+ }
+ translation = min;
+ n_projs = max - translation + 1;
+
+ foreach_out_edge(node, edge) {
+ proj = get_edge_src_irn(edge);
+ assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
+
+ pn = get_Proj_proj(proj) - translation;
+ set_Proj_proj(proj, pn);
+ }
+ const_graph = create_const_graph_value(dbgi, block, translation);
+ sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
+ return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
+}
- foreach_out_edge(irn, edge) {
- proj = get_edge_src_irn(edge);
- assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
+static ir_node *gen_Cmp(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *op1 = get_Cmp_left(node);
+ ir_node *op2 = get_Cmp_right(node);
+ ir_mode *cmp_mode = get_irn_mode(op1);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_op1;
+ ir_node *new_op2;
+ bool is_unsigned;
+
+ if (mode_is_float(cmp_mode)) {
+ /* TODO: revivie this code */
+ panic("FloatCmp NIY");
+#if 0
+ ir_node *new_op2 = be_transform_node(op2);
+ /* floating point compare */
+ pn_Cmp pnc = get_Proj_proj(selector);
- pn = get_Proj_proj(proj) - translation;
- set_Proj_proj(proj, pn);
+ if (pnc & pn_Cmp_Uo) {
+ /* check for unordered, need cmf */
+ return new_bd_arm_fpaCmfBra(dbgi, block, new_op1, new_op2, pnc);
}
+ /* Hmm: use need cmfe */
+ return new_bd_arm_fpaCmfeBra(dbgi, block, new_op1, new_op2, pnc);
+#endif
+ }
+ assert(get_irn_mode(op2) == cmp_mode);
+ is_unsigned = !mode_is_signed(cmp_mode);
- const_node = new_rd_Const(dbg, irg, block, mode_Iu, new_tarval_from_long(translation, mode_Iu));
- const_graph = gen_Const(const_node, cg);
- sub = new_rd_arm_Sub(dbg, irg, block, op, const_graph, get_irn_mode(op), ARM_SHF_NONE, NULL);
- result = new_rd_arm_SwitchJmp(dbg, irg, block, sub, mode_T);
- set_arm_n_projs(result, n_projs);
- set_arm_default_proj_num(result, get_Cond_defaultProj(irn)-translation);
+ /* compare with 0 can be done with Tst */
+ if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) {
+ new_op1 = be_transform_node(op1);
+ new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
+ return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false,
+ is_unsigned);
}
- return result;
+ if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) {
+ new_op2 = be_transform_node(op2);
+ new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
+ return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true,
+ is_unsigned);
+ }
+
+ /* integer compare, TODO: use shifer_op in all its combinations */
+ new_op1 = be_transform_node(op1);
+ new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
+ new_op2 = be_transform_node(op2);
+ new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
+ return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
+ is_unsigned);
}
/**
- * Returns the name of a SymConst.
- * @param symc the SymConst
- * @return name of the SymConst
+ * Transforms a Cond.
+ *
+ * @return the created ARM Cond node
*/
-const char *get_sc_name(ir_node *symc) {
- if (get_irn_opcode(symc) != iro_SymConst)
- return "NONE";
+static ir_node *gen_Cond(ir_node *node)
+{
+ ir_node *selector = get_Cond_selector(node);
+ ir_mode *mode = get_irn_mode(selector);
+ ir_node *block;
+ ir_node *flag_node;
+ dbg_info *dbgi;
+
+ if (mode != mode_b) {
+ return gen_SwitchJmp(node);
+ }
+ assert(is_Proj(selector));
- switch (get_SymConst_kind(symc)) {
- case symconst_addr_name:
- return get_id_str(get_SymConst_name(symc));
+ block = be_transform_node(get_nodes_block(node));
+ dbgi = get_irn_dbg_info(node);
+ flag_node = be_transform_node(get_Proj_pred(selector));
- case symconst_addr_ent:
- return get_entity_ld_name(get_SymConst_entity(symc));
+ return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector));
+}
+
+static tarval *fpa_imm[3][fpa_max];
- default:
- assert(0 && "Unsupported SymConst");
+#if 0
+/**
+ * Check, if a floating point tarval is an fpa immediate, i.e.
+ * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
+ */
+static int is_fpa_immediate(tarval *tv)
+{
+ ir_mode *mode = get_tarval_mode(tv);
+ int i, j, res = 1;
+
+ switch (get_mode_size_bits(mode)) {
+ case 32:
+ i = 0;
+ break;
+ case 64:
+ i = 1;
+ break;
+ default:
+ i = 2;
}
- return NULL;
-}
+ if (tarval_is_negative(tv)) {
+ tv = tarval_neg(tv);
+ res = -1;
+ }
-static ir_node *gen_SymConst(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *block = get_nodes_block(irn);
- ir_mode *mode = get_irn_mode(irn);
- dbg_info *dbg = get_irn_dbg_info(irn);
- return new_rd_arm_SymConst(dbg, current_ir_graph, block, mode, get_sc_name(irn));
+ for (j = 0; j < fpa_max; ++j) {
+ if (tv == fpa_imm[i][j])
+ return res * j;
+ }
+ return fpa_max;
}
-
-
+#endif
/**
- * Transforms a CopyB node.
+ * Transforms a Const node.
*
- * @param env The transformation environment
- * @return The transformed node.
+ * @return The transformed ARM node.
*/
-static ir_node *gen_CopyB(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *res = NULL;
- dbg_info *dbg = get_irn_dbg_info(irn);
- ir_mode *mode = get_irn_mode(irn);
- ir_node *src = get_CopyB_src(irn);
- ir_node *dst = get_CopyB_dst(irn);
- ir_node *mem = get_CopyB_mem(irn);
- ir_node *block = get_nodes_block(irn);
- int size = get_type_size_bytes(get_CopyB_type(irn));
- ir_graph *irg = current_ir_graph;
- ir_node *src_copy;
- ir_node *dst_copy;
-
- src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, src);
- dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, dst);
+static ir_node *gen_Const(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_mode *mode = get_irn_mode(node);
+ dbg_info *dbg = get_irn_dbg_info(node);
- res = new_rd_arm_CopyB( dbg, irg, block, dst_copy, src_copy, new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), mem, mode);
- set_arm_value(res, new_tarval_from_long(size, mode_Iu));
+ if (mode_is_float(mode)) {
+ env_cg->have_fp_insn = 1;
+ if (USE_FPA(env_cg->isa)) {
+ tarval *tv = get_Const_tarval(node);
+#if 0
+ int imm = is_fpa_immediate(tv);
- return res;
+ if (imm != fpa_max) {
+ if (imm > 0)
+ node = new_bd_arm_fpaMvf_i(dbg, block, mode, imm);
+ else
+ node = new_bd_arm_fpaMnf_i(dbg, block, mode, -imm);
+ } else {
+#endif
+ {
+ node = new_bd_arm_fpaConst(dbg, block, tv);
+ }
+ be_dep_on_frame(node);
+ return node;
+ }
+ else if (USE_VFP(env_cg->isa)) {
+ assert(mode != mode_E && "IEEE Extended FP not supported");
+ panic("VFP not supported yet");
+ }
+ else {
+ panic("Softfloat not supported yet");
+ }
+ }
+ return create_const_graph(node, block);
}
+/**
+ * Transforms a SymConst node.
+ *
+ * @return The transformed ARM node.
+ */
+static ir_node *gen_SymConst(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_entity *entity = get_SymConst_entity(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_node;
+
+ new_node = new_bd_arm_SymConst(dbgi, block, entity);
+ be_dep_on_frame(new_node);
+ return new_node;
+}
+/**
+ * Transforms a CopyB node.
+ *
+ * @return The transformed ARM node.
+ */
+static ir_node *gen_CopyB(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *src = get_CopyB_src(node);
+ ir_node *new_src = be_transform_node(src);
+ ir_node *dst = get_CopyB_dst(node);
+ ir_node *new_dst = be_transform_node(dst);
+ ir_node *mem = get_CopyB_mem(node);
+ ir_node *new_mem = be_transform_node(mem);
+ dbg_info *dbg = get_irn_dbg_info(node);
+ int size = get_type_size_bytes(get_CopyB_type(node));
+ ir_node *src_copy;
+ ir_node *dst_copy;
+
+ src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
+ dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
+
+ return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
+ new_bd_arm_EmptyReg(dbg, block),
+ new_bd_arm_EmptyReg(dbg, block),
+ new_bd_arm_EmptyReg(dbg, block),
+ new_mem, size);
+}
+/**
+ * Transforms a FrameAddr into an ARM Add.
+ */
+static ir_node *gen_be_FrameAddr(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_entity *ent = be_get_frame_entity(node);
+ ir_node *fp = be_get_FrameAddr_frame(node);
+ ir_node *new_fp = be_transform_node(fp);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_node;
+
+ new_node = new_bd_arm_FrameAddr(dbgi, block, new_fp, ent);
+ return new_node;
+}
+/**
+ * Transform a be_AddSP into an arm_AddSP. Eat up const sizes.
+ */
+static ir_node *gen_be_AddSP(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
+ ir_node *new_sz = be_transform_node(sz);
+ ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
+ ir_node *new_sp = be_transform_node(sp);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *nomem = new_NoMem();
+ ir_node *new_op;
+
+ /* ARM stack grows in reverse direction, make a SubSPandCopy */
+ new_op = new_bd_arm_SubSPandCopy(dbgi, block, new_sp, new_sz, nomem);
-/********************************************
- * _ _
- * | | | |
- * | |__ ___ _ __ ___ __| | ___ ___
- * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
- * | |_) | __/ | | | (_) | (_| | __/\__ \
- * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
- *
- ********************************************/
+ return new_op;
+}
/**
- * Return an expanding stack offset.
- * Note that function is called in the transform phase
- * where the stack offsets are still relative regarding
- * the first (frame allocating) IncSP.
- * However this is exactly what we want because frame
- * access must be done relative the the fist IncSP ...
+ * Transform a be_SubSP into an arm_SubSP. Eat up const sizes.
*/
-static int get_sp_expand_offset(ir_node *inc_sp) {
- unsigned offset = be_get_IncSP_offset(inc_sp);
- be_stack_dir_t dir = be_get_IncSP_direction(inc_sp);
+static ir_node *gen_be_SubSP(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
+ ir_node *new_sz = be_transform_node(sz);
+ ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
+ ir_node *new_sp = be_transform_node(sp);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *nomem = new_NoMem();
+ ir_node *new_op;
+
+ /* ARM stack grows in reverse direction, make an AddSP */
+ new_op = new_bd_arm_AddSP(dbgi, block, new_sp, new_sz, nomem);
- if (offset == BE_STACK_FRAME_SIZE)
- return 0;
- return dir == be_stack_dir_expand ? (int)offset : -(int)offset;
+ return new_op;
}
-static ir_node *gen_StackParam(ir_node *irn, arm_code_gen_t *cg) {
-#if 0
- ir_node *new_op = NULL;
- ir_node *block = get_nodes_block(irn);
- ir_node *noreg = ia32_new_NoReg_gp(env->cg);
- ir_node *mem = new_rd_NoMem(env->irg);
- ir_node *ptr = get_irn_n(irn, 0);
- entity *ent = be_get_frame_entity(irn);
- ir_mode *mode = env->mode;
-
-// /* If the StackParam has only one user -> */
-// /* put it in the Block where the user resides */
-// if (get_irn_n_edges(node) == 1) {
-// env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
-// }
+/**
+ * Transform a be_Copy.
+ */
+static ir_node *gen_be_Copy(ir_node *node)
+{
+ ir_node *result = be_duplicate_node(node);
+ ir_mode *mode = get_irn_mode(result);
- if (mode_is_float(mode)) {
- if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_fLoad(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
- else {
- env->cg->used_x87 = 1;
- new_op = new_rd_ia32_vfld(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
- }
- }
- else {
- new_op = new_rd_ia32_Load(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
+ if (mode_needs_gp_reg(mode)) {
+ set_irn_mode(node, mode_Iu);
}
- set_ia32_frame_ent(new_op, ent);
- set_ia32_use_frame(new_op);
-
- set_ia32_am_support(new_op, ia32_am_Source);
- set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, ia32_B);
- set_ia32_ls_mode(new_op, mode);
-
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
-
- return new_rd_Proj(env->dbg, env->irg, block, new_op, mode, 0);
-#endif
+ return result;
}
/**
- * Transforms a FrameAddr into an ia32 Add.
+ * Transform a Proj from a Load.
*/
-static ir_node *gen_be_FrameAddr(ir_node *irn, arm_code_gen_t *cg) {
- ir_node *block = get_nodes_block(irn);
- entity *ent = be_get_frame_entity(irn);
- int offset = get_entity_offset_bytes(ent);
- ir_node *op = get_irn_n(irn, 0);
- ir_node *cnst;
- ir_mode *mode = get_irn_mode(irn);
- dbg_info *dbg = get_irn_dbg_info(irn);
-
- if (be_is_IncSP(op)) {
- /* BEWARE: we get an offset which is absolute from an offset that
- is relative. Both must be merged */
- offset += get_sp_expand_offset(op);
+static ir_node *gen_Proj_Load(ir_node *node)
+{
+ ir_node *load = get_Proj_pred(node);
+ ir_node *new_load = be_transform_node(load);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
+
+ /* renumber the proj */
+ switch (get_arm_irn_opcode(new_load)) {
+ case iro_arm_Ldr:
+ /* handle all gp loads equal: they have the same proj numbers. */
+ if (proj == pn_Load_res) {
+ return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
+ } else if (proj == pn_Load_M) {
+ return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
+ }
+ break;
+ case iro_arm_fpaLdf:
+ if (proj == pn_Load_res) {
+ ir_mode *mode = get_Load_mode(load);
+ return new_rd_Proj(dbgi, new_load, mode, pn_arm_fpaLdf_res);
+ } else if (proj == pn_Load_M) {
+ return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_fpaLdf_M);
+ }
+ break;
+ default:
+ break;
}
- cnst = create_const_graph_value(irn, block, (unsigned)offset);
- if (is_arm_Mov_i(cnst))
- return new_rd_arm_Add_i(dbg, current_ir_graph, block, op, mode, get_arm_value(cnst));
- return new_rd_arm_Add(dbg, current_ir_graph, block, op, cnst, mode, ARM_SHF_NONE, NULL);
+ panic("Unsupported Proj from Load");
}
/**
- * Transforms a FrameLoad into an ia32 Load.
+ * Transform and renumber the Projs from a CopyB.
*/
-static ir_node *gen_FrameLoad(ir_node *irn, arm_code_gen_t *cg) {
-#if 0
- ir_node *new_op = NULL;
- ir_node *noreg = ia32_new_NoReg_gp(env->cg);
- ir_node *mem = get_irn_n(irn, 0);
- ir_node *ptr = get_irn_n(irn, 1);
- entity *ent = be_get_frame_entity(irn);
- ir_mode *mode = get_type_mode(get_entity_type(ent));
-
- if (mode_is_float(mode)) {
- if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_fLoad(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
- else {
- env->cg->used_x87 = 1;
- new_op = new_rd_ia32_vfld(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
+static ir_node *gen_Proj_CopyB(ir_node *node)
+{
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = be_transform_node(pred);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
+
+ switch (proj) {
+ case pn_CopyB_M_regular:
+ if (is_arm_CopyB(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
}
+ break;
+ default:
+ break;
}
- else {
- new_op = new_rd_ia32_Load(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
- }
+ panic("Unsupported Proj from CopyB");
+}
- set_ia32_frame_ent(new_op, ent);
- set_ia32_use_frame(new_op);
+/**
+ * Transform and renumber the Projs from a Quot.
+ */
+static ir_node *gen_Proj_Quot(ir_node *node)
+{
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = be_transform_node(pred);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ long proj = get_Proj_proj(node);
+
+ switch (proj) {
+ case pn_Quot_M:
+ if (is_arm_fpaDvf(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaDvf_M);
+ } else if (is_arm_fpaRdf(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaRdf_M);
+ } else if (is_arm_fpaFdv(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaFdv_M);
+ } else if (is_arm_fpaFrd(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaFrd_M);
+ }
+ break;
+ case pn_Quot_res:
+ if (is_arm_fpaDvf(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaDvf_res);
+ } else if (is_arm_fpaRdf(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaRdf_res);
+ } else if (is_arm_fpaFdv(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaFdv_res);
+ } else if (is_arm_fpaFrd(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaFrd_res);
+ }
+ break;
+ default:
+ break;
+ }
+ panic("Unsupported Proj from Quot");
+}
- set_ia32_am_support(new_op, ia32_am_Source);
- set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, ia32_B);
- set_ia32_ls_mode(new_op, mode);
+/**
+ * Transform the Projs of a be_AddSP.
+ */
+static ir_node *gen_Proj_be_AddSP(ir_node *node)
+{
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = be_transform_node(pred);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
+
+ if (proj == pn_be_AddSP_sp) {
+ ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu,
+ pn_arm_SubSPandCopy_stack);
+ arch_set_irn_register(res, &arm_gp_regs[REG_SP]);
+ return res;
+ } else if (proj == pn_be_AddSP_res) {
+ return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_arm_SubSPandCopy_addr);
+ } else if (proj == pn_be_AddSP_M) {
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_SubSPandCopy_M);
+ }
+ panic("Unsupported Proj from AddSP");
+}
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
+/**
+ * Transform the Projs of a be_SubSP.
+ */
+static ir_node *gen_Proj_be_SubSP(ir_node *node)
+{
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = be_transform_node(pred);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
+
+ if (proj == pn_be_SubSP_sp) {
+ ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu,
+ pn_arm_AddSP_stack);
+ arch_set_irn_register(res, &arm_gp_regs[REG_SP]);
+ return res;
+ } else if (proj == pn_be_SubSP_M) {
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_AddSP_M);
+ }
+ panic("Unsupported Proj from SubSP");
+}
- return new_op;
-#endif
+/**
+ * Transform the Projs from a Cmp.
+ */
+static ir_node *gen_Proj_Cmp(ir_node *node)
+{
+ (void) node;
+ panic("Mux NYI");
}
/**
- * Transforms a FrameStore into an ia32 Store.
+ * Transform the Thread Local Storage Proj.
*/
-static ir_node *gen_FrameStore(ir_node *irn, arm_code_gen_t *cg) {
-#if 0
- ir_node *new_op = NULL;
- ir_node *noreg = ia32_new_NoReg_gp(env->cg);
- ir_node *mem = get_irn_n(irn, 0);
- ir_node *ptr = get_irn_n(irn, 1);
- ir_node *val = get_irn_n(irn, 2);
- entity *ent = be_get_frame_entity(irn);
- ir_mode *mode = get_irn_mode(val);
+static ir_node *gen_Proj_tls(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ dbg_info *dbgi = NULL;
- if (mode_is_float(mode)) {
- if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
- else {
- env->cg->used_x87 = 1;
- new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+ return new_bd_arm_LdTls(dbgi, block, mode_Iu);
+}
+
+/**
+ * Transform a Proj node.
+ */
+static ir_node *gen_Proj(ir_node *node)
+{
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *pred = get_Proj_pred(node);
+ long proj = get_Proj_proj(node);
+
+ if (is_Store(pred)) {
+ if (proj == pn_Store_M) {
+ return be_transform_node(pred);
+ } else {
+ panic("Unsupported Proj from Store");
+ }
+ } else if (is_Load(pred)) {
+ return gen_Proj_Load(node);
+ } else if (is_CopyB(pred)) {
+ return gen_Proj_CopyB(node);
+ } else if (is_Quot(pred)) {
+ return gen_Proj_Quot(node);
+ } else if (be_is_SubSP(pred)) {
+ return gen_Proj_be_SubSP(node);
+ } else if (be_is_AddSP(pred)) {
+ return gen_Proj_be_AddSP(node);
+ } else if (is_Cmp(pred)) {
+ return gen_Proj_Cmp(node);
+ } else if (is_Start(pred)) {
+ if (proj == pn_Start_X_initial_exec) {
+ ir_node *block = get_nodes_block(pred);
+ ir_node *jump;
+
+ /* we exchange the ProjX with a jump */
+ block = be_transform_node(block);
+ jump = new_rd_Jmp(dbgi, block);
+ return jump;
+ }
+ if (node == get_irg_anchor(irg, anchor_tls)) {
+ return gen_Proj_tls(node);
+ }
+ } else {
+ ir_node *new_pred = be_transform_node(pred);
+ ir_mode *mode = get_irn_mode(node);
+ if (mode_needs_gp_reg(mode)) {
+ ir_node *new_proj = new_r_Proj(new_pred, mode_Iu,
+ get_Proj_proj(node));
+ new_proj->node_nr = node->node_nr;
+ return new_proj;
}
- }
- else if (get_mode_size_bits(mode) == 8) {
- new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
- }
- else {
- new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
}
- set_ia32_frame_ent(new_op, ent);
- set_ia32_use_frame(new_op);
+ return be_duplicate_node(node);
+}
- set_ia32_am_support(new_op, ia32_am_Dest);
- set_ia32_op_type(new_op, ia32_AddrModeD);
- set_ia32_am_flavour(new_op, ia32_B);
- set_ia32_ls_mode(new_op, mode);
+typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
+static inline ir_node *create_const(ir_node **place,
+ create_const_node_func func,
+ const arch_register_t* reg)
+{
+ ir_node *block, *res;
- return new_op;
-#endif
-}
+ if (*place != NULL)
+ return *place;
+ block = get_irg_start_block(env_cg->irg);
+ res = func(NULL, block);
+ arch_set_irn_register(res, reg);
+ *place = res;
+ return res;
+}
-// static ir_node *gen_be_Copy(ir_node *irn, arm_code_gen_t *cg) {
-// return new_rd_arm_Copy(env->dbg, env->irg, env->block, op, env->mode);
-// }
+static ir_node *gen_Unknown(ir_node *node)
+{
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ dbg_info *dbgi = get_irn_dbg_info(node);
-/*********************************************************
- * _ _ _
- * (_) | | (_)
- * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
- * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
- * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
- * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
- *
- *********************************************************/
-
-/************************************************************************/
-/* move constants out of startblock */
-/************************************************************************/
-void arm_move_consts(ir_node *node, void *env) {
- arm_code_gen_t *cgenv = (arm_code_gen_t *)env;
- int i;
-
- if (is_Block(node))
- return;
-
- if (is_Phi(node)) {
- for (i = 0; i < get_irn_arity(node); i++) {
- ir_node *pred = get_irn_n(node,i);
- opcode pred_code = get_irn_opcode(pred);
- if (pred_code == iro_Const) {
- ir_node *const_graph;
- const_graph = create_const_graph(pred, get_nodes_block(get_irn_n(get_nodes_block(node),i)));
- set_irn_n(node, i, const_graph);
- } else if (pred_code == iro_SymConst) {
- const char *str = get_sc_name(pred);
- ir_node *symconst_node;
- symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
- current_ir_graph, get_nodes_block(get_irn_n(get_nodes_block(node),i)),
- get_irn_mode(pred), str);
- set_irn_n(node, i, symconst_node);
- }
- }
- return;
- }
- for (i = 0; i < get_irn_arity(node); i++) {
- ir_node *pred = get_irn_n(node,i);
- opcode pred_code = get_irn_opcode(pred);
- if (pred_code == iro_Const) {
- ir_node *const_graph;
- const_graph = create_const_graph(pred, get_nodes_block(node));
- set_irn_n(node, i, const_graph);
- } else if (pred_code == iro_SymConst) {
- const char *str = get_sc_name(pred);
- ir_node *symconst_node;
- symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
- current_ir_graph, get_nodes_block(node),
- get_irn_mode(pred), str);
- set_irn_n(node, i, symconst_node);
- }
+ /* just produce a 0 */
+ ir_mode *mode = get_irn_mode(node);
+ if (mode_is_float(mode)) {
+ tarval *tv = get_mode_null(mode);
+ ir_node *node = new_bd_arm_fpaConst(dbgi, new_block, tv);
+ be_dep_on_frame(node);
+ return node;
+ } else if (mode_needs_gp_reg(mode)) {
+ return create_const_graph_value(dbgi, new_block, 0);
}
-}
+ panic("Unexpected Unknown mode");
+}
-/************************************************************************/
-/* move symbolic constants out of startblock */
-/************************************************************************/
-void arm_move_symconsts(ir_node *node, void *env) {
- int i;
+/**
+ * Change some phi modes
+ */
+static ir_node *gen_Phi(ir_node *node)
+{
+ const arch_register_req_t *req;
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *phi;
+
+ if (mode_needs_gp_reg(mode)) {
+ /* we shouldn't have any 64bit stuff around anymore */
+ assert(get_mode_size_bits(mode) <= 32);
+ /* all integer operations are on 32bit registers now */
+ mode = mode_Iu;
+ req = arm_reg_classes[CLASS_arm_gp].class_req;
+ } else {
+ req = arch_no_register_req;
+ }
- if (is_Block(node))
- return;
+ /* phi nodes allow loops, so we use the old arguments for now
+ * and fix this later */
+ phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
+ get_irn_in(node) + 1);
+ copy_node_attr(irg, node, phi);
+ be_duplicate_deps(node, phi);
- for (i = 0; i < get_irn_arity(node); i++) {
- ir_node *pred = get_irn_n(node,i);
- opcode pred_code = get_irn_opcode(pred);
+ arch_set_out_register_req(phi, 0, req);
- if (pred_code == iro_SymConst) {
- const char *str = get_sc_name(pred);
- ir_node *symconst_node;
+ be_enqueue_preds(node);
- symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
- current_ir_graph, get_nodes_block(node), get_irn_mode(pred), str);
- set_irn_n(node, i, symconst_node);
- }
- }
+ return phi;
}
/**
* the BAD transformer.
*/
-static ir_node *bad_transform(ir_node *irn, arm_code_gen_t *cg) {
- ir_fprintf(stderr, "Not implemented: %+F\n", irn);
- assert(0);
- return NULL;
+static ir_node *bad_transform(ir_node *irn)
+{
+ panic("ARM backend: unexpected node %+F", irn);
}
/**
- * Enters all transform functions into the generic pointer
+ * Set a node emitter. Make it a bit more type safe.
*/
-void arm_register_transformers(void) {
- ir_op *op_Max, *op_Min, *op_Mulh;
+static void set_transformer(ir_op *op, be_transform_func arm_transform_func)
+{
+ op->ops.generic = (op_func)arm_transform_func;
+}
+/**
+ * Enters all transform functions into the generic pointer
+ */
+static void arm_register_transformers(void)
+{
/* first clear the generic function pointer for all ops */
clear_irp_opcodes_generic_func();
-#define FIRM_OP(a) op_##a->ops.generic = (op_func)gen_##a
-#define BAD(a) op_##a->ops.generic = (op_func)bad_transform
-#define IGN(a)
-
- FIRM_OP(Add); // done
- FIRM_OP(Mul); // done
- FIRM_OP(Quot); // done
- FIRM_OP(And); // done
- FIRM_OP(Or); // done
- FIRM_OP(Eor); // done
-
- FIRM_OP(Sub); // done
- FIRM_OP(Shl); // done
- FIRM_OP(Shr); // done
- FIRM_OP(Shrs); // done
-
- FIRM_OP(Minus); // done
- FIRM_OP(Not); // done
- FIRM_OP(Abs); // done
-
- FIRM_OP(CopyB); // done
- FIRM_OP(Const); // TODO: floating point consts
- FIRM_OP(Conv); // TODO: floating point conversions
-
- FIRM_OP(Load); // done
- FIRM_OP(Store); // done
-
- FIRM_OP(SymConst);
- FIRM_OP(Cond); // integer done
-
- /* TODO: implement these nodes */
-
- IGN(Div); // intrinsic lowering
- IGN(Mod); // intrinsic lowering
- IGN(DivMod); // TODO: implement DivMod
-
- IGN(Mux);
- IGN(Unknown);
- IGN(Cmp); // done, implemented in cond
-
- /* You probably don't need to handle the following nodes */
-
- IGN(Call);
- IGN(Proj);
- IGN(Alloc);
-
- IGN(Block);
- IGN(Start);
- IGN(End);
- IGN(NoMem);
- IGN(Phi);
- IGN(IJmp);
- IGN(Jmp); // emitter done
- IGN(Break);
- IGN(Sync);
-
- BAD(Raise);
- BAD(Sel);
- BAD(InstOf);
- BAD(Cast);
- BAD(Free);
- BAD(Tuple);
- BAD(Id);
- BAD(Bad);
- BAD(Confirm);
- BAD(Filter);
- BAD(CallBegin);
- BAD(EndReg);
- BAD(EndExcept);
-
- FIRM_OP(be_FrameAddr);
-
- op_Max = get_op_Max();
- if (op_Max)
- BAD(Max);
- op_Min = get_op_Min();
- if (op_Min)
- BAD(Min);
- op_Mulh = get_op_Mulh();
- if (op_Mulh)
- BAD(Mulh);
-
-#undef IGN
-#undef FIRM_OP
-#undef BAD
+ set_transformer(op_Abs, gen_Abs);
+ set_transformer(op_Add, gen_Add);
+ set_transformer(op_And, gen_And);
+ set_transformer(op_be_AddSP, gen_be_AddSP);
+ set_transformer(op_be_Call, gen_be_Call);
+ set_transformer(op_be_Copy, gen_be_Copy);
+ set_transformer(op_be_FrameAddr, gen_be_FrameAddr);
+ set_transformer(op_be_SubSP, gen_be_SubSP);
+ set_transformer(op_Cmp, gen_Cmp);
+ set_transformer(op_Cond, gen_Cond);
+ set_transformer(op_Const, gen_Const);
+ set_transformer(op_Conv, gen_Conv);
+ set_transformer(op_CopyB, gen_CopyB);
+ set_transformer(op_Eor, gen_Eor);
+ set_transformer(op_Jmp, gen_Jmp);
+ set_transformer(op_Load, gen_Load);
+ set_transformer(op_Minus, gen_Minus);
+ set_transformer(op_Mul, gen_Mul);
+ set_transformer(op_Not, gen_Not);
+ set_transformer(op_Or, gen_Or);
+ set_transformer(op_Phi, gen_Phi);
+ set_transformer(op_Proj, gen_Proj);
+ set_transformer(op_Quot, gen_Quot);
+ set_transformer(op_Rotl, gen_Rotl);
+ set_transformer(op_Shl, gen_Shl);
+ set_transformer(op_Shr, gen_Shr);
+ set_transformer(op_Shrs, gen_Shrs);
+ set_transformer(op_Store, gen_Store);
+ set_transformer(op_Sub, gen_Sub);
+ set_transformer(op_SymConst, gen_SymConst);
+ set_transformer(op_Unknown, gen_Unknown);
+
+ set_transformer(op_ASM, bad_transform);
+ set_transformer(op_Builtin, bad_transform);
+ set_transformer(op_CallBegin, bad_transform);
+ set_transformer(op_Cast, bad_transform);
+ set_transformer(op_Confirm, bad_transform);
+ set_transformer(op_DivMod, bad_transform);
+ set_transformer(op_EndExcept, bad_transform);
+ set_transformer(op_EndReg, bad_transform);
+ set_transformer(op_Filter, bad_transform);
+ set_transformer(op_Free, bad_transform);
+ set_transformer(op_Id, bad_transform);
+ set_transformer(op_InstOf, bad_transform);
+ set_transformer(op_Mulh, bad_transform);
+ set_transformer(op_Mux, bad_transform);
+ set_transformer(op_Raise, bad_transform);
+ set_transformer(op_Sel, bad_transform);
+ set_transformer(op_Tuple, bad_transform);
}
-typedef ir_node *(transform_func)(ir_node *irn, arm_code_gen_t *cg);
-
/**
- * Transforms the given firm node (and maybe some other related nodes)
- * into one or more assembler nodes.
- *
- * @param node the firm node
- * @param env the debug module
+ * Initialize fpa Immediate support.
*/
-void arm_transform_node(ir_node *node, void *env) {
- arm_code_gen_t *cg = (arm_code_gen_t *)env;
- ir_op *op = get_irn_op(node);
- ir_node *asm_node = NULL;
-
- if (op == op_Block)
- return;
-
- DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
+static void arm_init_fpa_immediate(void)
+{
+ /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
+ fpa_imm[0][fpa_null] = get_mode_null(mode_F);
+ fpa_imm[0][fpa_one] = get_mode_one(mode_F);
+ fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
+ fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
+ fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
+ fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
+ fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
+ fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
+
+ fpa_imm[1][fpa_null] = get_mode_null(mode_D);
+ fpa_imm[1][fpa_one] = get_mode_one(mode_D);
+ fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
+ fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
+ fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
+ fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
+ fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
+ fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
+
+ fpa_imm[2][fpa_null] = get_mode_null(mode_E);
+ fpa_imm[2][fpa_one] = get_mode_one(mode_E);
+ fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
+ fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
+ fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
+ fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
+ fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
+ fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
+}
- if (op->ops.generic) {
- transform_func *transform = (transform_func *)op->ops.generic;
+/**
+ * Transform a Firm graph into an ARM graph.
+ */
+void arm_transform_graph(arm_code_gen_t *cg)
+{
+ static int imm_initialized = 0;
- asm_node = (*transform)(node, cg);
+ if (! imm_initialized) {
+ arm_init_fpa_immediate();
+ imm_initialized = 1;
}
+ arm_register_transformers();
+ env_cg = cg;
+ be_transform_graph(cg->irg, NULL);
+}
- if (asm_node) {
- exchange(node, asm_node);
- DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
- }
- else {
- DB((cg->mod, LEVEL_1, "ignored\n"));
- }
+void arm_init_transform(void)
+{
+ FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");
}
projects / libfirm / blobdiff