#include "irmode_t.h"
#include "irgmod.h"
#include "iredges.h"
-#include "irvrfy.h"
#include "ircons.h"
#include "irprintf.h"
#include "dbginfo.h"
typedef enum {
MATCH_NONE = 0,
- MATCH_COMMUTATIVE = 1 << 0,
- MATCH_SIZE_NEUTRAL = 1 << 1,
+ MATCH_COMMUTATIVE = 1 << 0, /**< commutative node */
+ MATCH_REVERSE = 1 << 1, /**< support reverse opcode */
+ MATCH_SIZE_NEUTRAL = 1 << 2,
+ MATCH_SKIP_NOT = 1 << 3, /**< skip Not on ONE input */
} match_flags_t;
-typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
-typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
+/**
+ * possible binop constructors.
+ */
+typedef struct arm_binop_factory_t {
+ /** normal reg op reg operation. */
+ ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
+ /** normal reg op imm operation. */
+ ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
+ /** barrel shifter reg op (reg shift reg operation. */
+ ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier);
+ /** barrel shifter reg op (reg shift imm operation. */
+ ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate);
+} arm_binop_factory_t;
static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
- new_binop_reg_func new_reg, new_binop_imm_func new_imm)
+ const arm_binop_factory_t *factory)
{
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *op1 = get_binop_left(node);
dbg_info *dbgi = get_irn_dbg_info(node);
arm_immediate_t imm;
+ if (flags & MATCH_SKIP_NOT) {
+ if (is_Not(op1))
+ op1 = get_Not_op(op1);
+ else if (is_Not(op2))
+ op2 = get_Not_op(op2);
+ else
+ panic("cannot execute MATCH_SKIP_NOT");
+ }
if (flags & MATCH_SIZE_NEUTRAL) {
op1 = arm_skip_downconv(op1);
op2 = arm_skip_downconv(op2);
if (try_encode_as_immediate(op2, &imm)) {
ir_node *new_op1 = be_transform_node(op1);
- return new_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
+ return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
}
new_op2 = be_transform_node(op2);
- if ((flags & MATCH_COMMUTATIVE) && try_encode_as_immediate(op1, &imm)) {
- return new_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
+ if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && try_encode_as_immediate(op1, &imm)) {
+ if (flags & MATCH_REVERSE)
+ return factory[1].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
+ else
+ return factory[0].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
}
new_op1 = be_transform_node(op1);
- return new_reg(dbgi, block, new_op1, new_op2);
+ /* check if we can fold in a Mov */
+ if (is_arm_Mov(new_op2)) {
+ const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2);
+
+ switch (attr->shift_modifier) {
+ case ARM_SHF_IMM:
+ case ARM_SHF_ASR_IMM:
+ case ARM_SHF_LSL_IMM:
+ case ARM_SHF_LSR_IMM:
+ case ARM_SHF_ROR_IMM:
+ if (factory->new_binop_reg_shift_imm) {
+ ir_node *mov_op = get_irn_n(new_op2, 0);
+ return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op,
+ attr->shift_modifier, attr->shift_immediate);
+ }
+ break;
+
+ case ARM_SHF_ASR_REG:
+ case ARM_SHF_LSL_REG:
+ case ARM_SHF_LSR_REG:
+ case ARM_SHF_ROR_REG:
+ if (factory->new_binop_reg_shift_reg) {
+ ir_node *mov_op = get_irn_n(new_op2, 0);
+ ir_node *mov_sft = get_irn_n(new_op2, 1);
+ return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft,
+ attr->shift_modifier);
+ }
+ break;
+ case ARM_SHF_REG:
+ case ARM_SHF_RRX:
+ break;
+ case ARM_SHF_INVALID:
+ panic("invalid shift");
+ }
+ }
+ if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && is_arm_Mov(new_op1)) {
+ const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1);
+ int idx = flags & MATCH_REVERSE ? 1 : 0;
+
+ switch (attr->shift_modifier) {
+ ir_node *mov_op, *mov_sft;
+
+ case ARM_SHF_IMM:
+ case ARM_SHF_ASR_IMM:
+ case ARM_SHF_LSL_IMM:
+ case ARM_SHF_LSR_IMM:
+ case ARM_SHF_ROR_IMM:
+ if (factory[idx].new_binop_reg_shift_imm) {
+ mov_op = get_irn_n(new_op1, 0);
+ return factory[idx].new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op,
+ attr->shift_modifier, attr->shift_immediate);
+ }
+ break;
+
+ case ARM_SHF_ASR_REG:
+ case ARM_SHF_LSL_REG:
+ case ARM_SHF_LSR_REG:
+ case ARM_SHF_ROR_REG:
+ if (factory[idx].new_binop_reg_shift_reg) {
+ mov_op = get_irn_n(new_op1, 0);
+ mov_sft = get_irn_n(new_op1, 1);
+ return factory[idx].new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft,
+ attr->shift_modifier);
+ }
+ break;
+
+ case ARM_SHF_REG:
+ case ARM_SHF_RRX:
+ break;
+ case ARM_SHF_INVALID:
+ panic("invalid shift");
+ }
+ }
+ return factory->new_binop_reg(dbgi, block, new_op1, new_op2);
}
/**
*/
static ir_node *gen_Add(ir_node *node)
{
- ir_mode *mode = get_irn_mode(node);
+ static const arm_binop_factory_t add_factory = {
+ new_bd_arm_Add_reg,
+ new_bd_arm_Add_imm,
+ new_bd_arm_Add_reg_shift_reg,
+ new_bd_arm_Add_reg_shift_imm
+ };
+
+ ir_mode *mode = get_irn_mode(node);
if (mode_is_float(mode)) {
ir_node *block = be_transform_node(get_nodes_block(node));
}
#endif
- return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
- new_bd_arm_Add_reg, new_bd_arm_Add_imm);
+ return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory);
}
}
static ir_node *gen_And(ir_node *node)
{
- return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
- new_bd_arm_And_reg, new_bd_arm_And_imm);
+ static const arm_binop_factory_t and_factory = {
+ new_bd_arm_And_reg,
+ new_bd_arm_And_imm,
+ new_bd_arm_And_reg_shift_reg,
+ new_bd_arm_And_reg_shift_imm
+ };
+ static const arm_binop_factory_t bic_factory = {
+ new_bd_arm_Bic_reg,
+ new_bd_arm_Bic_imm,
+ new_bd_arm_Bic_reg_shift_reg,
+ new_bd_arm_Bic_reg_shift_imm
+ };
+
+ /* check for and not */
+ ir_node *left = get_And_left(node);
+ ir_node *right = get_And_right(node);
+
+ if (is_Not(left) || is_Not(right)) {
+ return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT,
+ &bic_factory);
+ }
+
+ return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory);
}
static ir_node *gen_Or(ir_node *node)
{
- return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
- new_bd_arm_Or_reg, new_bd_arm_Or_imm);
+ static const arm_binop_factory_t or_factory = {
+ new_bd_arm_Or_reg,
+ new_bd_arm_Or_imm,
+ new_bd_arm_Or_reg_shift_reg,
+ new_bd_arm_Or_reg_shift_imm
+ };
+
+ return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory);
}
static ir_node *gen_Eor(ir_node *node)
{
- return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
- new_bd_arm_Eor_reg, new_bd_arm_Eor_imm);
+ static const arm_binop_factory_t eor_factory = {
+ new_bd_arm_Eor_reg,
+ new_bd_arm_Eor_imm,
+ new_bd_arm_Eor_reg_shift_reg,
+ new_bd_arm_Eor_reg_shift_imm
+ };
+
+ return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory);
}
static ir_node *gen_Sub(ir_node *node)
{
+ static const arm_binop_factory_t sub_rsb_factory[2] = {
+ {
+ new_bd_arm_Sub_reg,
+ new_bd_arm_Sub_imm,
+ new_bd_arm_Sub_reg_shift_reg,
+ new_bd_arm_Sub_reg_shift_imm
+ },
+ {
+ new_bd_arm_Rsb_reg,
+ new_bd_arm_Rsb_imm,
+ new_bd_arm_Rsb_reg_shift_reg,
+ new_bd_arm_Rsb_reg_shift_imm
+ }
+ };
+
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *op1 = get_Sub_left(node);
ir_node *new_op1 = be_transform_node(op1);
panic("Softfloat not supported yet");
}
} else {
- return gen_int_binop(node, MATCH_SIZE_NEUTRAL,
- new_bd_arm_Sub_reg, new_bd_arm_Sub_imm);
+ return gen_int_binop(node, MATCH_SIZE_NEUTRAL | MATCH_REVERSE, sub_rsb_factory);
}
}
ir_node *new_op = be_transform_node(op);
dbg_info *dbgi = get_irn_dbg_info(node);
- /* TODO: we could do alot more here with all the Mvn variations */
+ /* check if we can fold in a Mov */
+ if (is_arm_Mov(new_op)) {
+ const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op);
+
+ switch (attr->shift_modifier) {
+ ir_node *mov_op, *mov_sft;
+
+ case ARM_SHF_IMM:
+ case ARM_SHF_ASR_IMM:
+ case ARM_SHF_LSL_IMM:
+ case ARM_SHF_LSR_IMM:
+ case ARM_SHF_ROR_IMM:
+ mov_op = get_irn_n(new_op, 0);
+ return new_bd_arm_Mvn_reg_shift_imm(dbgi, block, mov_op,
+ attr->shift_modifier, attr->shift_immediate);
+
+ case ARM_SHF_ASR_REG:
+ case ARM_SHF_LSL_REG:
+ case ARM_SHF_LSR_REG:
+ case ARM_SHF_ROR_REG:
+ mov_op = get_irn_n(new_op, 0);
+ mov_sft = get_irn_n(new_op, 1);
+ return new_bd_arm_Mvn_reg_shift_reg(dbgi, block, mov_op, mov_sft,
+ attr->shift_modifier);
+
+ case ARM_SHF_REG:
+ case ARM_SHF_RRX:
+ break;
+ case ARM_SHF_INVALID:
+ panic("invalid shift");
+ }
+ }
return new_bd_arm_Mvn_reg(dbgi, block, new_op);
}
new_op2 = be_transform_node(op2);
return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
-
- panic("FloatCmp NIY");
-#if 0
- ir_node *new_op2 = be_transform_node(op2);
- /* floating point compare */
- pn_Cmp pnc = get_Proj_proj(selector);
-
- if (pnc & pn_Cmp_Uo) {
- /* check for unordered, need cmf */
- return new_bd_arm_CmfBra(dbgi, block, new_op1, new_op2, pnc);
- }
- /* Hmm: use need cmfe */
- return new_bd_arm_CmfeBra(dbgi, block, new_op1, new_op2, pnc);
-#endif
}
assert(get_irn_mode(op2) == cmp_mode);
is_unsigned = !mode_is_signed(cmp_mode);
- /* compare with 0 can be done with Tst */
- if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) {
- new_op1 = be_transform_node(op1);
- new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
- return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false,
- is_unsigned);
- }
- if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) {
- new_op2 = be_transform_node(op2);
- new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
- return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true,
- is_unsigned);
- }
-
/* integer compare, TODO: use shifter_op in all its combinations */
new_op1 = be_transform_node(op1);
new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
new_mem, size);
}
+/**
+ * Transform builtin clz.
+ */
+static ir_node *gen_clz(ir_node *node)
+{
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ dbg_info *dbg = get_irn_dbg_info(node);
+ ir_node *op = get_irn_n(node, 1);
+ ir_node *new_op = be_transform_node(op);
+
+ /* TODO armv5 instruction, otherwise create a call */
+ return new_bd_arm_Clz(dbg, block, new_op);
+}
+
+/**
+ * Transform Builtin node.
+ */
+static ir_node *gen_Builtin(ir_node *node)
+{
+ ir_builtin_kind kind = get_Builtin_kind(node);
+
+ switch (kind) {
+ case ir_bk_trap:
+ case ir_bk_debugbreak:
+ case ir_bk_return_address:
+ case ir_bk_frame_address:
+ case ir_bk_prefetch:
+ case ir_bk_ffs:
+ break;
+ case ir_bk_clz:
+ return gen_clz(node);
+ case ir_bk_ctz:
+ case ir_bk_parity:
+ case ir_bk_popcount:
+ case ir_bk_bswap:
+ case ir_bk_outport:
+ case ir_bk_inport:
+ case ir_bk_inner_trampoline:
+ break;
+ }
+ panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
+}
+
+/**
+ * Transform Proj(Builtin) node.
+ */
+static ir_node *gen_Proj_Builtin(ir_node *proj)
+{
+ ir_node *node = get_Proj_pred(proj);
+ ir_node *new_node = be_transform_node(node);
+ ir_builtin_kind kind = get_Builtin_kind(node);
+
+ switch (kind) {
+ case ir_bk_return_address:
+ case ir_bk_frame_address:
+ case ir_bk_ffs:
+ case ir_bk_clz:
+ case ir_bk_ctz:
+ case ir_bk_parity:
+ case ir_bk_popcount:
+ case ir_bk_bswap:
+ assert(get_Proj_proj(proj) == pn_Builtin_1_result);
+ return new_node;
+ case ir_bk_trap:
+ case ir_bk_debugbreak:
+ case ir_bk_prefetch:
+ case ir_bk_outport:
+ assert(get_Proj_proj(proj) == pn_Builtin_M);
+ return new_node;
+ case ir_bk_inport:
+ case ir_bk_inner_trampoline:
+ break;
+ }
+ panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
+}
+
static ir_node *gen_Proj_Load(ir_node *node)
{
ir_node *load = get_Proj_pred(node);
ir_node *call = get_Proj_pred(get_Proj_pred(node));
ir_node *new_call = be_transform_node(call);
ir_type *function_type = get_Call_type(call);
- calling_convention_t *cconv = decide_calling_convention(function_type);
+ calling_convention_t *cconv = arm_decide_calling_convention(function_type);
const reg_or_stackslot_t *res = &cconv->results[pn];
ir_mode *mode;
int regn;
}
mode = res->reg0->reg_class->mode;
- free_calling_convention(cconv);
+ arm_free_calling_convention(cconv);
return new_r_Proj(new_call, mode, regn);
}
}
/* FALLTHROUGH */
}
+ case iro_Builtin:
+ return gen_Proj_Builtin(node);
default:
panic("code selection didn't expect Proj after %+F\n", pred);
}
ir_node *new_mem = be_transform_node(mem);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_type *type = get_Call_type(node);
- calling_convention_t *cconv = decide_calling_convention(type);
+ calling_convention_t *cconv = arm_decide_calling_convention(type);
int n_params = get_Call_n_params(node);
int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
/* max inputs: memory, callee, register arguments */
pmap_insert(node_to_stack, node, incsp);
}
- set_arm_in_req_all(res, in_req);
+ arch_set_in_register_reqs(res, in_req);
/* create output register reqs */
arch_set_out_register_req(res, 0, arch_no_register_req);
/* copy pinned attribute */
set_irn_pinned(res, get_irn_pinned(node));
- free_calling_convention(cconv);
+ arm_free_calling_convention(cconv);
return res;
}
be_set_transform_function(op_Sub, gen_Sub);
be_set_transform_function(op_SymConst, gen_SymConst);
be_set_transform_function(op_Unknown, gen_Unknown);
+ be_set_transform_function(op_Builtin, gen_Builtin);
}
/**
abihelper = be_abihelper_prepare(irg);
be_collect_stacknodes(abihelper);
assert(cconv == NULL);
- cconv = decide_calling_convention(get_entity_type(entity));
+ cconv = arm_decide_calling_convention(get_entity_type(entity));
create_stacklayout(irg);
be_transform_graph(cg->irg, NULL);
be_abihelper_finish(abihelper);
abihelper = NULL;
- free_calling_convention(cconv);
+ arm_free_calling_convention(cconv);
cconv = NULL;
frame_type = get_irg_frame_type(irg);
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