# the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
$arch = "arm";
-
-$comment_string = '/*';
+$new_emit_syntax = 1;
# the number of additional opcodes you want to register
#$additional_opcodes = 0;
{ "name" => "r10", "type" => 2 },
{ "name" => "r11", "type" => 2 },
{ "name" => "r12", "type" => 6 }, # reserved for linker
- { "name" => "sp", "type" => 6 }, # this is our stack pointer
- { "name" => "lr", "type" => 3 }, # this is our return address
- { "name" => "pc", "type" => 6 }, # this is our program counter
+ { "name" => "sp", "realname" => "r13", "type" => 6 }, # this is our stack pointer
+ { "name" => "lr", "realname" => "r14", "type" => 3 }, # this is our return address
+ { "name" => "pc", "realname" => "r15", "type" => 6 }, # this is our program counter
{ "mode" => "mode_Iu" }
],
"fpa" => [
]
); # %reg_classes
+%emit_templates = (
+ M => "${arch}_emit_mode(env, node);",
+ X => "${arch}_emit_shift(env, node);",
+ S0 => "${arch}_emit_source_register(env, node, 0);",
+ S1 => "${arch}_emit_source_register(env, node, 1);",
+ S2 => "${arch}_emit_source_register(env, node, 2);",
+ S3 => "${arch}_emit_source_register(env, node, 3);",
+ S4 => "${arch}_emit_source_register(env, node, 4);",
+ D0 => "${arch}_emit_dest_register(env, node, 0);",
+ D1 => "${arch}_emit_dest_register(env, node, 1);",
+ D2 => "${arch}_emit_dest_register(env, node, 2);",
+ C => "${arch}_emit_immediate(env, node);",
+ O => "${arch}_emit_offset(env, mode);",
+);
+
#--------------------------------------------------#
# _ #
# (_) #
# |_| #
#--------------------------------------------------#
+$default_cmp_attr = "NULL";
+
%nodes = (
#-----------------------------------------------------------------#
"init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
"cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. add %D1, %S1, %S2%X0 /* Add(%S1, %S2) -> %D1, (%A1, %A2) */'
+ "emit" => '. add %D0, %S0, %S1%X'
},
"Add_i" => {
"init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
"cmp_attr" => 'return attr_a->value != attr_b->value;',
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. add %D1, %S1, %C /* Add(%C, %S1) -> %D1, (%A1, const) */'
+ "emit" => '. add %D0, %S0, %C'
},
"Mul" => {
"irn_flags" => "R",
"comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "!in_r1" ] },
- "emit" =>'. mul %D1, %S1, %S2 /* Mul(%S1, %S2) -> %D1, (%A1, %A2) */'
+ "emit" =>'. mul %D0, %S0, %S1'
+},
+
+"Smull" => {
+ #"op_flags" => "C",
+ "irn_flags" => "R",
+ "comment" => "construct signed 64bit Mul: Mul(a, b) = Mul(b, a) = a * b",
+ "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp", "gp" ] },
+ "emit" =>'. smull %D0, %D1, %S0, %S1',
+ "outs" => [ "low", "high" ],
+},
+
+"Umull" => {
+ #"op_flags" => "C",
+ "irn_flags" => "R",
+ "comment" => "construct unsigned 64bit Mul: Mul(a, b) = Mul(b, a) = a * b",
+ "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp", "gp" ] },
+ "emit" =>'. umull %D0, %D1, %S0, %S1',
+ "outs" => [ "low", "high" ],
},
"Mla" => {
"irn_flags" => "R",
"comment" => "construct Mla: Mla(a, b, c) = a * b + c",
"reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in_r1" ] },
- "emit" =>'. mla %D1, %S1, %S2, %S3 /* Mla(%S1, %S2, %S3) -> %D1, (%A1, %A2, %A3) */'
+ "emit" =>'. mla %D0, %S0, %S1, %S2'
},
"And" => {
"init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
"cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. and %D1, %S1, %S2%X0 /* And(%S1, %S2) -> %D1, (%A1, %A2) */'
+ "emit" => '. and %D0, %S0, %S1%X'
},
"And_i" => {
"attr" => "tarval *tv",
"init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. and %D1, %S1, %C /* And(%C, %S1) -> %D1, (%A1, const) */',
+ "emit" => '. and %D0, %S0, %C',
"cmp_attr" => 'return attr_a->value != attr_b->value;'
},
"init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
"cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. orr %D1, %S1, %S2%X0 /* Or(%S1, %S2) -> %D1, (%A1, %A2) */'
+ "emit" => '. orr %D0, %S0, %S1%X'
},
"Or_i" => {
"init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
"cmp_attr" => 'return attr_a->value != attr_b->value;',
- "emit" => '. orr %D1, %S1, %C /* Or(%C, %S1) -> %D1, (%A1, const) */'
+ "emit" => '. orr %D0, %S0, %C'
},
"Eor" => {
"init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
"cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. eor %D1, %S1, %S2%X0 /* Xor(%S1, %S2) -> %D1, (%A1, %A2) */'
+ "emit" => '. eor %D0, %S0, %S1%X'
},
"Eor_i" => {
"init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
"cmp_attr" => 'return attr_a->value != attr_b->value;',
- "emit" => '. eor %D1, %S1, %C /* Xor(%C, %S1) -> %D1, (%A1, const) */'
+ "emit" => '. eor %D0, %S0, %C'
},
# not commutative operations
"init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
"cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. bic %D1, %S1, %S2%X0 /* AndNot(%S1, %S2) -> %D1, (%A1, %A2) */'
+ "emit" => '. bic %D0, %S0, %S1%X'
},
"Bic_i" => {
"attr" => "tarval *tv",
"init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. bic %D1, %S1, %C /* AndNot(%C, %S1) -> %D1, (%A1, const) */',
+ "emit" => '. bic %D0, %S0, %C',
"cmp_attr" => 'return attr_a->value != attr_b->value;'
},
"init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
"cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. sub %D1, %S1, %S2%X0 /* Sub(%S1, %S2) -> %D1, (%A1, %A2) */'
+ "emit" => '. sub %D0, %S0, %S1%X'
},
"Sub_i" => {
"init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
"cmp_attr" => 'return attr_a->value != attr_b->value;',
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. sub %D1, %S1, %C /* Sub(%S1, %C) -> %D1, (%A1, const) */',
+ "emit" => '. sub %D0, %S0, %C',
},
"Rsb" => {
"init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
"cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. rsb %D1, %S1, %S2%X0 /* Rsb(%S1, %S2) -> %D1, (%A1, %A2) */'
+ "emit" => '. rsb %D0, %S0, %S1%X'
},
"Rsb_i" => {
"attr" => "tarval *tv",
"init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. rsb %D1, %S1, %C /* Rsb(%S1, %C) -> %D1, (%A1, const) */',
+ "emit" => '. rsb %D0, %S0, %C',
"cmp_attr" => 'return attr_a->value != attr_b->value;'
},
"irn_flags" => "R",
"comment" => "construct Shl: Shl(a, b) = a << b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. mov %D1, %S1, LSL %S2\t/* Shl(%S1, %S2) -> %D1, (%A1, %A2) */'
+ "emit" => '. mov %D0, %S0, lsl %S1'
},
"Shr" => {
"irn_flags" => "R",
"comment" => "construct Shr: Shr(a, b) = a >> b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
- "emit" => '. mov %D1, %S1, LSR %S2 /* Shr(%S1, %S2) -> %D1, (%A1, %A2) */'
+ "emit" => '. mov %D0, %S0, lsr %S1'
},
"Shrs" => {
"irn_flags" => "R",
"comment" => "construct Shrs: Shrs(a, b) = a >> b",
"reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
- "emit" => '. mov %D1, %S1, ASR %S2\t\t /* Shrs(%S1, %S2) -> %D1, (%A1, %A2) */'
+ "emit" => '. mov %D0, %S0, asr %S1'
},
#"RotR" => {
# "irn_flags" => "R",
# "comment" => "construct RotR: RotR(a, b) = a ROTR b",
# "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
-# "emit" => '. mov %D1, %S1, ROR %S2 /* RotR(%S1, %S2) -> %D1, (%A1, %A2) */'
-## "emit" => '. ror %S1, %S2, %D1 /* RotR(%S1, %S2) -> %D1, (%A1, %A2) */'
+# "emit" => '. mov %D0, %S0, ror %S1 /* RotR(%S0, %S1) -> %D0, (%A1, %A2) */'
+## "emit" => '. ror %S0, %S1, %D0'
#},
#"RotL" => {
# "irn_flags" => "R",
# "comment" => "construct RotL: RotL(a, b) = a ROTL b",
# "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
-# "emit" => '. rol %S1, %S2, %D1 /* RotL(%S1, %S2) -> %D1, (%A1, %A2) */'
+# "emit" => '. rol %S0, %S1, %D0'
#},
#"RotL_i" => {
# "irn_flags" => "R",
# "comment" => "construct RotL: RotL(a, const) = a ROTL const",
# "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
-# "emit" => '. rol %S1, %C, %D1 /* RotL(%S1, %C) -> %D1, (%A1, const) */'
+# "emit" => '. rol %S0, %C, %D0'
#},
"Mov" => {
"init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
"cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. mov %D1, %S1%X0\t/* Mov(%S1%X0) -> %D1, (%A1) */'
+ "emit" => '. mov %D0, %S0%X'
},
"Mov_i" => {
"attr" => "tarval *tv",
"init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
"reg_req" => { "out" => [ "gp" ] },
- "emit" => '. mov %D1, %C /* Mov Const into register */',
+ "emit" => '. mov %D0, %C',
"cmp_attr" => 'return attr_a->value != attr_b->value;'
},
"init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
"cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. mvn %D1, %S1%X0 /* ~(%S1%X0) -> %D1, (%A1) */'
+ "emit" => '. mvn %D0, %S0%X'
},
"Mvn_i" => {
"init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
"cmp_attr" => 'return attr_a->value != attr_b->value;',
"reg_req" => { "out" => [ "gp" ] },
- "emit" => '. mvn %D1, %C /* Mov ~Const into register */',
+ "emit" => '. mvn %D0, %C',
},
"Abs" => {
"comment" => "construct Abs: Abs(a) = |a|",
"reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
"emit" =>
-'. movs %S1, %S1, #0 /* set condition flag */\n
-. rsbmi %D1, %S1, #0 /* Neg(%S1) -> %D1, (%A1) */'
+'. movs %S0, %S0, #0
+. rsbmi %D0, %S0, #0'
},
# other operations
"EmptyReg" => {
"op_flags" => "c",
"irn_flags" => "R",
- "comment" => "just to get an empty register for calculations",
+ "comment" => "allocate an empty register for calculations",
"reg_req" => { "out" => [ "gp" ] },
- "emit" => '. /* %D1 now available for calculations */',
+ "emit" => '. /* %D0 now available for calculations */',
"cmp_attr" => 'return 1;'
},
"op_flags" => "c",
"irn_flags" => "R",
"comment" => "represents a symbolic constant",
- "attr" => "const char *label",
- "init_attr" => ' attr->symconst_label = label;',
+ "attr" => "ident *id",
+ "init_attr" => ' attr->symconst_id = id;',
"reg_req" => { "out" => [ "gp" ] },
-# "emit" => '. ldr %D1, %C /* Mov Const into register */',
"cmp_attr" =>
' /* should be identical but ...*/
- return strcmp(attr_a->symconst_label, attr_b->symconst_label);'
+ return attr_a->symconst_id == attr_b->symconst_id;'
},
"CondJmp" => {
"state" => "exc_pinned",
"comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
"reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp", "none" ] },
- "emit" => '. ldr %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */',
+ "emit" => '. ldr %D0, [%S0, #0]',
"outs" => [ "res", "M" ],
},
"state" => "exc_pinned",
"comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
"reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp", "none" ] },
- "emit" => '. ldrb %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */',
+ "emit" => '. ldrb %D0, [%S0, #0]',
"outs" => [ "res", "M" ],
},
"state" => "exc_pinned",
"comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
"reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp", "none" ] },
- "emit" => '. ldrsb %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */',
+ "emit" => '. ldrsb %D0, [%S0, #0]',
"outs" => [ "res", "M" ],
},
"state" => "exc_pinned",
"comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
"reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp", "none" ] },
- "emit" => '. ldrh %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */',
+ "emit" => '. ldrh %D0, [%S0, #0]',
"outs" => [ "res", "M" ],
},
"state" => "exc_pinned",
"comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
"reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp", "none" ] },
- "emit" => '. ldrsh %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */',
+ "emit" => '. ldrsh %D0, [%S0, #0]',
"outs" => [ "res", "M" ],
},
"irn_flags" => "R",
"state" => "exc_pinned",
"comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- "reg_req" => { "in" => [ "gp", "gp", "none" ] },
- "emit" => '. strb %S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */',
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "none" ] },
+ "emit" => '. strb %S1, [%S0, #0]',
"outs" => [ "M" ],
},
"irn_flags" => "R",
"state" => "exc_pinned",
"comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- "reg_req" => { "in" => [ "gp", "gp", "none" ] },
- "emit" => '. strsb %S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */',
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "none" ] },
+ "emit" => '. strsb %S1, [%S0, #0]',
"outs" => [ "M" ],
},
"irn_flags" => "R",
"state" => "exc_pinned",
"comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- "reg_req" => { "in" => [ "gp", "gp", "none" ] },
- "emit" => '. strh %S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */',
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], out => [ "none" ] },
+ "emit" => '. strh %S1, [%S0, #0]',
"outs" => [ "M" ],
},
"irn_flags" => "R",
"state" => "exc_pinned",
"comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- "reg_req" => { "in" => [ "gp", "gp", "none" ] },
- "emit" => '. strsh%S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */',
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], out => [ "none" ] },
+ "emit" => '. strhs %S1, [%S0, #0]',
"outs" => [ "M" ],
},
"irn_flags" => "R",
"state" => "exc_pinned",
"comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- "reg_req" => { "in" => [ "gp", "gp", "none" ] },
- "emit" => '. str %S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */',
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], out => [ "none" ] },
+ "emit" => '. str %S1, [%S0, #0]',
"outs" => [ "M" ],
},
"state" => "exc_pinned",
"comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
"reg_req" => { "in" => [ "sp", "gp", "gp", "gp", "gp", "none" ], "out" => [ "gp", "none" ] },
- "emit" => '. stmfd %S1!, {%S2, %S3, %S4, %S5} /* Store multiple on Stack*/',
+ "emit" => '. stmfd %S0!, {%S1, %S2, %S3, %S4}',
"outs" => [ "ptr", "M" ],
},
"state" => "exc_pinned",
"comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
"reg_req" => { "in" => [ "sp", "none" ], "out" => [ "gp", "gp", "gp", "none" ] },
- "emit" => '. ldmfd %S1, {%D1, %D2, %D3} /* Load multiple from Stack */',
+ "emit" => '. ldmfd %S0, {%D0, %D1, %D2}',
"outs" => [ "res0", "res1", "res2", "M" ],
},
"irn_flags" => "R",
"comment" => "construct FPA Add: Add(a, b) = Add(b, a) = a + b",
"reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
- "emit" => '. adf%M %D1, %S1, %S2 /* FPA Add(%S1, %S2) -> %D1 */',
+ "emit" => '. adf%M %D0, %S0, %S1',
},
"fpaMul" => {
"op_flags" => "C",
"comment" => "construct FPA Mul: Mul(a, b) = Mul(b, a) = a * b",
"reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
- "emit" =>'. muf%M %D1, %S1, %S2 /* FPA Mul(%S1, %S2) -> %D1 */',
+ "emit" =>'. muf%M %D0, %S0, %S1',
},
"fpaFMul" => {
"op_flags" => "C",
"comment" => "construct FPA Fast Mul: Mul(a, b) = Mul(b, a) = a * b",
"reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
- "emit" =>'. fml%M %D1, %S1, %S2 /* FPA Fast Mul(%S1, %S2) -> %D1 */',
+ "emit" =>'. fml%M %D0, %S0, %S1',
},
"fpaMax" => {
"irn_flags" => "R",
"comment" => "construct FPA Max: Max(a, b) = Max(b, a) = a > b ? a : b",
"reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
- "emit" =>'. fmax %S1, %S2, %D1 /* FPA Max(%S1, %S2) -> %D1 */',
+ "emit" =>'. fmax %S0, %S1, %D0',
},
"fpaMin" => {
"irn_flags" => "R",
"comment" => "construct FPA Min: Min(a, b) = Min(b, a) = a < b ? a : b",
"reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
- "emit" =>'. fmin %S1, %S2, %D1 /* FPA Min(%S1, %S2) -> %D1 */',
+ "emit" =>'. fmin %S0, %S1, %D0',
},
# not commutative operations
"irn_flags" => "R",
"comment" => "construct FPA Sub: Sub(a, b) = a - b",
"reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
- "emit" => '. suf%M %D1, %S1, %S2 /* FPA Sub(%S1, %S2) -> %D1 */'
+ "emit" => '. suf%M %D0, %S0, %S1'
},
"fpaRsb" => {
"irn_flags" => "R",
"comment" => "construct FPA reverse Sub: Sub(a, b) = b - a",
"reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
- "emit" => '. rsf%M %D1, %S1, %S2 /* FPA reverse Sub(%S1, %S2) -> %D1 */'
+ "emit" => '. rsf%M %D0, %S0, %S1'
},
"fpaDiv" => {
"comment" => "construct FPA Div: Div(a, b) = a / b",
"reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
- "emit" =>'. dvf%M %D1, %S1, %S2 /* FPA Div(%S1, %S2) -> %D1 */',
+ "emit" =>'. dvf%M %D0, %S0, %S1',
},
"fpaRdv" => {
"comment" => "construct FPA reverse Div: Div(a, b) = b / a",
"reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
- "emit" =>'. rdf%M %D1, %S1, %S2 /* FPA reverse Div(%S1, %S2) -> %D1 */',
+ "emit" =>'. rdf%M %D0, %S0, %S1',
},
"fpaFDiv" => {
"comment" => "construct FPA Fast Div: Div(a, b) = a / b",
"reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
- "emit" =>'. fdv%M %D1, %S1, %S2 /* FPA Fast Div(%S1, %S2) -> %D1 */',
+ "emit" =>'. fdv%M %D0, %S0, %S1',
},
"fpaFRdv" => {
"comment" => "construct FPA Fast reverse Div: Div(a, b) = b / a",
"reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
- "emit" =>'. frd%M %D1, %S1, %S2 /* FPA Fast reverse Div(%S1, %S2) -> %D1 */',
+ "emit" =>'. frd%M %D0, %S0, %S1',
},
"fpaMov" => {
"irn_flags" => "R",
"comment" => "construct FPA Move: b = a",
"reg_req" => { "in" => [ "fpa" ], "out" => [ "fpa" ] },
- "emit" => '. mvf%M %S1, %D1 /* FPA Mov %S1 -> %D1 */',
+ "emit" => '. mvf%M %S0, %D0',
},
"fpaMnv" => {
"irn_flags" => "R",
"comment" => "construct FPA Move Negated: b = -a",
"reg_req" => { "in" => [ "fpa" ], "out" => [ "fpa" ] },
- "emit" => '. mnf%M %S1, %D1 /* FPA Neg(%S1) -> %D1 */',
+ "emit" => '. mnf%M %S0, %D0',
},
"fpaAbs" => {
"irn_flags" => "R",
"comment" => "construct FPA Absolute value: fAbsd(a) = |a|",
"reg_req" => { "in" => [ "fpa" ], "out" => [ "fpa" ] },
- "emit" => '. abs%M %D1, %S1 /* FPA Abs(%S1) -> %D1 */',
+ "emit" => '. abs%M %D0, %S0',
},
# other operations
"attr" => "tarval *val",
"init_attr" => 'attr->value = val;',
"reg_req" => { "out" => [ "fpa" ] },
- "emit" => '. fmov %D1, %C /* Mov fConst into register */',
+ "emit" => '. fmov %D0, %C',
"cmp_attr" => 'return attr_a->value != attr_b->value;',
},
"irn_flags" => "R",
"comment" => "construct a FPA integer->float conversion",
"reg_req" => { "in" => ["gp"], "out" => [ "fpa" ] },
- "emit" => '. flt%M %D1, %S1 /* convert int to fp */',
+ "emit" => '. flt%M %D0, %S0',
},
"fpaFix" => {
"irn_flags" => "R",
"comment" => "construct a FPA float->integer conversion",
"reg_req" => { "in" => ["fpa"], "out" => [ "gp" ] },
- "emit" => '. fix %D1, %S1 /* convert fp to int */',
+ "emit" => '. fix %D0, %S0',
},
# Load / Store
"attr" => "ir_mode *op_mode",
"init_attr" => "attr->op_mode = op_mode;",
"reg_req" => { "in" => [ "gp", "none" ], "out" => [ "fpa", "none" ] },
- "emit" => '. ldf%M %D1, [%S1, #0] /* Load((%S1)) -> %D1 */',
+ "emit" => '. ldf%M %D0, [%S0, #0]',
"outs" => [ "res", "M" ],
},
"comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
"attr" => "ir_mode *op_mode",
"init_attr" => "attr->op_mode = op_mode;",
- "reg_req" => { "in" => [ "gp", "fpa", "none" ] },
- "emit" => '. stf%M [%S2, #0], %S1 /* Store(%S2) -> (%S1), (%A1, %A2) */',
+ "reg_req" => { "in" => [ "gp", "fpa", "none" ], "out" => [ "none" ] },
+ "emit" => '. stf%M [%S1, #0], %S0',
"outs" => [ "M" ],
},
"irn_flags" => "R",
"state" => "exc_pinned",
"comment" => "construct fp double to 2 gp register transfer",
- "reg_req" => { "in" => [ "fpa", "none" ], "out" => [ "gp", "gp" ] },
+ "reg_req" => { "in" => [ "fpa", "none" ], "out" => [ "gp", "gp", "none" ] },
"outs" => [ "low", "high", "M" ],
},