Teach new_tarval_from_str_int() to parse binary numbers: 0[bB][01]+.

[libfirm] / ir / be / arm / arm_spec.pl

diff --git a/ir/be/arm/arm_spec.pl b/ir/be/arm/arm_spec.pl
index 471f7d3..3b37e23 100644 (file)
--- a/ir/be/arm/arm_spec.pl
+++ b/ir/be/arm/arm_spec.pl
@@ -1,7 +1,5 @@
-# Creation: 2006/02/13
 # Arm Architecure Specification
 # Author: Matthias Braun, Michael Beck, Oliver Richter, Tobias Gneist
-# $Id$
 
 $arch = "arm";
 
@@ -10,38 +8,38 @@ $arch = "arm";
 #
 $mode_gp    = "mode_Iu";
 $mode_flags = "mode_Bu";
-$mode_fp    = "mode_E";
+$mode_fp    = "mode_F";
 
 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
 %reg_classes = (
        gp => [
-               { name => "r0" },
-               { name => "r1" },
-               { name => "r2" },
-               { name => "r3" },
-               { name => "r4" },
-               { name => "r5" },
-               { name => "r6" },
-               { name => "r7" },
-               { name => "r8" },
-               { name => "r9" },
-               { name => "r10" },
-               { name => "r11" },
-               { name => "r12" },
-               { name => "sp" },
-               { name => "lr" },
-               { name => "pc" },
+               { name => "r0",  dwarf => 0 },
+               { name => "r1",  dwarf => 1 },
+               { name => "r2",  dwarf => 2 },
+               { name => "r3",  dwarf => 3 },
+               { name => "r4",  dwarf => 4 },
+               { name => "r5",  dwarf => 5 },
+               { name => "r6",  dwarf => 6 },
+               { name => "r7",  dwarf => 7 },
+               { name => "r8",  dwarf => 8 },
+               { name => "r9",  dwarf => 9 },
+               { name => "r10", dwarf => 10 },
+               { name => "r11", dwarf => 11 },
+               { name => "r12", dwarf => 12 },
+               { name => "sp",  dwarf => 13 },
+               { name => "lr",  dwarf => 14 },
+               { name => "pc",  dwarf => 15 },
                { mode => $mode_gp }
        ],
        fpa => [
-               { name => "f0" },
-               { name => "f1" },
-               { name => "f2" },
-               { name => "f3" },
-               { name => "f4" },
-               { name => "f5" },
-               { name => "f6" },
-               { name => "f7" },
+               { name => "f0", dwarf => 96 },
+               { name => "f1", dwarf => 97 },
+               { name => "f2", dwarf => 98 },
+               { name => "f3", dwarf => 99 },
+               { name => "f4", dwarf => 100 },
+               { name => "f5", dwarf => 101 },
+               { name => "f6", dwarf => 102 },
+               { name => "f7", dwarf => 103 },
                { mode => $mode_fp }
        ],
        flags => [
@@ -72,25 +70,25 @@ $default_attr_type = "arm_attr_t";
 $default_copy_attr = "arm_copy_attr";
 
 %init_attr = (
-       arm_attr_t           => "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);",
+       arm_attr_t           => "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);",
        arm_SymConst_attr_t  =>
-               "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);\n".
+               "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n".
                "\tinit_arm_SymConst_attributes(res, entity, symconst_offset);",
-       arm_CondJmp_attr_t   => "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);",
-       arm_SwitchJmp_attr_t => "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);",
-       arm_fConst_attr_t    => "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);",
+       arm_CondJmp_attr_t   => "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);",
+       arm_SwitchJmp_attr_t => "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);",
+       arm_fConst_attr_t    => "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);",
        arm_load_store_attr_t =>
-               "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);\n".
+               "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n".
                "\tinit_arm_load_store_attributes(res, ls_mode, entity, entity_sign, offset, is_frame_entity);",
        arm_shifter_operand_t =>
-               "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);\n",
+               "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n",
        arm_cmp_attr_t =>
-               "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);\n",
+               "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n",
        arm_farith_attr_t =>
-               "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);\n".
+               "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n".
                "\tinit_arm_farith_attributes(res, op_mode);",
        arm_CopyB_attr_t =>
-               "\tinit_arm_attributes(res, flags, in_reqs, exec_units, n_res);\n".
+               "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n".
                "\tinit_arm_CopyB_attributes(res, size);",
 );
 
@@ -312,7 +310,7 @@ LinkMovPC => {
        attr_type    => "arm_shifter_operand_t",
        attr         => "arm_shift_modifier_t shift_modifier, unsigned char immediate_value, unsigned char immediate_rot",
        custominit   => "init_arm_shifter_operand(res, immediate_value, shift_modifier, immediate_rot);\n".
-                       "\tarch_irn_add_flags(res, arch_irn_flags_modify_flags);",
+                       "\tarch_add_irn_flags(res, arch_irn_flags_modify_flags);",
        emit         => ". mov lr, pc\n".
                        ". mov pc, %SO",
 },
@@ -325,7 +323,7 @@ LinkLdrPC => {
        out_arity    => "variable",
        attr_type    => "arm_load_store_attr_t",
        attr         => "ir_mode *ls_mode, ir_entity *entity, int entity_sign, long offset, bool is_frame_entity",
-       custominit   => "arch_irn_add_flags(res, arch_irn_flags_modify_flags);",
+       custominit   => "arch_add_irn_flags(res, arch_irn_flags_modify_flags);",
        emit         => ". mov lr, pc\n".
                        ". ldr pc, %SO",
 },
@@ -336,7 +334,7 @@ Bl => {
        out_arity  => "variable",
        attr_type  => "arm_SymConst_attr_t",
        attr       => "ir_entity *entity, int symconst_offset",
-       custominit => "arch_irn_add_flags(res, arch_irn_flags_modify_flags);",
+       custominit => "arch_add_irn_flags(res, arch_irn_flags_modify_flags);",
        emit       => '. bl %SC',
 },
 
@@ -351,7 +349,6 @@ EmptyReg => {
 },
 
 CopyB => {
-       op_flags  => [ "fragile" ],
        state     => "pinned",
        attr      => "unsigned size",
        attr_type => "arm_CopyB_attr_t",
@@ -416,16 +413,15 @@ SwitchJmp => {
        op_flags  => [ "labeled", "cfopcode", "forking" ],
        state     => "pinned",
        mode      => "mode_T",
-       attr      => "int n_projs, long def_proj_num",
-       init_attr => "\tset_arm_SwitchJmp_n_projs(res, n_projs);\n".
-                    "\tset_arm_SwitchJmp_default_proj_num(res, def_proj_num);\n".
-                    "\tinfo->out_infos = NULL;",
+       attr      => "const ir_switch_table *table",
+       init_attr => "init_arm_SwitchJmp_attributes(res, table);",
        reg_req   => { in => [ "gp" ], out => [ "none" ] },
+       out_arity => "variable",
        attr_type => "arm_SwitchJmp_attr_t",
 },
 
 Ldr => {
-       op_flags  => [ "labeled", "fragile" ],
+       op_flags  => [ "labeled" ],
        state     => "exc_pinned",
        ins       => [ "ptr", "mem" ],
        outs      => [ "res", "M" ],
@@ -436,7 +432,7 @@ Ldr => {
 },
 
 Str => {
-       op_flags  => [ "labeled", "fragile" ],
+       op_flags  => [ "labeled" ],
        state     => "exc_pinned",
        ins       => [ "ptr", "val", "mem" ],
        outs      => [ "M" ],
@@ -448,7 +444,7 @@ Str => {
 },
 
 StoreStackM4Inc => {
-       op_flags  => [ "labeled", "fragile" ],
+       op_flags  => [ "labeled" ],
        irn_flags => [ "rematerializable" ],
        state     => "exc_pinned",
        reg_req   => { in => [ "sp", "gp", "gp", "gp", "gp", "none" ], out => [ "sp:I|S", "none" ] },
@@ -457,7 +453,7 @@ StoreStackM4Inc => {
 },
 
 LoadStackM3Epilogue => {
-       op_flags  => [ "labeled", "fragile" ],
+       op_flags  => [ "labeled" ],
        irn_flags => [ "rematerializable" ],
        state     => "exc_pinned",
        reg_req   => { in => [ "sp", "none" ], out => [ "r11:I", "sp:I|S", "pc:I", "none" ] },
@@ -532,7 +528,7 @@ Cmfe => {
 },
 
 Ldf => {
-       op_flags  => [ "labeled", "fragile" ],
+       op_flags  => [ "labeled" ],
        state     => "exc_pinned",
        ins       => [ "ptr", "mem" ],
        outs      => [ "res", "M" ],
@@ -543,7 +539,7 @@ Ldf => {
 },
 
 Stf => {
-       op_flags  => [ "labeled", "fragile" ],
+       op_flags  => [ "labeled" ],
        state     => "exc_pinned",
        ins       => [ "ptr", "val", "mem" ],
        outs      => [ "M" ],