change backends to produce 1 big array with all registers

[libfirm] / ir / be / arm / arm_optimize.c

diff --git a/ir/be/arm/arm_optimize.c b/ir/be/arm/arm_optimize.c
index fd4e0eb..aa57547 100644 (file)
--- a/ir/be/arm/arm_optimize.c
+++ b/ir/be/arm/arm_optimize.c
@@ -21,7 +21,7 @@
  * @file
  * @brief       Implements several optimizations for ARM.
  * @author      Michael Beck
- * @version     $Id: $
+ * @version     $Id$
  */
 #include "config.h"
 
@@ -40,8 +40,6 @@
 #include "arm_nodes_attr.h"
 #include "arm_new_nodes.h"
 
-static arm_code_gen_t  *cg;
-
 static unsigned arm_ror(unsigned v, unsigned ror)
 {
        return (v << (32 - ror)) | (v >> ror);
@@ -77,7 +75,7 @@ void arm_gen_vals_from_word(unsigned int value, arm_vals *result)
 
                value  >>= 8;
                initial += 8;
-       } while(value != 0);
+       } while (value != 0);
 }
 
 /**
@@ -123,7 +121,7 @@ static void peephole_be_IncSP(ir_node *node)
        block = get_nodes_block(node);
        for (cnt = 1; cnt < v.ops; ++cnt) {
                int value = sign * arm_ror(v.values[cnt], v.rors[cnt]);
-               ir_node *next = be_new_IncSP(&arm_gp_regs[REG_SP], block, node,
+               ir_node *next = be_new_IncSP(&arm_registers[REG_SP], block, node,
                                             value, 1);
                sched_add_after(node, next);
                node = next;
@@ -152,13 +150,13 @@ static ir_node *gen_ptr_add(ir_node *node, ir_node *frame, arm_vals *v)
        ir_node *ptr;
 
        ptr = new_bd_arm_Add_imm(dbgi, block, frame, v->values[0], v->rors[0]);
-       arch_set_irn_register(ptr, &arm_gp_regs[REG_R12]);
+       arch_set_irn_register(ptr, &arm_registers[REG_R12]);
        sched_add_before(node, ptr);
 
        for (cnt = 1; cnt < v->ops; ++cnt) {
                ir_node *next = new_bd_arm_Add_imm(dbgi, block, ptr, v->values[cnt],
                                                   v->rors[cnt]);
-               arch_set_irn_register(next, &arm_gp_regs[REG_R12]);
+               arch_set_irn_register(next, &arm_registers[REG_R12]);
                sched_add_before(node, next);
                ptr = next;
        }
@@ -176,13 +174,13 @@ static ir_node *gen_ptr_sub(ir_node *node, ir_node *frame, arm_vals *v)
        ir_node *ptr;
 
        ptr = new_bd_arm_Sub_imm(dbgi, block, frame, v->values[0], v->rors[0]);
-       arch_set_irn_register(ptr, &arm_gp_regs[REG_R12]);
+       arch_set_irn_register(ptr, &arm_registers[REG_R12]);
        sched_add_before(node, ptr);
 
        for (cnt = 1; cnt < v->ops; ++cnt) {
                ir_node *next = new_bd_arm_Sub_imm(dbgi, block, ptr, v->values[cnt],
                                                   v->rors[cnt]);
-               arch_set_irn_register(next, &arm_gp_regs[REG_R12]);
+               arch_set_irn_register(next, &arm_registers[REG_R12]);
                sched_add_before(node, next);
                ptr = next;
        }
@@ -267,10 +265,8 @@ static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
 }
 
 /* Perform peephole-optimizations. */
-void arm_peephole_optimization(arm_code_gen_t *new_cg)
+void arm_peephole_optimization(ir_graph *irg)
 {
-       cg = new_cg;
-
        /* register peephole optimizations */
        clear_irp_opcodes_generic_func();
        register_peephole_optimisation(op_be_IncSP,      peephole_be_IncSP);
@@ -278,5 +274,5 @@ void arm_peephole_optimization(arm_code_gen_t *new_cg)
        register_peephole_optimisation(op_arm_Ldr,       peephole_arm_Str_Ldr);
        register_peephole_optimisation(op_arm_FrameAddr, peephole_arm_FrameAddr);
 
-       be_peephole_opt(cg->birg);
+       be_peephole_opt(irg);
 }