- implemented ia32 inport, outport for ir_bk_(in|out)port

[libfirm] / ir / be / arm / arm_optimize.c

diff --git a/ir/be/arm/arm_optimize.c b/ir/be/arm/arm_optimize.c
index 19dc8f3..883c03b 100644 (file)
--- a/ir/be/arm/arm_optimize.c
+++ b/ir/be/arm/arm_optimize.c
@@ -23,9 +23,7 @@
  * @author      Michael Beck
  * @version     $Id: $
  */
-#ifdef HAVE_CONFIG_H
 #include "config.h"
-#endif
 
 #include "irgmod.h"
 #include "ircons.h"
@@ -39,7 +37,6 @@
 #include "gen_arm_regalloc_if.h"
 #include "gen_arm_new_nodes.h"
 
-static const arch_env_t *arch_env;
 static arm_code_gen_t  *cg;
 
 /** Execute ARM ROL. */
@@ -152,20 +149,19 @@ static void peephole_be_IncSP(ir_node *node) {
  */
 static ir_node *gen_ptr_add(ir_node *node, ir_node *frame, arm_vals *v)
 {
-       ir_graph *irg   = current_ir_graph;
        dbg_info *dbg   = get_irn_dbg_info(node);
        ir_node  *block = get_nodes_block(node);
        int     cnt;
        ir_node *ptr;
 
-       ptr = new_rd_arm_Add_i(dbg, irg, block, frame, mode_Iu, arm_encode_imm_w_shift(v->shifts[0], v->values[0]));
-       arch_set_irn_register(arch_env, ptr, &arm_gp_regs[REG_R12]);
+       ptr = new_bd_arm_Add_i(dbg, block, frame, mode_Iu, arm_encode_imm_w_shift(v->shifts[0], v->values[0]));
+       arch_set_irn_register(ptr, &arm_gp_regs[REG_R12]);
        sched_add_before(node, ptr);
 
        for (cnt = 1; cnt < v->ops; ++cnt) {
                long value = arm_encode_imm_w_shift(v->shifts[cnt], v->values[cnt]);
-               ir_node *next = new_rd_arm_Add_i(dbg, irg, block, ptr, mode_Iu, value);
-               arch_set_irn_register(arch_env, next, &arm_gp_regs[REG_R12]);
+               ir_node *next = new_bd_arm_Add_i(dbg, block, ptr, mode_Iu, value);
+               arch_set_irn_register(next, &arm_gp_regs[REG_R12]);
                sched_add_before(node, next);
                ptr = next;
        }
@@ -177,20 +173,19 @@ static ir_node *gen_ptr_add(ir_node *node, ir_node *frame, arm_vals *v)
 */
 static ir_node *gen_ptr_sub(ir_node *node, ir_node *frame, arm_vals *v)
 {
-       ir_graph *irg   = current_ir_graph;
        dbg_info *dbg   = get_irn_dbg_info(node);
        ir_node  *block = get_nodes_block(node);
        int     cnt;
        ir_node *ptr;
 
-       ptr = new_rd_arm_Sub_i(dbg, irg, block, frame, mode_Iu, arm_encode_imm_w_shift(v->shifts[0], v->values[0]));
-       arch_set_irn_register(arch_env, ptr, &arm_gp_regs[REG_R12]);
+       ptr = new_bd_arm_Sub_i(dbg, block, frame, mode_Iu, arm_encode_imm_w_shift(v->shifts[0], v->values[0]));
+       arch_set_irn_register(ptr, &arm_gp_regs[REG_R12]);
        sched_add_before(node, ptr);
 
        for (cnt = 1; cnt < v->ops; ++cnt) {
                long value = arm_encode_imm_w_shift(v->shifts[cnt], v->values[cnt]);
-               ir_node *next = new_rd_arm_Sub_i(dbg, irg, block, ptr, mode_Iu, value);
-               arch_set_irn_register(arch_env, next, &arm_gp_regs[REG_R12]);
+               ir_node *next = new_bd_arm_Sub_i(dbg, block, ptr, mode_Iu, value);
+               arch_set_irn_register(next, &arm_gp_regs[REG_R12]);
                sched_add_before(node, next);
                ptr = next;
        }
@@ -232,14 +227,14 @@ static void peephole_be_Spill(ir_node *node) {
        if (mode_is_float(mode)) {
                if (USE_FPA(cg->isa)) {
                        /* transform into fpaStf */
-                       store = new_rd_arm_fpaStf(dbg, irg, block, ptr, value, get_irg_no_mem(irg), mode);
+                       store = new_bd_arm_fpaStf(dbg, block, ptr, value, get_irg_no_mem(irg), mode);
                        sched_add_before(node, store);
                } else {
                        panic("peephole_be_Spill: spill not supported for this mode");
                }
        } else if (mode_is_dataM(mode)) {
                 /* transform into Store */;
-                store = new_rd_arm_Store(dbg, irg, block, ptr, value, get_irg_no_mem(irg));
+                store = new_bd_arm_Store(dbg, block, ptr, value, get_irg_no_mem(irg));
                 sched_add_before(node, store);
        } else {
                panic("peephole_be_Spill: spill not supported for this mode");
@@ -285,19 +280,19 @@ static void peephole_be_Reload(ir_node *node) {
        if (mode_is_float(mode)) {
                if (USE_FPA(cg->isa)) {
                        /* transform into fpaLdf */
-                       load = new_rd_arm_fpaLdf(dbg, irg, block, ptr, mem, mode);
+                       load = new_bd_arm_fpaLdf(dbg, block, ptr, mem, mode);
                        sched_add_before(node, load);
                        proj = new_rd_Proj(dbg, irg, block, load, mode, pn_arm_fpaLdf_res);
-                       arch_set_irn_register(arch_env, proj, reg);
+                       arch_set_irn_register(proj, reg);
                } else {
                        panic("peephole_be_Spill: spill not supported for this mode");
                }
        } else if (mode_is_dataM(mode)) {
                /* transform into Store */;
-               load = new_rd_arm_Load(dbg, irg, block, ptr, mem);
+               load = new_bd_arm_Load(dbg, block, ptr, mem);
                sched_add_before(node, load);
                proj = new_rd_Proj(dbg, irg, block, load, mode_Iu, pn_arm_Load_res);
-               arch_set_irn_register(arch_env, proj, reg);
+               arch_set_irn_register(proj, reg);
        } else {
                panic("peephole_be_Spill: spill not supported for this mode");
        }
@@ -316,8 +311,7 @@ static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
 /* Perform peephole-optimizations. */
 void arm_peephole_optimization(arm_code_gen_t *new_cg)
 {
-       cg       = new_cg;
-       arch_env = cg->arch_env;
+       cg = new_cg;
 
        /* register peephole optimizations */
        clear_irp_opcodes_generic_func();