* @file
* @brief arm emitter
* @author Oliver Richter, Tobias Gneist, Michael Beck
- * @version $Id$
*/
#include "config.h"
#include "raw_bitset.h"
#include "dbginfo.h"
-#include "../besched.h"
-#include "../beblocksched.h"
-#include "../beirg.h"
-#include "../begnuas.h"
-#include "../be_dbgout.h"
+#include "besched.h"
+#include "beblocksched.h"
+#include "beirg.h"
+#include "begnuas.h"
+#include "bedwarf.h"
#include "arm_emitter.h"
#include "arm_optimize.h"
#include "arm_map_regs.h"
#include "gen_arm_regalloc_if.h"
-#include "../benode.h"
-
-#define SNPRINTF_BUF_LEN 128
+#include "benode.h"
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
static set *sym_or_tv;
static arm_isa_t *isa;
-/**
- * Returns the register at in position pos.
- */
-static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
+static void arm_emit_register(const arch_register_t *reg)
{
- ir_node *op;
- const arch_register_t *reg = NULL;
-
- assert(get_irn_arity(irn) > pos && "Invalid IN position");
-
- /* The out register of the operator at position pos is the
- in register we need. */
- op = get_irn_n(irn, pos);
-
- reg = arch_get_irn_register(op);
-
- assert(reg && "no in register found");
-
- /* in case of a joker register: just return a valid register */
- if (arch_register_type_is(reg, joker)) {
- const arch_register_req_t *req = arch_get_register_req(irn, pos);
-
- if (arch_register_req_is(req, limited)) {
- /* in case of limited requirements: get the first allowed register */
- unsigned idx = rbitset_next(req->limited, 0, 1);
- reg = arch_register_for_index(req->cls, idx);
- } else {
- /* otherwise get first register in class */
- reg = arch_register_for_index(req->cls, 0);
- }
- }
- return reg;
-}
-
-
-/**
- * Returns the register at out position pos.
- */
-static const arch_register_t *get_out_reg(const ir_node *node, int pos)
-{
- ir_node *proj;
- const arch_register_t *reg = NULL;
-
- /* 1st case: irn is not of mode_T, so it has only */
- /* one OUT register -> good */
- /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
- /* Proj with the corresponding projnum for the register */
-
- if (get_irn_mode(node) != mode_T) {
- reg = arch_get_irn_register(node);
- } else if (is_arm_irn(node)) {
- reg = arch_irn_get_register(node, pos);
- } else {
- const ir_edge_t *edge;
-
- foreach_out_edge(node, edge) {
- proj = get_edge_src_irn(edge);
- assert(is_Proj(proj) && "non-Proj from mode_T node");
- if (get_Proj_proj(proj) == pos) {
- reg = arch_get_irn_register(proj);
- break;
- }
- }
- }
-
- assert(reg && "no out register found");
- return reg;
+ be_emit_string(arch_register_get_name(reg));
}
void arm_emit_source_register(const ir_node *node, int pos)
{
- const arch_register_t *reg = get_in_reg(node, pos);
- be_emit_string(arch_register_get_name(reg));
+ const arch_register_t *reg = arch_get_irn_register_in(node, pos);
+ arm_emit_register(reg);
}
void arm_emit_dest_register(const ir_node *node, int pos)
{
- const arch_register_t *reg = get_out_reg(node, pos);
- be_emit_string(arch_register_get_name(reg));
+ const arch_register_t *reg = arch_get_irn_register_out(node, pos);
+ arm_emit_register(reg);
}
void arm_emit_offset(const ir_node *node)
void arm_emit_shifter_operand(const ir_node *node)
{
- const arm_shifter_operand_t *attr = get_irn_generic_attr_const(node);
+ const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(node);
switch (attr->shift_modifier) {
case ARM_SHF_REG:
{
const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(irn);
sym_or_tv_t key, *entry;
- unsigned label;
key.u.entity = attr->entity;
key.is_entity = true;
key.label = 0;
- entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
+ entry = set_insert(sym_or_tv_t, sym_or_tv, &key, sizeof(key), hash_ptr(key.u.generic));
if (entry->label == 0) {
/* allocate a label */
entry->label = get_unique_label();
}
- label = entry->label;
/* load the symbol indirect */
be_emit_cstring("\tldr ");
static void emit_arm_FrameAddr(const ir_node *irn)
{
- const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
+ const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(irn);
be_emit_cstring("\tadd ");
arm_emit_dest_register(irn, 0);
static void emit_arm_fConst(const ir_node *irn)
{
sym_or_tv_t key, *entry;
- unsigned label;
ir_mode *mode;
key.u.tv = get_fConst_value(irn);
key.is_entity = false;
key.label = 0;
- entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
+ entry = set_insert(sym_or_tv_t, sym_or_tv, &key, sizeof(key), hash_ptr(key.u.generic));
if (entry->label == 0) {
/* allocate a label */
entry->label = get_unique_label();
}
- label = entry->label;
/* load the tarval indirect */
mode = get_irn_mode(irn);
*/
static ir_node *sched_next_block(const ir_node *block)
{
- return get_irn_link(block);
+ return (ir_node*)get_irn_link(block);
}
/**
*/
static ir_node *get_cfop_target_block(const ir_node *irn)
{
- return get_irn_link(irn);
+ return (ir_node*)get_irn_link(irn);
}
/**
const ir_node *next_block;
ir_node *op1 = get_irn_n(irn, 0);
const char *suffix;
- pn_Cmp pnc = get_arm_CondJmp_pnc(irn);
- const arm_cmp_attr_t *cmp_attr = get_irn_generic_attr_const(op1);
+ ir_relation relation = get_arm_CondJmp_relation(irn);
+ const arm_cmp_attr_t *cmp_attr = get_arm_cmp_attr_const(op1);
bool is_signed = !cmp_attr->is_unsigned;
assert(is_arm_Cmp(op1) || is_arm_Tst(op1));
}
if (cmp_attr->ins_permuted) {
- pnc = get_mirrored_pnc(pnc);
+ relation = get_inversed_relation(relation);
}
/* for now, the code works for scheduled and non-schedules blocks */
/* we have a block schedule */
next_block = sched_next_block(block);
- assert(pnc != pn_Cmp_False);
- assert(pnc != pn_Cmp_True);
+ assert(relation != ir_relation_false);
+ assert(relation != ir_relation_true);
if (get_cfop_target_block(proj_true) == next_block) {
/* exchange both proj's so the second one can be omitted */
proj_true = proj_false;
proj_false = t;
- pnc = get_negated_pnc(pnc, mode_Iu);
+ relation = get_negated_relation(relation);
}
- switch (pnc) {
- case pn_Cmp_Eq: suffix = "eq"; break;
- case pn_Cmp_Lt: suffix = is_signed ? "lt" : "lo"; break;
- case pn_Cmp_Le: suffix = is_signed ? "le" : "ls"; break;
- case pn_Cmp_Gt: suffix = is_signed ? "gt" : "hi"; break;
- case pn_Cmp_Ge: suffix = is_signed ? "ge" : "hs"; break;
- case pn_Cmp_Lg: suffix = "ne"; break;
- case pn_Cmp_Leg: suffix = "al"; break;
- default: panic("Cmp has unsupported pnc");
+ switch (relation & (ir_relation_less_equal_greater)) {
+ case ir_relation_equal: suffix = "eq"; break;
+ case ir_relation_less: suffix = is_signed ? "lt" : "lo"; break;
+ case ir_relation_less_equal: suffix = is_signed ? "le" : "ls"; break;
+ case ir_relation_greater: suffix = is_signed ? "gt" : "hi"; break;
+ case ir_relation_greater_equal: suffix = is_signed ? "ge" : "hs"; break;
+ case ir_relation_less_greater: suffix = "ne"; break;
+ case ir_relation_less_equal_greater: suffix = "al"; break;
+ default: panic("Cmp has unsupported relation");
}
/* emit the true proj */
be_emit_finish_line_gas(proj_true);
if (get_cfop_target_block(proj_false) == next_block) {
- be_emit_cstring("\t/* fallthrough to ");
- arm_emit_cfop_target(proj_false);
- be_emit_cstring(" */");
- be_emit_finish_line_gas(proj_false);
+ if (be_options.verbose_asm) {
+ be_emit_cstring("\t/* fallthrough to ");
+ arm_emit_cfop_target(proj_false);
+ be_emit_cstring(" */");
+ be_emit_finish_line_gas(proj_false);
+ }
} else {
be_emit_cstring("\tb ");
arm_emit_cfop_target(proj_false);
/** Sort register in ascending order. */
static int reg_cmp(const void *a, const void *b)
{
- const arch_register_t * const *ra = a;
- const arch_register_t * const *rb = b;
+ const arch_register_t * const *ra = (const arch_register_t**)a;
+ const arch_register_t * const *rb = (const arch_register_t**)b;
return *ra < *rb ? -1 : (*ra != *rb);
}
*/
static void emit_arm_CopyB(const ir_node *irn)
{
- const arm_CopyB_attr_t *attr = get_irn_generic_attr_const(irn);
+ const arm_CopyB_attr_t *attr = get_arm_CopyB_attr_const(irn);
unsigned size = attr->size;
- const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
- const char *src = arch_register_get_name(get_in_reg(irn, 1));
+ const char *tgt = arch_register_get_name(arch_get_irn_register_in(irn, 0));
+ const char *src = arch_register_get_name(arch_get_irn_register_in(irn, 1));
const char *t0, *t1, *t2, *t3;
const arch_register_t *tmpregs[4];
/* collect the temporary registers and sort them, we need ascending order */
- tmpregs[0] = get_in_reg(irn, 2);
- tmpregs[1] = get_in_reg(irn, 3);
- tmpregs[2] = get_in_reg(irn, 4);
+ tmpregs[0] = arch_get_irn_register_in(irn, 2);
+ tmpregs[1] = arch_get_irn_register_in(irn, 3);
+ tmpregs[2] = arch_get_irn_register_in(irn, 4);
tmpregs[3] = &arm_registers[REG_R12];
/* Note: R12 is always the last register because the RA did not assign higher ones */
t2 = arch_register_get_name(tmpregs[2]);
t3 = arch_register_get_name(tmpregs[3]);
- be_emit_cstring("/* MemCopy (");
- be_emit_string(src);
- be_emit_cstring(")->(");
- arm_emit_source_register(irn, 0);
- be_emit_irprintf(" [%u bytes], Uses ", size);
- be_emit_string(t0);
- be_emit_cstring(", ");
- be_emit_string(t1);
- be_emit_cstring(", ");
- be_emit_string(t2);
- be_emit_cstring(", and ");
- be_emit_string(t3);
- be_emit_cstring("*/");
- be_emit_finish_line_gas(NULL);
+ if (be_options.verbose_asm) {
+ be_emit_cstring("/* MemCopy (");
+ be_emit_string(src);
+ be_emit_cstring(")->(");
+ arm_emit_source_register(irn, 0);
+ be_emit_irprintf(" [%u bytes], Uses ", size);
+ be_emit_string(t0);
+ be_emit_cstring(", ");
+ be_emit_string(t1);
+ be_emit_cstring(", ");
+ be_emit_string(t2);
+ be_emit_cstring(", and ");
+ be_emit_string(t3);
+ be_emit_cstring("*/");
+ be_emit_finish_line_gas(NULL);
+ }
assert(size > 0 && "CopyB needs size > 0" );
static void emit_arm_SwitchJmp(const ir_node *irn)
{
- const ir_edge_t *edge;
- ir_node *proj;
- int i;
- ir_node **projs;
- int n_projs;
- int block_nr;
- ir_node *default_proj = NULL;
-
- block_nr = get_irn_node_nr(irn);
- n_projs = get_arm_SwitchJmp_n_projs(irn);
-
- projs = XMALLOCNZ(ir_node*, n_projs);
-
- foreach_out_edge(irn, edge) {
- proj = get_edge_src_irn(edge);
- assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
-
- if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
- default_proj = proj;
-
- projs[get_Proj_proj(proj)] = proj;
- }
- assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
-
- /*
- CMP %1S, n_projs - 1
- BHI default
- */
-
- be_emit_cstring("\tcmp ");
+ const arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr_const(irn);
+ be_emit_cstring("\tldrls pc, [pc, ");
arm_emit_source_register(irn, 0);
- be_emit_irprintf(", #%u", n_projs - 1);
+ be_emit_cstring(", asl #2]");
be_emit_finish_line_gas(irn);
- be_emit_cstring("\tbhi ");
- arm_emit_cfop_target(default_proj);
- be_emit_finish_line_gas(default_proj);
-
- /*
- LDR %r12, .TABLE_X_START
- ADD %r12, %r12, [%1S, LSL #2]
- LDR %r15, %r12
- */
-
- be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
- be_emit_finish_line_gas(NULL);
-
- be_emit_irprintf("\tadd %%r12, %%r12, ");
- arm_emit_source_register(irn, 0);
- be_emit_cstring(", LSL #2");
- be_emit_finish_line_gas(NULL);
-
- be_emit_cstring("\tldr %r15, [%r12, #0]");
- be_emit_finish_line_gas(NULL);
-
- be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
- be_emit_finish_line_gas(NULL);
- be_emit_irprintf("\t.align 2");
- be_emit_finish_line_gas(NULL);
- be_emit_irprintf("TABLE_%d:", block_nr);
- be_emit_finish_line_gas(NULL);
-
- for (i = 0; i < n_projs; ++i) {
- proj = projs[i];
- if (proj == NULL) {
- proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
- }
- be_emit_cstring("\t.word\t");
- arm_emit_cfop_target(proj);
- be_emit_finish_line_gas(proj);
- }
- be_emit_irprintf("\t.align 2\n");
- be_emit_finish_line_gas(NULL);
- xfree(projs);
+ be_emit_jump_table(irn, attr->table, NULL, get_cfop_target_block);
}
/** Emit an IncSP node */
be_emit_cstring(", ");
arm_emit_source_register(irn, 0);
be_emit_irprintf(", #0x%X", offs);
+ be_emit_finish_line_gas(irn);
} else {
/* omitted IncSP(0) */
return;
}
- be_emit_finish_line_gas(irn);
}
static void emit_be_Copy(const ir_node *irn)
{
ir_mode *mode = get_irn_mode(irn);
- if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
+ if (arch_get_irn_register_in(irn, 0) == arch_get_irn_register_out(irn, 0)) {
/* omitted Copy */
return;
}
assert(sp_change == 0);
}
+static void emit_be_Start(const ir_node *node)
+{
+ ir_graph *irg = get_irn_irg(node);
+ ir_type *frame_type = get_irg_frame_type(irg);
+ unsigned size = get_type_size_bytes(frame_type);
+
+ /* allocate stackframe */
+ if (size > 0) {
+ be_emit_cstring("\tsub ");
+ arm_emit_register(&arm_registers[REG_SP]);
+ be_emit_cstring(", ");
+ arm_emit_register(&arm_registers[REG_SP]);
+ be_emit_irprintf(", #0x%X", size);
+ be_emit_finish_line_gas(node);
+ }
+}
+
static void emit_be_Return(const ir_node *node)
{
+ ir_graph *irg = get_irn_irg(node);
+ ir_type *frame_type = get_irg_frame_type(irg);
+ unsigned size = get_type_size_bytes(frame_type);
+
+ /* deallocate stackframe */
+ if (size > 0) {
+ be_emit_cstring("\tadd ");
+ arm_emit_register(&arm_registers[REG_SP]);
+ be_emit_cstring(", ");
+ arm_emit_register(&arm_registers[REG_SP]);
+ be_emit_irprintf(", #0x%X", size);
+ be_emit_finish_line_gas(node);
+ }
+
be_emit_cstring("\tmov pc, lr");
be_emit_finish_line_gas(node);
}
if (get_cfop_target_block(node) != next_block) {
be_emit_cstring("\tb ");
arm_emit_cfop_target(node);
+ be_emit_finish_line_gas(node);
} else {
- be_emit_cstring("\t/* fallthrough to ");
- arm_emit_cfop_target(node);
- be_emit_cstring(" */");
+ if (be_options.verbose_asm) {
+ be_emit_cstring("\t/* fallthrough to ");
+ arm_emit_cfop_target(node);
+ be_emit_cstring(" */");
+ be_emit_finish_line_gas(node);
+ }
}
- be_emit_finish_line_gas(node);
}
static void emit_nothing(const ir_node *irn)
static void arm_register_emitters(void)
{
/* first clear the generic function pointer for all ops */
- clear_irp_opcodes_generic_func();
+ ir_clear_opcodes_generic_func();
/* register all emitter functions defined in spec */
arm_register_spec_emitters();
set_emitter(op_be_MemPerm, emit_be_MemPerm);
set_emitter(op_be_Perm, emit_be_Perm);
set_emitter(op_be_Return, emit_be_Return);
+ set_emitter(op_be_Start, emit_be_Start);
/* no need to emit anything for the following nodes */
set_emitter(op_Phi, emit_nothing);
set_emitter(op_be_Keep, emit_nothing);
- set_emitter(op_be_Start, emit_nothing);
- set_emitter(op_be_Barrier, emit_nothing);
}
/**
if (op->ops.generic) {
emit_func *emit = (emit_func *)op->ops.generic;
- be_dbg_set_dbg_info(get_irn_dbg_info(irn));
+ be_dwarf_location(get_irn_dbg_info(irn));
(*emit)(irn);
} else {
panic("Error: No emit handler for node %+F (graph %+F)\n",
- irn, current_ir_graph);
+ irn, get_irn_irg(irn));
}
}
*/
static void arm_emit_block_header(ir_node *block, ir_node *prev)
{
- int n_cfgpreds;
- int need_label;
- int i, arity;
- ir_graph *irg = get_irn_irg(block);
- ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
+ bool need_label = false;
+ int n_cfgpreds;
- need_label = 0;
n_cfgpreds = get_Block_n_cfgpreds(block);
if (n_cfgpreds == 1) {
ir_node *pred = get_Block_cfgpred(block, 0);
* are no fallthroughs */
if (pred_block == prev &&
!(is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)))) {
- need_label = 0;
+ need_label = false;
} else {
- need_label = 1;
+ need_label = true;
}
} else {
- need_label = 1;
+ need_label = true;
}
- if (need_label) {
- be_gas_emit_block_name(block);
- be_emit_char(':');
-
- be_emit_pad_comment();
- be_emit_cstring(" /* preds:");
-
- /* emit list of pred blocks in comment */
- arity = get_irn_arity(block);
- for (i = 0; i < arity; ++i) {
- ir_node *predblock = get_Block_cfgpred_block(block, i);
- be_emit_irprintf(" %d", get_irn_node_nr(predblock));
- }
- } else {
- be_emit_cstring("\t/* ");
- be_gas_emit_block_name(block);
- be_emit_cstring(": ");
- }
- if (exec_freq != NULL) {
- be_emit_irprintf(" freq: %f",
- get_block_execfreq(exec_freq, block));
- }
- be_emit_cstring(" */\n");
- be_emit_write_line();
+ be_gas_begin_block(block, need_label);
}
/**
ir_node *irn;
arm_emit_block_header(block, prev_block);
- be_dbg_set_dbg_info(get_irn_dbg_info(block));
+ be_dwarf_location(get_irn_dbg_info(block));
sched_foreach(block, irn) {
arm_emit_node(irn);
}
*/
static int cmp_sym_or_tv(const void *elt, const void *key, size_t size)
{
- const sym_or_tv_t *p1 = elt;
- const sym_or_tv_t *p2 = key;
+ const sym_or_tv_t *p1 = (const sym_or_tv_t*)elt;
+ const sym_or_tv_t *p2 = (const sym_or_tv_t*)key;
(void) size;
/* as an identifier NEVER can point to a tarval, it's enough
ir_entity *entity = get_irg_entity(irg);
const arch_env_t *arch_env = be_get_irg_arch_env(irg);
ir_node **blk_sched;
- int i, n;
+ size_t i, n;
isa = (arm_isa_t*) arch_env;
sym_or_tv = new_set(cmp_sym_or_tv, 8);
arm_register_emitters();
- be_dbg_method_begin(entity);
-
/* create the block schedule */
blk_sched = be_create_block_schedule(irg);
- be_gas_emit_function_prolog(entity, 4);
+ be_gas_emit_function_prolog(entity, 4, NULL);
irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
/* emit SymConst values */
if (set_count(sym_or_tv) > 0) {
- sym_or_tv_t *entry;
-
be_emit_cstring("\t.align 2\n");
- foreach_set(sym_or_tv, entry) {
+ foreach_set(sym_or_tv, sym_or_tv_t, entry) {
emit_constant_name(entry);
be_emit_cstring(":\n");
be_emit_write_line();
be_emit_write_line();
} else {
ir_tarval *tv = entry->u.tv;
- int i, size = get_mode_size_bytes(get_tarval_mode(tv));
- unsigned v;
+ int vi;
+ int size = get_mode_size_bytes(get_tarval_mode(tv));
/* beware: ARM fpa uses big endian format */
- for (i = ((size + 3) & ~3) - 4; i >= 0; i -= 4) {
+ for (vi = ((size + 3) & ~3) - 4; vi >= 0; vi -= 4) {
/* get 32 bits */
- v = get_tarval_sub_bits(tv, i+3);
- v = (v << 8) | get_tarval_sub_bits(tv, i+2);
- v = (v << 8) | get_tarval_sub_bits(tv, i+1);
- v = (v << 8) | get_tarval_sub_bits(tv, i+0);
+ unsigned v;
+ v = get_tarval_sub_bits(tv, vi+3);
+ v = (v << 8) | get_tarval_sub_bits(tv, vi+2);
+ v = (v << 8) | get_tarval_sub_bits(tv, vi+1);
+ v = (v << 8) | get_tarval_sub_bits(tv, vi+0);
be_emit_irprintf("\t.word\t%u\n", v);
be_emit_write_line();
}
del_set(sym_or_tv);
be_gas_emit_function_epilog(entity);
- be_dbg_method_end();
}
void arm_init_emitter(void)
projects / libfirm / blobdiff