* @file
* @brief arm emitter
* @author Oliver Richter, Tobias Gneist, Michael Beck
- * @version $Id$
*/
#include "config.h"
#include "raw_bitset.h"
#include "dbginfo.h"
-#include "../besched.h"
-#include "../beblocksched.h"
-#include "../beirg.h"
-#include "../begnuas.h"
-#include "../be_dbgout.h"
+#include "besched.h"
+#include "beblocksched.h"
+#include "beirg.h"
+#include "begnuas.h"
+#include "bedwarf.h"
#include "arm_emitter.h"
#include "arm_optimize.h"
#include "arm_map_regs.h"
#include "gen_arm_regalloc_if.h"
-#include "../benode.h"
+#include "benode.h"
#define SNPRINTF_BUF_LEN 128
static set *sym_or_tv;
static arm_isa_t *isa;
-/**
- * Returns the register at in position pos.
- */
-static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
-{
- ir_node *op;
- const arch_register_t *reg = NULL;
-
- assert(get_irn_arity(irn) > pos && "Invalid IN position");
-
- /* The out register of the operator at position pos is the
- in register we need. */
- op = get_irn_n(irn, pos);
-
- reg = arch_get_irn_register(op);
-
- assert(reg && "no in register found");
-
- /* in case of a joker register: just return a valid register */
- if (reg->type & arch_register_type_joker) {
- const arch_register_req_t *req = arch_get_register_req(irn, pos);
-
- if (arch_register_req_is(req, limited)) {
- /* in case of limited requirements: get the first allowed register */
- unsigned idx = rbitset_next(req->limited, 0, 1);
- reg = arch_register_for_index(req->cls, idx);
- } else {
- /* otherwise get first register in class */
- reg = arch_register_for_index(req->cls, 0);
- }
- }
- return reg;
-}
-
-
-/**
- * Returns the register at out position pos.
- */
-static const arch_register_t *get_out_reg(const ir_node *node, int pos)
-{
- ir_node *proj;
- const arch_register_t *reg = NULL;
-
- /* 1st case: irn is not of mode_T, so it has only */
- /* one OUT register -> good */
- /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
- /* Proj with the corresponding projnum for the register */
-
- if (get_irn_mode(node) != mode_T) {
- reg = arch_get_irn_register(node);
- } else if (is_arm_irn(node)) {
- reg = arch_irn_get_register(node, pos);
- } else {
- const ir_edge_t *edge;
-
- foreach_out_edge(node, edge) {
- proj = get_edge_src_irn(edge);
- assert(is_Proj(proj) && "non-Proj from mode_T node");
- if (get_Proj_proj(proj) == pos) {
- reg = arch_get_irn_register(proj);
- break;
- }
- }
- }
-
- assert(reg && "no out register found");
- return reg;
-}
-
static void arm_emit_register(const arch_register_t *reg)
{
be_emit_string(arch_register_get_name(reg));
void arm_emit_source_register(const ir_node *node, int pos)
{
- const arch_register_t *reg = get_in_reg(node, pos);
+ const arch_register_t *reg = arch_get_irn_register_in(node, pos);
arm_emit_register(reg);
}
void arm_emit_dest_register(const ir_node *node, int pos)
{
- const arch_register_t *reg = get_out_reg(node, pos);
+ const arch_register_t *reg = arch_get_irn_register_out(node, pos);
arm_emit_register(reg);
}
{
const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(irn);
sym_or_tv_t key, *entry;
- unsigned label;
key.u.entity = attr->entity;
key.is_entity = true;
key.label = 0;
- entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
+ entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), hash_ptr(key.u.generic));
if (entry->label == 0) {
/* allocate a label */
entry->label = get_unique_label();
}
- label = entry->label;
/* load the symbol indirect */
be_emit_cstring("\tldr ");
static void emit_arm_fConst(const ir_node *irn)
{
sym_or_tv_t key, *entry;
- unsigned label;
ir_mode *mode;
key.u.tv = get_fConst_value(irn);
key.is_entity = false;
key.label = 0;
- entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
+ entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), hash_ptr(key.u.generic));
if (entry->label == 0) {
/* allocate a label */
entry->label = get_unique_label();
}
- label = entry->label;
/* load the tarval indirect */
mode = get_irn_mode(irn);
const arm_CopyB_attr_t *attr = get_arm_CopyB_attr_const(irn);
unsigned size = attr->size;
- const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
- const char *src = arch_register_get_name(get_in_reg(irn, 1));
+ const char *tgt = arch_register_get_name(arch_get_irn_register_in(irn, 0));
+ const char *src = arch_register_get_name(arch_get_irn_register_in(irn, 1));
const char *t0, *t1, *t2, *t3;
const arch_register_t *tmpregs[4];
/* collect the temporary registers and sort them, we need ascending order */
- tmpregs[0] = get_in_reg(irn, 2);
- tmpregs[1] = get_in_reg(irn, 3);
- tmpregs[2] = get_in_reg(irn, 4);
+ tmpregs[0] = arch_get_irn_register_in(irn, 2);
+ tmpregs[1] = arch_get_irn_register_in(irn, 3);
+ tmpregs[2] = arch_get_irn_register_in(irn, 4);
tmpregs[3] = &arm_registers[REG_R12];
/* Note: R12 is always the last register because the RA did not assign higher ones */
static void emit_arm_SwitchJmp(const ir_node *irn)
{
- const ir_edge_t *edge;
- ir_node *proj;
- int i;
- ir_node **projs;
- int n_projs;
- int block_nr;
- ir_node *default_proj = NULL;
-
- block_nr = get_irn_node_nr(irn);
- n_projs = get_arm_SwitchJmp_n_projs(irn);
-
- projs = XMALLOCNZ(ir_node*, n_projs);
-
- foreach_out_edge(irn, edge) {
- proj = get_edge_src_irn(edge);
- assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
-
- if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
- default_proj = proj;
-
- projs[get_Proj_proj(proj)] = proj;
- }
- assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
-
- /*
- CMP %1S, n_projs - 1
- BHI default
- */
-
- be_emit_cstring("\tcmp ");
+ const arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr_const(irn);
+ be_emit_cstring("\tldrls pc, [pc, ");
arm_emit_source_register(irn, 0);
- be_emit_irprintf(", #%u", n_projs - 1);
+ be_emit_cstring(", asl #2]");
be_emit_finish_line_gas(irn);
- be_emit_cstring("\tbhi ");
- arm_emit_cfop_target(default_proj);
- be_emit_finish_line_gas(default_proj);
-
- /*
- LDR %r12, .TABLE_X_START
- ADD %r12, %r12, [%1S, LSL #2]
- LDR %r15, %r12
- */
-
- be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
- be_emit_finish_line_gas(NULL);
-
- be_emit_irprintf("\tadd %%r12, %%r12, ");
- arm_emit_source_register(irn, 0);
- be_emit_cstring(", LSL #2");
- be_emit_finish_line_gas(NULL);
-
- be_emit_cstring("\tldr %r15, [%r12, #0]");
- be_emit_finish_line_gas(NULL);
-
- be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
- be_emit_finish_line_gas(NULL);
- be_emit_irprintf("\t.align 2");
- be_emit_finish_line_gas(NULL);
- be_emit_irprintf("TABLE_%d:", block_nr);
- be_emit_finish_line_gas(NULL);
-
- for (i = 0; i < n_projs; ++i) {
- proj = projs[i];
- if (proj == NULL) {
- proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
- }
- be_emit_cstring("\t.word\t");
- arm_emit_cfop_target(proj);
- be_emit_finish_line_gas(proj);
- }
- be_emit_irprintf("\t.align 2\n");
- be_emit_finish_line_gas(NULL);
- xfree(projs);
+ be_emit_jump_table(irn, attr->table, NULL, get_cfop_target_block);
}
/** Emit an IncSP node */
{
ir_mode *mode = get_irn_mode(irn);
- if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
+ if (arch_get_irn_register_in(irn, 0) == arch_get_irn_register_out(irn, 0)) {
/* omitted Copy */
return;
}
static void arm_register_emitters(void)
{
/* first clear the generic function pointer for all ops */
- clear_irp_opcodes_generic_func();
+ ir_clear_opcodes_generic_func();
/* register all emitter functions defined in spec */
arm_register_spec_emitters();
if (op->ops.generic) {
emit_func *emit = (emit_func *)op->ops.generic;
- be_dbg_set_dbg_info(get_irn_dbg_info(irn));
+ be_dwarf_location(get_irn_dbg_info(irn));
(*emit)(irn);
} else {
panic("Error: No emit handler for node %+F (graph %+F)\n",
- irn, current_ir_graph);
+ irn, get_irn_irg(irn));
}
}
ir_node *irn;
arm_emit_block_header(block, prev_block);
- be_dbg_set_dbg_info(get_irn_dbg_info(block));
+ be_dwarf_location(get_irn_dbg_info(block));
sched_foreach(block, irn) {
arm_emit_node(irn);
}
arm_register_emitters();
- be_dbg_method_begin(entity);
-
/* create the block schedule */
blk_sched = be_create_block_schedule(irg);
- be_gas_emit_function_prolog(entity, 4);
+ be_gas_emit_function_prolog(entity, 4, NULL);
irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
be_emit_write_line();
} else {
ir_tarval *tv = entry->u.tv;
- int i, size = get_mode_size_bytes(get_tarval_mode(tv));
- unsigned v;
+ int vi;
+ int size = get_mode_size_bytes(get_tarval_mode(tv));
/* beware: ARM fpa uses big endian format */
- for (i = ((size + 3) & ~3) - 4; i >= 0; i -= 4) {
+ for (vi = ((size + 3) & ~3) - 4; vi >= 0; vi -= 4) {
/* get 32 bits */
- v = get_tarval_sub_bits(tv, i+3);
- v = (v << 8) | get_tarval_sub_bits(tv, i+2);
- v = (v << 8) | get_tarval_sub_bits(tv, i+1);
- v = (v << 8) | get_tarval_sub_bits(tv, i+0);
+ unsigned v;
+ v = get_tarval_sub_bits(tv, vi+3);
+ v = (v << 8) | get_tarval_sub_bits(tv, vi+2);
+ v = (v << 8) | get_tarval_sub_bits(tv, vi+1);
+ v = (v << 8) | get_tarval_sub_bits(tv, vi+0);
be_emit_irprintf("\t.word\t%u\n", v);
be_emit_write_line();
}
del_set(sym_or_tv);
be_gas_emit_function_epilog(entity);
- be_dbg_method_end();
}
void arm_init_emitter(void)