besched: Add and use sched_foreach_reverse_safe().

[libfirm] / ir / be / amd64 / bearch_amd64.c

diff --git a/ir/be/amd64/bearch_amd64.c b/ir/be/amd64/bearch_amd64.c
index ed865c1..3045a5f 100644 (file)
--- a/ir/be/amd64/bearch_amd64.c
+++ b/ir/be/amd64/bearch_amd64.c
@@ -1,20 +1,6 @@
 /*
- * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
- *
  * This file is part of libFirm.
- *
- * This file may be distributed and/or modified under the terms of the
- * GNU General Public License version 2 as published by the Free Software
- * Foundation and appearing in the file LICENSE.GPL included in the
- * packaging of this file.
- *
- * Licensees holding valid libFirm Professional Edition licenses may use
- * this file in accordance with the libFirm Commercial License.
- * Agreement provided with the Software.
- *
- * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
- * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE.
+ * Copyright (C) 2012 University of Karlsruhe.
  */
 
 /**
@@ -33,9 +19,11 @@
 
 #include "bitset.h"
 #include "debug.h"
+#include "error.h"
 
-#include "be.h"
+#include "be_t.h"
 #include "bearch.h"
+#include "beirg.h"
 #include "benode.h"
 #include "belower.h"
 #include "besched.h"
@@ -110,7 +98,6 @@ static const arch_irn_ops_t amd64_irn_ops = {
        amd64_get_frame_entity,
        amd64_set_frame_offset,
        amd64_get_sp_bias,
-       NULL,    /* get_inverse             */
        NULL,    /* get_op_estimated_cost   */
        NULL,    /* possible_memory_operand */
        NULL,    /* perform_memory_operand  */
@@ -148,11 +135,8 @@ static void transform_Reload(ir_node *node)
        ir_node   *proj;
        ir_node   *load;
 
-       ir_node  *sched_point = sched_prev(node);
-
        load = new_bd_amd64_Load(dbgi, block, ptr, mem, entity);
-       sched_add_after(sched_point, load);
-       sched_remove(node);
+       sched_replace(node, load);
 
        proj = new_rd_Proj(dbgi, load, mode, pn_amd64_Load_res);
 
@@ -172,26 +156,19 @@ static void transform_Spill(ir_node *node)
        ir_node   *val    = get_irn_n(node, n_be_Spill_val);
        //ir_mode   *mode   = get_irn_mode(val);
        ir_entity *entity = be_get_frame_entity(node);
-       ir_node   *sched_point;
        ir_node   *store;
 
-       sched_point = sched_prev(node);
        store = new_bd_amd64_Store(dbgi, block, ptr, val, mem, entity);
-
-       sched_remove(node);
-       sched_add_after(sched_point, store);
+       sched_replace(node, store);
 
        exchange(node, store);
 }
 
 static void amd64_after_ra_walker(ir_node *block, void *data)
 {
-       ir_node *node, *prev;
        (void) data;
 
-       for (node = sched_last(block); !sched_is_begin(node); node = prev) {
-               prev = sched_prev(node);
-
+       sched_foreach_reverse_safe(block, node) {
                if (be_is_Reload(node)) {
                        transform_Reload(node);
                } else if (be_is_Spill(node)) {
@@ -251,7 +228,6 @@ static amd64_isa_t amd64_isa_template = {
                &amd64_registers[REG_RSP], /* stack pointer register */
                &amd64_registers[REG_RBP], /* base pointer register */
                3,                         /* power of two stack alignment for calls, 2^2 == 4 */
-               NULL,                      /* main environment */
                7,                         /* costs for a spill instruction */
                5,                         /* costs for a reload instruction */
                false,                     /* no custom abi handling */
@@ -269,14 +245,11 @@ static void amd64_finish(void)
        amd64_free_opcodes();
 }
 
-static arch_env_t *amd64_begin_codegeneration(const be_main_env_t *env)
+static arch_env_t *amd64_begin_codegeneration(void)
 {
        amd64_isa_t *isa = XMALLOC(amd64_isa_t);
        *isa = amd64_isa_template;
 
-       be_emit_init(env->file_handle);
-       be_gas_begin_compilation_unit(env);
-
        return &isa->base;
 }
 
@@ -285,12 +258,6 @@ static arch_env_t *amd64_begin_codegeneration(const be_main_env_t *env)
  */
 static void amd64_end_codegeneration(void *self)
 {
-       amd64_isa_t *isa = (amd64_isa_t*)self;
-
-       /* emit now all global declarations */
-       be_gas_end_compilation_unit(isa->base.main_env);
-
-       be_emit_exit();
        free(self);
 }
 
@@ -454,41 +421,29 @@ static int amd64_is_valid_clobber(const char *clobber)
 
 static int amd64_register_saved_by(const arch_register_t *reg, int callee)
 {
-       if (callee) {
-               /* check for callee saved */
-               if (reg->reg_class == &amd64_reg_classes[CLASS_amd64_gp]) {
-                       switch (reg->index) {
-                       case REG_GP_RBX:
-                       case REG_GP_RBP:
-                       case REG_GP_R12:
-                       case REG_GP_R13:
-                       case REG_GP_R14:
-                       case REG_GP_R15:
-                               return 1;
-                       default:
-                               return 0;
-                       }
-               }
-       } else {
-               /* check for caller saved */
-               if (reg->reg_class == &amd64_reg_classes[CLASS_amd64_gp]) {
-                       switch (reg->index) {
-                       case REG_GP_RAX:
-                       case REG_GP_RCX:
-                       case REG_GP_RDX:
-                       case REG_GP_RSI:
-                       case REG_GP_RDI:
-                       case REG_GP_R8:
-                       case REG_GP_R9:
-                       case REG_GP_R10:
-                       case REG_GP_R11:
-                               return 1;
-                       default:
-                               return 0;
-                       }
-               }
+       switch (reg->global_index) {
+       case REG_RBX:
+       case REG_RBP:
+       case REG_R12:
+       case REG_R13:
+       case REG_R14:
+       case REG_R15:
+               return callee;
+
+       case REG_RAX:
+       case REG_RCX:
+       case REG_RDX:
+       case REG_RSI:
+       case REG_RDI:
+       case REG_R8:
+       case REG_R9:
+       case REG_R10:
+       case REG_R11:
+               return !callee;
+
+       default:
+               return 0;
        }
-       return 0;
 }
 
 const arch_isa_if_t amd64_isa_if = {