amd64: added be_Spill and be_Reload transformation.

[libfirm] / ir / be / amd64 / amd64_spec.pl

diff --git a/ir/be/amd64/amd64_spec.pl b/ir/be/amd64/amd64_spec.pl
index d184a76..8d81010 100644 (file)
--- a/ir/be/amd64/amd64_spec.pl
+++ b/ir/be/amd64/amd64_spec.pl
@@ -115,7 +115,7 @@ $arch = "amd64";
                { name => "r14", type => 2 },
                { name => "r15", type => 2 },
 #              { name => "gp_NOREG", type => 4 }, # we need a dummy register for NoReg nodes
-               { mode => "mode_Iu" }
+               { mode => "mode_Lu" }
        ],
 #      fp => [
 #              { name => "xmm0", type => 1 },
@@ -142,7 +142,7 @@ $arch = "amd64";
        ],
 );
 
-$mode_gp        = "mode_Iu";
+$mode_gp        = "mode_Lu";
 $mode_flags     = "mode_Iu";
 
 sub amd64_custom_init_attr {
@@ -203,22 +203,45 @@ Push => {
 #      units     => [ "GP" ],
 },
 Add => {
+       op_flags   => "C",
        irn_flags  => "R",
        state      => "exc_pinned",
        reg_req    => { in => [ "gp", "gp" ],
                        out => [ "gp" ] },
        in         => [ "left", "right" ],
-       emit       => ". mov %S2, %D1\n"
-                     . ". add %S1, %D1\n",
        outs       => [ "res" ],
        mode       => $mode_gp,
+       modified_flags => 1,
+},
+Mul => {
+       # we should not rematrialize this node. It produces 2 results and has
+       # very strict constraints
+       state     => "exc_pinned",
+       reg_req   => { in  => [ "rax", "gp" ],
+                      out => [ "rax rdx" ] },
+       ins       => [ "left", "right" ],
+       emit      => '. mul %S2',
+       outs      => [ "res" ],
+       mode      => $mode_gp,
+       am        => "source,binary",
+       modified_flags => $status_flags
+},
+Sub => {
+       irn_flags  => "R",
+       state      => "exc_pinned",
+       reg_req    => { in => [ "gp", "gp" ],
+                       out => [ "gp" ] },
+       in         => [ "left", "right" ],
+       outs       => [ "res" ],
+       mode       => $mode_gp,
+       modified_flags => 1,
 },
 Immediate => {
        op_flags  => "c",
        attr      => "unsigned imm_value",
        init_attr => "attr->ext.imm_value = imm_value;",
        reg_req   => { out => [ "gp" ] },
-       emit      => '. movq %C, %D1',
+       emit      => '. mov %C, %D1',
        mode      => $mode_gp,
 },
 SymConst => {
@@ -268,6 +291,33 @@ Jcc => {
        init_attr => "attr->ext.pnc = pnc;",
        mode      => "mode_T",
 },
+Load => {
+       op_flags  => "L|F",
+       state     => "exc_pinned",
+       reg_req   => { in => [ "gp", "none" ],
+                      out => [ "gp", "none" ] },
+       ins       => [ "ptr", "mem" ],
+       outs      => [ "res",  "M" ],
+       emit      => ". mov (%S1), %D1"
+},
+FrameAddr => {
+       op_flags  => "c",
+       irn_flags => "R",
+       reg_req   => { in => [ "gp" ], out => [ "gp" ] },
+       ins       => [ "base" ],
+       attr      => "ir_entity *entity",
+       attr_type => "amd64_SymConst_attr_t",
+       mode      => $mode_gp,
+},
+Store => {
+       op_flags  => "L|F",
+       state     => "exc_pinned",
+       reg_req   => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+       ins       => [ "ptr", "val", "mem" ],
+       outs      => [ "M" ],
+       mode      => "mode_M",
+       emit      => ". mov %S2, (%S1)"
+},
 
 #NoReg_GP => {
 #      state     => "pinned",