use memory constraints for mips atomic asm

[musl] / arch / mips / atomic.h

diff --git a/arch/mips/atomic.h b/arch/mips/atomic.h
index a09f98d..6731d17 100644 (file)
--- a/arch/mips/atomic.h
+++ b/arch/mips/atomic.h
@@ -27,16 +27,17 @@ static inline int a_cas(volatile int *p, int t, int s)
        int dummy;
        __asm__ __volatile__(
                ".set push\n"
+               ".set mips2\n"
                ".set noreorder\n"
-               "1:     ll %0, 0(%2)\n"
+               "1:     ll %0, %2\n"
                "       bne %0, %3, 1f\n"
                "       addu %1, %4, $0\n"
-               "       sc %1, 0(%2)\n"
+               "       sc %1, %2\n"
                "       beq %1, $0, 1b\n"
                "       nop\n"
                "1:     \n"
                ".set pop\n"
-               : "=&r"(t), "=&r"(dummy) : "r"(p), "r"(t), "r"(s) : "memory" );
+               : "=&r"(t), "=&r"(dummy), "+m"(*p) : "r"(t), "r"(s) : "memory" );
         return t;
 }
 
@@ -56,15 +57,16 @@ static inline int a_swap(volatile int *x, int v)
        int old, dummy;
        __asm__ __volatile__(
                ".set push\n"
+               ".set mips2\n"
                ".set noreorder\n"
-               "1:     ll %0, 0(%2)\n"
+               "1:     ll %0, %2\n"
                "       addu %1, %3, $0\n"
-               "       sc %1, 0(%2)\n"
+               "       sc %1, %2\n"
                "       beq %1, $0, 1b\n"
                "       nop\n"
                "1:     \n"
                ".set pop\n"
-               : "=&r"(old), "=&r"(dummy) : "r"(x), "r"(v) : "memory" );
+               : "=&r"(old), "=&r"(dummy), "+m"(*x) : "r"(v) : "memory" );
         return old;
 }
 
@@ -73,15 +75,16 @@ static inline int a_fetch_add(volatile int *x, int v)
        int old, dummy;
        __asm__ __volatile__(
                ".set push\n"
+               ".set mips2\n"
                ".set noreorder\n"
-               "1:     ll %0, 0(%2)\n"
+               "1:     ll %0, %2\n"
                "       addu %1, %0, %3\n"
-               "       sc %1, 0(%2)\n"
+               "       sc %1, %2\n"
                "       beq %1, $0, 1b\n"
                "       nop\n"
                "1:     \n"
                ".set pop\n"
-               : "=&r"(old), "=&r"(dummy) : "r"(x), "r"(v) : "memory" );
+               : "=&r"(old), "=&r"(dummy), "+m"(*x) : "r"(v) : "memory" );
         return old;
 }
 
@@ -90,15 +93,16 @@ static inline void a_inc(volatile int *x)
        int dummy;
        __asm__ __volatile__(
                ".set push\n"
+               ".set mips2\n"
                ".set noreorder\n"
-               "1:     ll %0, 0(%1)\n"
+               "1:     ll %0, %1\n"
                "       addu %0, %0, 1\n"
-               "       sc %0, 0(%1)\n"
+               "       sc %0, %1\n"
                "       beq %0, $0, 1b\n"
                "       nop\n"
                "1:     \n"
                ".set pop\n"
-               : "=&r"(dummy) : "r"(x) : "memory" );
+               : "=&r"(dummy), "+m"(*x) : : "memory" );
 }
 
 static inline void a_dec(volatile int *x)
@@ -106,15 +110,16 @@ static inline void a_dec(volatile int *x)
        int dummy;
        __asm__ __volatile__(
                ".set push\n"
+               ".set mips2\n"
                ".set noreorder\n"
-               "1:     ll %0, 0(%1)\n"
+               "1:     ll %0, %1\n"
                "       subu %0, %0, 1\n"
-               "       sc %0, 0(%1)\n"
+               "       sc %0, %1\n"
                "       beq %0, $0, 1b\n"
                "       nop\n"
                "1:     \n"
                ".set pop\n"
-               : "=&r"(dummy) : "r"(x) : "memory" );
+               : "=&r"(dummy), "+m"(*x) : : "memory" );
 }
 
 static inline void a_store(volatile int *p, int x)
@@ -122,15 +127,16 @@ static inline void a_store(volatile int *p, int x)
        int dummy;
        __asm__ __volatile__(
                ".set push\n"
+               ".set mips2\n"
                ".set noreorder\n"
-               "1:     ll %0, 0(%1)\n"
+               "1:     ll %0, %1\n"
                "       addu %0, %2, $0\n"
-               "       sc %0, 0(%1)\n"
+               "       sc %0, %1\n"
                "       beq %0, $0, 1b\n"
                "       nop\n"
                "1:     \n"
                ".set pop\n"
-               : "=&r"(dummy) : "r"(p), "r"(x) : "memory" );
+               : "=&r"(dummy), "+m"(*p) : "r"(x) : "memory" );
 }
 
 static inline void a_spin()
@@ -147,15 +153,16 @@ static inline void a_and(volatile int *p, int v)
        int dummy;
        __asm__ __volatile__(
                ".set push\n"
+               ".set mips2\n"
                ".set noreorder\n"
-               "1:     ll %0, 0(%1)\n"
+               "1:     ll %0, %1\n"
                "       and %0, %0, %2\n"
-               "       sc %0, 0(%1)\n"
+               "       sc %0, %1\n"
                "       beq %0, $0, 1b\n"
                "       nop\n"
                "1:     \n"
                ".set pop\n"
-               : "=&r"(dummy) : "r"(p), "r"(v) : "memory" );
+               : "=&r"(dummy), "+m"(*p) : "r"(v) : "memory" );
 }
 
 static inline void a_or(volatile int *p, int v)
@@ -163,15 +170,21 @@ static inline void a_or(volatile int *p, int v)
        int dummy;
        __asm__ __volatile__(
                ".set push\n"
+               ".set mips2\n"
                ".set noreorder\n"
-               "1:     ll %0, 0(%1)\n"
+               "1:     ll %0, %1\n"
                "       or %0, %0, %2\n"
-               "       sc %0, 0(%1)\n"
+               "       sc %0, %1\n"
                "       beq %0, $0, 1b\n"
                "       nop\n"
                "1:     \n"
                ".set pop\n"
-               : "=&r"(dummy) : "r"(p), "r"(v) : "memory" );
+               : "=&r"(dummy), "+m"(*p) : "r"(v) : "memory" );
+}
+
+static inline void a_or_l(volatile void *p, long v)
+{
+       a_or(p, v);
 }
 
 static inline void a_and_64(volatile uint64_t *p, uint64_t v)