- case iro_Add: {
- bitinfo* const l = get_bitinfo(get_Add_left(irn));
- bitinfo* const r = get_bitinfo(get_Add_right(irn));
- ir_tarval* const lz = l->z;
- ir_tarval* const lo = l->o;
- ir_tarval* const rz = r->z;
- ir_tarval* const ro = r->o;
- if (lz == lo && rz == ro) {
- z = o = tarval_add(lz, rz);
- } else {
- // TODO improve: can only do lower disjoint bits
- /* Determine where any of the operands has zero bits, i.e. where no
- * carry out is generated if there is not carry in */
- ir_tarval* const no_c_in_no_c_out = tarval_and(lz, rz);
- /* Generate a mask of the lower consecutive zeroes: x | -x. In this
- * range the addition is disjoint and therefore Add behaves like Or.
- */
- ir_tarval* const low_zero_mask = tarval_or(no_c_in_no_c_out, tarval_neg(no_c_in_no_c_out));
- ir_tarval* const low_one_mask = tarval_not(low_zero_mask);
- z = tarval_or( tarval_or(lz, rz), low_zero_mask);
- o = tarval_and(tarval_or(lo, ro), low_one_mask);
+ case iro_Shr: {
+ bitinfo* const l = get_bitinfo(get_Shr_left(irn));
+ bitinfo* const r = get_bitinfo(get_Shr_right(irn));
+ ir_tarval* const rz = r->z;
+ if (rz == r->o) {
+ z = tarval_shr(l->z, rz);
+ o = tarval_shr(l->o, rz);
+ } else {
+ goto cannot_analyse;
+ }
+ break;
+ }
+
+ case iro_Shrs: {
+ bitinfo* const l = get_bitinfo(get_Shrs_left(irn));
+ bitinfo* const r = get_bitinfo(get_Shrs_right(irn));
+ ir_tarval* const rz = r->z;
+ if (rz == r->o) {
+ z = tarval_shrs(l->z, rz);
+ o = tarval_shrs(l->o, rz);
+ } else {
+ goto cannot_analyse;
+ }
+ break;
+ }
+
+ case iro_Rotl: {
+ bitinfo* const l = get_bitinfo(get_Rotl_left(irn));
+ bitinfo* const r = get_bitinfo(get_Rotl_right(irn));
+ ir_tarval* const rz = r->z;
+ if (rz == r->o) {
+ z = tarval_rotl(l->z, rz);
+ o = tarval_rotl(l->o, rz);
+ } else {
+ goto cannot_analyse;
+ }
+ break;