+ return "oparity_any";
+ }
+ } elsif ($arity == $ARITY_VARIABLE) {
+ return "oparity_variable";
+ } elsif ($arity == $ARITY_DYNAMIC) {
+ return "oparity_dynamic";
+ } else {
+ die "Fatal error: Unknown arity $arity";
+ }
+}
+
+###
+# Return the list of pointers for the given execution units.
+###
+sub gen_execunit_list_initializer {
+ my $units = shift;
+ my $uc_arch = uc($arch);
+ my $ret = "";
+ my $ret2 = "";
+ my %init;
+
+ foreach my $unit (@{ $units }) {
+ if ($unit eq "DUMMY") {
+ push(@{ $init{"DUMMY"} }, "\t\t&be_machine_execution_units_DUMMY[0]");
+ }
+ elsif (exists($cpu{"$unit"})) {
+ # operation can be executed on all units of this type
+ # -> add them all
+ my $tp_name = "$arch\_execution_units_$unit";
+ my $idx = 0;
+ foreach (@{ $cpu{"$unit"} }) {
+ next if ($idx++ == 0); # skip first element (it's not a unit)
+ my $unit_name = "$uc_arch\_EXECUNIT_TP_$unit\_$_";
+ push(@{ $init{"$unit"} }, "\t\t&".$tp_name."[".$unit_name."]");
+ }
+ }
+ else {
+ # operation can be executed only a certain unit
+ # -> find corresponding unit type
+ my $found = 0;
+TP_SEARCH: foreach my $cur_type (keys(%cpu)) {
+ foreach my $cur_unit (@{ $cpu{"$cur_type"} }) {
+ if ($unit eq $cur_unit) {
+ my $tp_name = "$arch\_execution_units_$cur_type";
+ my $unit_name = "$uc_arch\_EXECUNIT_TP_$cur_type\_$unit";
+ push(@{ $init{"$unit"} }, "\t\t&".$tp_name."[".$unit_name."]");
+ $found = 1;
+ last TP_SEARCH;
+ }
+ }
+ }
+
+ if (! $found) {
+ print STDERR "Invalid execution unit $unit specified!\n";
+ }
+ }
+ }
+
+ # prepare the 2-dim array init
+ foreach my $key (keys(%init)) {
+ $ret .= "\tstatic const be_execution_unit_t *allowed_units_".$key."[] =\n";
+ $ret .= "\t{\n";
+ foreach (@{ $init{"$key"} }) {
+ $ret .= "$_,\n";
+ }
+ $ret .= "\t\tNULL\n";
+ $ret .= "\t};\n";
+ $ret2 .= "\t\tallowed_units_$key,\n";
+ }
+ $ret2 .= "\t\tNULL\n";
+
+ $ret .= "\tstatic const be_execution_unit_t **exec_units[] =\n";
+ $ret .= "\t{\n";
+ $ret .= $ret2;
+ $ret .= "\t};\n";
+
+ return $ret;
+}
+
+sub mangle_requirements {
+ my $reqs = shift;
+ my $class = shift;
+ my $flags = shift;
+
+ my @alternatives = split(/ /, $reqs);
+ for(my $idx = 0; $idx < scalar(@alternatives); $idx++) {
+ $alternatives[$idx] =~ s/!/not_/g;
+ }
+
+ @alternatives = sort @alternatives;
+
+ my $name = $class."_".join('_', @alternatives);
+ if (defined($flags)) {
+ $flags =~ s/\|/_/g;
+ $name .= "_$flags";
+ }
+
+ return $name;
+}
+
+###
+# Determines whether $name is a specified register class or not.
+# @return 1 if name is register class, 0 otherwise
+###
+sub is_reg_class {
+ my $name = shift;
+ return 1 if exists($reg_classes{"$name"});
+ return 0;
+}
+
+###
+# Returns the register class for a given register.
+# @return class or undef
+###
+sub get_reg_class {
+ my $reg = shift;
+ $reg = substr($reg, 1) if ($reg =~ /!.*/);
+ return $reg2class{"$reg"}{"class"} if (exists($reg2class{"$reg"}));
+ return undef;
+}
+
+###
+# Returns the index of a given register within its register class.
+# @return index or undef
+###
+sub get_reg_index {
+ my $reg = shift;
+ return $reg2class{"$reg"}{"index"} if (exists($reg2class{"$reg"}));
+ return undef;
+}
+
+###
+# Remember the register class for each index in the given requirements.
+# We need this information for requirements like "in_sX" or "out_dX"
+# @return array of classes corresponding to the requirement for each index
+###
+sub build_inout_idx_class {
+ my $n = shift;
+ my $op = shift;
+ my $is_in = shift;
+ my @idx_class;
+
+ my $inout = ($is_in ? "in" : "out");
+
+ if (exists($n->{"reg_req"}{"$inout"})) {
+ my @reqs = @{ $n->{"reg_req"}{"$inout"} };
+
+ for (my $idx = 0; $idx <= $#reqs; $idx++) {
+ my $class = undef;
+ my ($req,) = split(/:/, $reqs[$idx]);
+
+ if ($req eq "none") {
+ $class = "none";
+ } elsif (is_reg_class($req)) {
+ $class = $req;
+ } else {
+ my @regs = split(/ /, $req);
+GET_CLASS: foreach my $reg (@regs) {
+ if ($reg =~ /!?(in|out)\_r\d+/ || $reg =~ /!in/) {
+ $class = "UNKNOWN_CLASS";
+ } else {
+ $class = get_reg_class($reg);
+ if (!defined $class) {
+ die("Fatal error: Could not get ".uc($inout)." register class for '$op' pos $idx (reg $reg) ... exiting.\n");
+ } else {
+ last GET_CLASS;
+ } # !defined class
+ } # if (reg =~ ...
+ } # foreach
+ } # if
+
+ push(@idx_class, $class);
+ } # for
+ } # if
+
+ return @idx_class;
+}
+
+###
+# Generates the function for a given $op and a given IN-index
+# which returns a subset of possible register from a register class
+# @return classname from which the subset is derived or undef and
+# pos which corresponds to in/out reference position or undef
+###
+sub build_subset_class_func {
+ my $neg = undef;
+ my $class = undef;
+ my $has_limit = 0;
+ my $limit_name;
+ my $same_pos = 0;
+ my $different_pos = 0;
+ my $temp;
+ my @obst_init;
+ my @obst_limits;
+ my @obst_ignore;
+ my @limit_array;
+ my $limit_reqs; #used for name mangling
+
+ # build function header
+ my $node = shift;
+ my $op = shift;
+ my $idx = shift;
+ my $is_in = shift;
+ my @regs = split(/ /, shift);
+ my $flags = shift;
+
+ my @idx_class = build_inout_idx_class($node, $op, !$is_in);
+
+ # set/unset registers
+CHECK_REQS: foreach (@regs) {
+ if (!$is_in && /(!)?in_r(\d+)/) {
+ my $bit_pos = 1 << ($2 - 1);
+ if ($different_pos & $bit_pos) {
+ if ($1) {
+ print STDERR "duplicate !in constraint\n";
+ } else {
+ print STDERR "conflicting !in and in constraints\n";
+ }
+ return (undef, undef, undef, undef);
+ }
+
+ if ($same_pos & $bit_pos) {
+ if ($1) {
+ print STDERR "conflicting !in and in constraints\n";
+ } else {
+ print STDERR "duplicate in constraint\n";
+ }
+ return (undef, undef, undef, undef);
+ }
+
+ if ($1) {
+ $different_pos |= $bit_pos;
+ } else {
+ $same_pos |= $bit_pos;
+ }
+
+ $class = $idx_class[$2 - 1];
+ next CHECK_REQS;
+ }
+
+ # check for negate
+ if (substr($_, 0, 1) eq "!") {
+ if (defined($neg) && $neg == 0) {
+ # we have seen a positiv constraint as first one but this one is negative
+ # this doesn't make sense
+ print STDERR "Mixed positive and negative constraints for the same slot are not allowed.\n";
+ return (undef, undef, undef, undef);
+ }
+
+ if (!defined($neg)) {
+ $has_limit = 1;
+ }
+
+ $_ = substr($_, 1); # skip '!'
+ $neg = 1;
+ } else {
+ if (defined($neg) && $neg == 1) {
+ # we have seen a negative constraint as first one but this one is positive
+ # this doesn't make sense
+ print STDERR "Mixed positive and negative constraints for the same slot are not allowed.\n";
+ return (undef, undef, undef, undef);
+ }
+
+ $has_limit = 1;
+ $neg = 0;
+ }
+
+ # check if register belongs to one of the given classes
+ $temp = get_reg_class($_);
+ if (!defined($temp)) {
+ print STDERR "Unknown register '$_'!\n";
+ return (undef, undef, undef, undef);
+ }
+
+ # set class
+ if (!defined($class)) {
+ $class = $temp;
+ } elsif ($class ne $temp) {
+ # all registers must belong to the same class
+ print STDERR "Registerclass mismatch. '$_' is not member of class '$class'.\n";
+ return (undef, undef, undef, undef);
+ }
+
+ # calculate position inside the initializer bitfield (only 32 bits per
+ # element)
+ my $regidx = get_reg_index($_);
+ my $arrayp = $regidx / 32;
+ push(@{$limit_array[$arrayp]}, $_);
+ $limit_reqs .= "$_ ";
+ }
+
+ # don't allow ignore regs in negative constraints
+ if($neg) {
+ my @cur_class = @{ $reg_classes{"$class"} };
+ for (my $idx = 0; $idx <= $#cur_class; $idx++) {
+ if (defined($cur_class[$idx]{"type"}) && ($cur_class[$idx]{"type"} & 4)) {
+ my $reg = $cur_class[$idx]{"name"};
+ my $regix = get_reg_index($reg);
+ my $arrayp = $regix / 32;
+ push(@{$limit_array[$arrayp]}, $reg);
+ $limit_reqs .= "$reg ";
+ }
+ }
+ }
+
+ if ($has_limit == 1) {
+ $limit_name = "${arch}_limit_".mangle_requirements($limit_reqs, $class);
+
+ if(defined($limit_bitsets{$limit_name})) {
+ $limit_name = $limit_bitsets{$limit_name};
+ return ($class, $limit_name, $same_pos, $different_pos);
+ }
+
+ $limit_bitsets{$limit_name} = $limit_name;
+
+ push(@obst_limit_func, "static const unsigned " . $limit_name . "[] = { ");
+ my $first = 1;
+ my $limitbitsetlen = $regclass2len{$class};
+ my $limitarraylen = ($limitbitsetlen+31) / 32;
+ for(my $i = 0; $i < $limitarraylen; $i++) {
+
+ my $limitarraypart = $limit_array[$i];
+ if($first) {
+ $first = 0;
+ } else {
+ push(@obst_limit_func, ", ");
+ }
+ my $temp;
+ if($neg) {
+ $temp = "0xFFFFFFFF";
+ }
+ foreach my $reg (@{$limitarraypart}) {
+ if($neg) {
+ $temp .= " & ~";
+ } elsif(defined($temp)) {
+ $temp .= " | ";
+ }
+ my $firstreg = uc($reg_classes{$class}[0]->{"name"});
+ my $classuc = uc($class);
+ my $reguc = uc($reg);
+ $temp .= "BIT(REG_${classuc}_${reguc})";
+ }
+ if(defined($temp)) {
+ push(@obst_limit_func, "${temp}");
+ } else {
+ push(@obst_limit_func, "0");
+ }
+ }
+ push(@obst_limit_func, " };\n");
+ }
+
+ return ($class, $limit_name, $same_pos, $different_pos);
+}
+
+###
+# Generate register requirements structure
+###
+sub generate_requirements {
+ my ($reqs, $flags) = split(/:/, shift);
+ my $node = shift;
+ my $op = shift;
+ my $idx = shift;
+ my $is_in = shift;
+ my $class = "";
+ my $width = 1;
+ my $result;
+
+ my @req_type_mask;
+ if (defined($flags)) {
+ foreach my $f (split(/|/, $flags)) {
+ if ($f eq "I") {
+ push(@req_type_mask, "arch_register_req_type_ignore");
+ } elsif ($f eq "S") {
+ push(@req_type_mask, "arch_register_req_type_produces_sp");
+ } elsif ($f eq "a") {
+ push(@req_type_mask, "arch_register_req_type_aligned");
+ } elsif ($f eq "2" or $f eq "4" or $f eq "8") {
+ $width = int($f);
+ }